Large Scale Integration Fabrication Research Articles

Efficient three-dimensional resist profile-driven source mask optimization optical proximity correction based on Abbe-principal component analysis and Sylvester equation

As one of the critical stages of a very large scale integration fabrication process, postexposure bake (PEB) plays a crucial role in determining the final three-dimensional (3-D) profiles and lessening the standing wave effects. However, the full 3-D chemically amplified resist simulation is not widely adopted during the postlayout optimization due to the long run-time and huge memory usage. An efficient simulation method is proposed to simulate the PEB while considering standing wave effects and resolution enhancement techniques, such as source mask optimization and subresolution assist features based on the Sylvester equation and Abbe-principal component analysis method. Simulation results show that our algorithm is 20× faster than the conventional Gaussian convolution method.

Ion sources for ion implantation technology (invited)

Ion sources for ion implantation are introduced. The technique is applied not only to large scale integration (LSI) devices but also to flat panel display. For LSI fabrication, ion source scheduled maintenance cycle is most important. For CMOS image sensor devices, metal contamination at implanted wafer is most important. On the other hand, to fabricate miniaturized devices, cluster ion implantation has been proposed to make shallow PN junction. While for power devices such as silicon carbide, aluminum ion is required. For doping processes of LCD fabrication, a large ion source is required. The extraction area is about 150 cm × 10 cm, and the beam uniformity is important as well as the total target beam current.

High-Performance Gate-First Epitaxial Ge n-MOSFETs on Si With $\hbox{LaAlO}_{3}$ Gate Dielectrics

This brief presents high-performance Ge n-MOSFETs with good high-field mobility of 218 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /V · s at 0.5 MV/cm, low subthreshold swing (SS) of 108 mV/dec, small equivalent oxide thickness (EOT) of 1.6 nm, low 7 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-10</sup> A/μm OFF-state leakage, small bias temperature instability of 31 mV at 1.2 V overdrive and 85°C, and full process compatibility with current very large-scale integration fabrication. These are one of the best SS and high-field mobility data among gate-first Ge n-MOSFETs using epitaxial Ge on 6-in Si wafer and proper high-κ LaAlO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> dielectric without using an interfacial layer. Using a different high-κ HfAlO gate dielectric, the Ge n-MOSFETs showed poor leakage, large flatband voltage shift, and degraded EOT.

Evaluation of Stress and Crystal Quality in Si During Shallow Trench Isolation by UV-Raman Spectroscopy

Defects and stress gradually accumulate throughout various Si large-scale integration fabrication processes. It is essential to monitor defects and stress carefully to suppress their unintentional introduction. In this study, we measured the stress and crystal quality in shallow trench isolation (STI) samples by ultraviolet (UV)-Raman spectroscopy with an extremely high-resolution wavenumber to evaluate the effect of post-annealing on the recovery of Si crystals. The variations of crystal quality in 200-mm wafers with STI structures gradually decreased after post-annealing for 4 h, 6 h, and 8 h; however, there was no substantial difference in the values of full-width at half-maximum of the Raman spectra. Precise measurements of variations of stress and crystal quality were successfully performed by UV-Raman spectroscopy with a high-resolution wavenumber, which enabled us to evaluate the STI process accurately.

Low-Threshold-Voltage MoN/HfAlO/SiON p-MOSFETs With 0.85-nm EOT

By using HfAlO as a capping layer on SiON, MoN/HfAlO/SiON p-MOSFETs show an effective work function of 5.1 eV, a low threshold voltage of -0.1 V, and a peak hole mobility of 80 cm2/(Vmiddots) at small equivalent oxide thickness of 0.85 nm. These self-aligned and gate-first p-MOSFETs processes, with standard ion implantation and 1000degC rapid thermal annealing, are fully compatible with current very large scale integration fabrication lines.

Hotspot management and its applications in ultralow &lt;inline-formula&gt;&lt;math display="inline" overflow="scroll"&gt;&lt;msub&gt;&lt;mi mathvariant="normal"&gt;k&lt;/mi&gt;&lt;mn&gt;1&lt;/mn&gt;&lt;/msub&gt;&lt;/math&gt;&lt;/inline-formula&gt; lithography

We have constructed a hotspot management flow and applied the flow to large-scale integration (LSI) manufacturing in the ultralow k1 lithography era. This flow involves three main management steps: hotspot reduction, hotspot extraction, and hotspot monitoring. Hotspot reduction works with lithography-friendly restricted design rule (RDR) and manufacturability check (MC). Hotspot extraction is carried out with a view to realizing short operation time and accurate extraction. Hotspot monitoring is achieved with tolerance-based verification in the mask fabrication process and wafer process (lithography and etching). These technology elements could be integrated into the LSI fabrication flow for reduction of total cost, quick turnaround time (TAT), and ramp-up to volume production. In addition to discussion of the technology elements in hotspot management, we also provide typical applications for important decisions in LSI fabrication: photomask availability for any exposure tools ("exposure tool yokoten") and process condition updates in LSI fabrication.

HfLaON n-MOSFETs Using a Low Work Function $ \hbox{HfSi}_{x}$ Gate

At a 1.2-nm equivalent oxide thickness, HfSi <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> /Hf <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.7</sub> La <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.3</sub> ON n-MOSFETs showed an effective work function of 4.33 eV, a low threshold voltage of 0.18 V, and a peak electron mobility of 215 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /(Vldrs). These self-aligned and gate-first HfSi <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> /Hf <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.7</sub> La <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.3</sub> ON n-MOSFETs were processed using standard ion implantation and 1000-degC rapid thermal annealing, making them fully compatible with current very large scale integration fabrication lines.

High-Temperature Stable HfLaON p-MOSFETs With High-Work-Function $\hbox{Ir}_{3}\hbox{Si}$ Gate

We report a novel 1000 degC stable HfLaON p-MOSFET with Ir3 Si gate. Low leakage current of 1.8times10-5 A/cm2 at 1 V above flat-band voltage, good effective work function of 5.08 eV, and high mobility of 84 cm2/Vmiddots are simultaneously obtained at 1.6 nm equivalent oxide thickness. This gate-first p-MOSFET process with self-aligned ion implant and 1000 degC rapid thermal annealing is fully compatible to current very large scale integration fabrication lines

HfSiON n-MOSFETs Using Low-Work Function$hboxHfSi_x$Gate

The authors have developed a novel high-temperature stable HfSi x gate for high-kappa HfSiON gate dielectric. After a 1000 degC RTA, the HfSix/HfSiON devices showed an effective work function of 4.27 eV and a peak electron mobility of 216 cm2/Vmiddots at 1.6-nm equivalent oxide thickness, with additional merit of a process compatible with current very large scale integration fabrication lines

HfAlON n-MOSFETs incorporating low-work function gate using ytterbium silicide

The authors have fabricated low-temperature fully silicided YbSi/sub 2-x/-gated n-MOSFETs that used an HfAlON gate dielectric with a 1.7-nm EOT. After a 600 /spl deg/C rapid thermal annealing, these devices displayed an effective work function of 4.1 eV and a peak electron mobility of 180 cm/sup 2//V/spl middot/s. They have additional merit of a process compatible with current very large scale integration fabrication lines.

History of extreme ultraviolet lithography

Extreme ultraviolet lithography (EUVL) technology was proposed and progressed on both hemispheres in the latter part of the 1980s, independently. Although this technology is a design using a catoptric system instead of refraction lens and the accuracy of subnanometer is demanded for all component engineering, the research and development of Japan and the United States has led to significant breakthroughs in processing and measurement technology over the past 20 years. EUVL is now the most promising next-generation technology for large scale integration fabrication. This article discusses the beginnings of EUVL, what advances are needed, and future prospects.

Experimental Study of the Degradation of Mechanical Strength of Silicon Wafers Caused by Large Scale Integration Processes

The historical change of mechanical strength of silicon wafer during the large scale integration (LSI) fabrication process has been studied. It was confirmed that the major factor which determines the strength of the bulk crystal is the bulk microdefect (BMD) density in the metal oxide semiconductor field effect transistor fabrication process with local oxidation of silicon (LOGOS) isolation. Unfortunately, the LOGOS fabrication process increases the BMD density and reduces the wafer strength. Further, this study revealed that the ion implantation process induces the most serious degradation of the mechanical strength in the surface region of the Si substrate in the LSI fabrication processes. Whether or not this deterioration in strength is recovered depends on the status of ion implantation and the method of subsequent annealing. The deterioration of strength was caused by ion implantation due to the effect of interstitial silicon atoms and their clusters in a low dose situation (<1014 cm−2), and the amorphous layer or surface roughness in a high dose condition (>1015 cm−2). In order to reduce the crystal defects or wafer‐slips, attention should be paid to the procedural steps which cause reduction in the mechanical strength of silicon crystals while designing the LSI fabrication process.

Control of etching-product-dependent shape and selectivity in gate polysilicon reactive ion etching

In polycrystalline silicon (polysilicon) etching for gate electrodes in high-performance complementary metal-oxide-semiconductor large scale integration fabrication, extremely high selectivity of polysilicon etching to the gate oxide is needed because the thickness of the gate oxide reduces. It is also important to overcome the well-known shape distortion problem, called “notching” or “local side etching,” where the gate side-wall is locally side-etched at the interface between the polysilicon and the gate oxide. We examine the origin of notching and the selectivity to the gate oxide in chlorine- and oxygen-based reactive ion etching of the phosphorous-doped polysilicon gate with an SiO2 hard mask. It is found that the etching product returning to the surface plays an important role in both side-wall and gate-oxide protection, which determines the shape of the electrode and the selectivity. Based on our findings, we developed a novel step-etching method that provides high-performance gate electrode etching that is infinitely selective without notching. This method uses the addition of a SiCl4 gas, which is equivalent to the etching product, as well as oxygen during overetching when the generation of etching product is reduced.

Niobium nitride Josephson junction process development

NbN/MgO/NbN tunnel junction fabrication has been developed using statistical experimental design for insertion into a Josephson LSI (large-scale integration) fabrication technology. Junction deposition conditions have been studied and correlated with structural characterization and junction I-V measurements. Josephson junctions with sum gaps as large as 5.0 mV and junction quality factor of 47 mV have been produced. Current density uniformity, a critical parameter in circuit design, has also been investigated. I/sub c/(O) uniformity at 4.2 K of a 4000 junction array was within sigma =3.1% and was +or-10% across 1 in/sup 2/. The utility of this junction process has been demonstrated by insertion into a standard circuit fabrication process that has produced logic circuit operation above 10 K.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Electron optics for high throughput electron beam lithography system

A new electron optical column has been designed for cell projection method involving 0.2 μm large scale integration fabrication. Assuming a resist sensitivity of 1 μC/cm2 and a deflection settling time of 100 nsec, the maximum shot length is optimized to 5 μm. The objective lens system has two magnetic lenses and one magnetic deflector, and the lens system size enlargement effect has been investigated to deflect the beam up to 5 mm square field. As a result, beam edge resolution under 0.07 μm and shaped beam distortion under 0.01 μm have been achieved. In order to reduce the practical settling time, a three stage deflection system has been adopted.

Observations on aluminum diffusion and its effect on the specific contact resistance of Al/W/Si ohmic contact

This paper describes the observation of aluminum diffusion into the silicon base of Al/W/Si ohmic contacts during aluminum annealing, and its effect on the ohmic property of the contact. The contacts are prepared by plasma-deposition of tungsten, then sequential evaporation of aluminum on n + and p + silicon substrates. The contacts were examined by specific contact resistance measurement, I/V characteristic measurement, Rutherford backscattering spectroscopy (RBS) and X-ray diffraction analysis. RBS showed that, at 500°C annealing, the aluminum diffusion was small, but it became evident after 600°C annealing. However, very low specific contact resistance and good ohmic characteristics were found in the samples annealed at 600°C. Thus we conclude that the aluminum annealing in very large scale integration fabrication does not significantly affect the ohmic characteristics of the Al/W/Si contact.