Large Scale Field Programmable Gate Research Articles

Simplified digital coherent-based beyond-100G optical access systems for B5G/6G [Invited

In this paper, we review the latest progress in the simplified digital coherent technologies suitable for future beyond-100G optical access systems, which will be a key optical transport platform for meeting the very wide range of extreme requirements of beyond-5G (B5G) and 6G users. As the centerpiece of beyond-100G optical access systems, the technical challenges and recent demonstrations of ultimate-capacity passive optical network systems carrying more than 100 Gb/s per wavelength by using simplified digital coherent technologies incorporating low-complexity digital signal processing (DSP) are presented. In addition, to facilitate the implementation of these relatively large-scale digital coherent technologies in the optical access area, which has strict cost, power consumption, and size restraints, the rapid progress in compact optical transceiver form factors and optical devices heading toward 400 Gb/s-based Ethernet transceivers for the 80 km range (400G-ZR) and over 800 Gb/s short-reach applications based on the digital coherent technologies are also discussed. Furthermore, the recent expansion of simplified digital coherent-based optical access systems such as optical space communications and their latest experimental demonstrations are introduced as an alternative evolution of beyond-100G optical access systems, going hand in hand with the reduction of complexity of the real-life digital coherent platforms such as the DSP large-scale integration and the large-scale field programmable gate arrays.

High-performance parallel computing for next-generation holographic imaging

Holography is a method of recording and reproducing three-dimensional (3D) images, and the widespread availability of computers has encouraged the development of holographic 3D screens (electroholography). However, the technology has not yet been used in practical applications because a hologram requires an enormous volume of data and modern computing power is inadequate to process this volume of data in real time. Here, we show that a special-purpose holography computing board, which uses eight large-scale field-programmable gate arrays, can be used to generate 108-pixel holograms that can be updated at a video frame rate. With our approach, we achieve a parallel operation of 4,480 hologram calculation circuits on a single board, and by clustering eight of these boards, we can increase the number of parallel calculations to 35,840. Using a 3D image composed of 7,877 points, we show that 108-pixel holograms can be updated at a video rate, thus allowing 3D movies to be projected. We also demonstrate that the system speed scales up in a linear manner as the number of parallel circuits is increased. The system operates at 0.25 GHz with an effective speed equivalent to 0.5 petaflops (1015 floating-point operations per second), matching that of a high-performance computer. A special-purpose holography computing board, which uses eight large-scale field-programmable gate arrays, can be used to generate 108-pixel holograms that can be updated at a video frame rate.

EVALUATION STUDY OF SYSTOLIC ARRAY PROCESSORS OPTIMIZATION AND MAPPING ON k-LUT FPGA DEVICES

This paper analyzes the design automation of embedded Systolic Array Processors (SAPs), into large scale Field Programmable Gate Array (FPGA) devices. SAPs are hardware implementations of a class of iterative, high-level language algorithms, for applications where the high-speed of processing has the principal meaning of a design. Embedding SAPs onto FPGAs is a complex process. The optimization phase in this process reduces the SAP significantly, thus less FPGA area is occupied by the embedded design, without any loss in the final performance. The present paper examines the effect of Projection Vectors (PVs) and Task Scheduling Vectors (TSVs) on the optimization process. Two optimization approaches are examined, namely technology mapping using FlowMap and Flowpack algorithms and optimization via logic synthesis using Xilinx Synthesis Tool. The multiplication of matrices, with entries being up to 32-bit integer vectors, has been taken as a sample space for the experiments conducted. The results, confirm that the selection of PV and TSV greatly affects the number of input/output signal connections of the FPGA, while the selection of an optimization approach affects the final number of logic resources occupied on the targeted device.

超高速高性能门控型三分幅相机

Aiming at the framing photography frequency of about 108 frame/s or above,a kind of 3-frame framing camera with ultra high-speed and high performance is developed and put into operation.The optical principle of the camera is based on splitting the focused imaging light beam in the field of image space.It features good imaging quality and high light energy efficiency.The lens coupled gated image intensifier with high speed shutter control ability,cooled scientific CCD camera and the high speed controller based on large scale field programmable gate array with system trigger and shutter trigger are the main portions.This framing camera can capture 3frame images with ultrahigh speed of above 3.3×108 frame/s.The minimum exposure time for each image is about 3ns and can be independently setup in a wide range of from several ns to s.The frame interval time can also be adjusted at discretion step from 0ns to second level.The effective image size isΦ25mm and image array is 1 024×1 024.The spatial resolution is about 30lp/mm.The framing camera features good linearity,good response uniformity,and excellent flexibility in applications.

Modeling, validation, and co-design of IBM Blue Gene/Q: Tools and examples

Major architectural innovations in the compute node have been introduced in the IBM Blue Gene®/Q, including programmable Level 1 (L1) cache data prefetching units to hide memory access latency, hardware support for transactional memory (TM) and speculative execution (SE), an enhanced five-dimensional integrated torus network, and a high-performance quad floating-point SIMD (single-instruction, multiple-data) unit. In this paper, we present the tools and methodology that we used to model, co-design, and validate these new features from early concept phase through design implementation. Early in the design cycle, we made extensive use of an architectural simulator, BGQSim, capable of executing unmodified binary Blue Gene/Q code for single as well as multiple nodes. As the hardware description language for the chip implementation became available, we complemented BGQSim with a cycle-accurate and cycle-reproducible, large-scale field-programmable gate array-based platform, Twinstar, to validate the implementation against performance targets and functional specifications. Through specific examples, we show the effectiveness of these tools in co-developing the hardware and software of Blue Gene/Q, allowing us to meet the design targets at an aggressive project schedule.

Using combinational logic function to watermark IP based on FPGA

In the field of digital circuit design, the extensive applications of reusable intellectual property (IP) simplify the design procedure based on very large scale field programmable gate array (FPGA), and shorten the time to market (TTM). However, the flexibility of reusable IP makes itself easy to be stolen and illegally distributed by intruders. The protection method proposed in this paper maps IP owner's signature to combinational logic functions, and then implements these functions into unused lookup tables (LUTs) in the design based on FPGA, which can be used as a strong proof of IPs ownership. The related experiment results show that this protection method has favorable characteristics such as low overhead, few effects on performance, and high security.

Special-purpose computer HORN-5 for a real-time electroholography

In electroholography, a real-time reconstruction is one of the grand challenges. To realize it, we developed a parallelized high performance computing board for computer-generated hologram, named HORN-5 board, where four large-scale field programmable gate array chips were mounted. The number of circuits for hologram calculation implemented to the board was 1,408. The board calculated a hologram at higher speed by 360 times than a personal computer with Pentium4 processor. A personal computer connected with four HORN-5 boards calculated a hologram of 1,408 x 1,050 made from a three-dimensional object consisting of 10,000 points at 0.0023 s. In other words, beyond at video rate (30 frames / s), it realized a real-time reconstruction.