Large Code Size Research Articles

C vs Python: A Cursory Look with Industry Opinion

In this paper, the author explores the characteristics and applications of C & Python programming languages across various industries, drawing insights from interviews with professionals. The study includes a comparative analysis of C and Python based on execution time, code readability, and length. C, favored for its speed and applicability in game development and embedded systems, has complexities such as large code size and lack of cross-platform support. In contrast, Python excels in artificial intelligence, machine learning, and web scraping due to its simplicity and extensive libraries. The article emphasizes the influence of programming communities on language popularity, noting Python's widespread adoption due to its concise syntax and strong community support. Industry experts concur on C's complexity and time-intensive nature but acknowledge its effectiveness. Python's ease of learning has made it the world's most widely used language, prompting non-coding sectors to encourage Python education.

Improved Basic Block Reordering

Basic block reordering is an important step for profile-guided binary optimization. The state-of-the-art goal for basic block reordering is to maximize the number of fall-through branches. However, we demonstrate that such orderings may impose suboptimal performance on instruction and I-TLB caches. We propose a new algorithm that relies on a model combining the effects of fall-through and caching behavior. As details of modern processor caching is quite complex and often unknown, we show how to use machine learning in selecting parameters that best trade off different caching effects to maximize binary performance. An extensive evaluation on a variety of applications, including Facebook production workloads, the open-source compilers Clang and GCC, and SPEC CPU benchmarks, indicate that the new method outperforms existing block reordering techniques, improving the resulting performance of applications with large code size. We have open sourced the code of the new algorithm as a part of a post-link binary optimization tool, BOLT.

Engineering faster sorters for small sets of items

AbstractSorting a set of items is a task that can be useful by itself or as a building block for more complex operations. That is why a lot of effort has been put into finding sorting algorithms that sort large sets as efficiently as possible. But the more sophisticated and complex the algorithms become, the less efficient they are for small sets of items due to large constant factors. A relatively simple sorting algorithm that is often used as a base case sorter is insertion sort, because it has small code size and small constant factors influencing its execution time. We aim to determine if there is a faster way to sort small sets of items to provide an efficient base case sorter. We looked at sorting networks, at how they can improve the speed of sorting few elements, and how to implement them in an efficient manner using conditional moves. Since sorting networks need to be implemented explicitly for each set size, providing networks for larger sizes becomes less efficient due to increased code sizes. To also enable the sorting of slightly larger base cases, we adapted sample sort to Register Sample Sort, to break down those larger sets into sizes that can in turn be sorted by sorting networks. From our experiments we found that when sorting only small sets of integers, the sorting networks outperform insertion sort by a factor of at least 1.76 for any array size between six and 16, and by a factor of 2.72 on average across all machines and array sizes. When integrating sorting networks as a base case sorter into Quicksort, we achieved far less performance improvements over using insertion sort, which is probably due to the networks having a larger code size and cluttering the L1 instruction cache. The same effect occurs when including Register Sample Sort as a base case sorter for IPSo. But for x86 machines that have a larger L1 instruction cache of 64 KiB or more, we obtained speedups of 12.7% when using sorting networks as a base case sorter in std::sort, and of 5%–6% when integrating Register Sample Sort as a base case sorter into IPSo, each in comparison to using insertion sort as the base case sorter. In conclusion, the desired improvement in speed could only be achieved under special circumstances, but the results clearly show the potential of using conditional moves in the field of sorting algorithms.

Improving Fault-Localization Accuracy by Referencing Debugging History to Alleviate Structure Bias in Code Suspiciousness

Spectrum-based fault localization (SBFL) techniques can automatically localize software faults. They employ the program spectrum, such as code coverage profile with test verdicts, to rank the program entities based on their code suspiciousness. In the past decades, researchers have proposed many approaches to optimize these techniques; however, the program structure, which can influence their performance, is not taken into consideration in developing and improving these techniques. In this article, we identify and analyze the effect of the program structure on the application of SBFL techniques. We observe that some specific program structures may introduce structure bias to code suspiciousness and negatively influence the output of SBFL techniques. To mitigate these effects and improve the performance of fault localization, we propose Delta4Ts, a structure-aware technique. Delta4Ts references debugging history to alleviate the impact of structure bias in the calculation of code suspiciousness. It reasons from the observable suspicious value towards the desired suspicious value and the impact of structure bias. To evaluate Delta4Ts under practical constraints, we conduct a controlled experiment using nine widely-studied SBFL formulae on 12 C programs and 6 Java programs. The experiment results show that Delta4Ts can significantly improve the accuracy of the studied SBFL formulae by an average of 34.8% on 12 C programs and 30.6% on 6 Java programs, and improve more on subject programs associated with more history versions or having larger code sizes.

A Lightweight Assisted Vulnerability Discovery Method Using Deep Neural Networks

Thousands of vulnerabilities are discovered in programs every day, which is extremely harmful to software security. Thus, discovering vulnerabilities in projects has become a central issue. Facing a sustained growth of software complexity and large code size, manual code auditing becomes time-consuming and labor-intensive. With more open source programs available and a high degree of code formalization, it is possible to study features from source code to guide vulnerability discovery work. In this paper, we present a lightweight-assisted vulnerability discovery method using a deep neural network (LAVDNN) to detect weakness and to provide guidance for manual auditing. The method proposed in this paper leverages function names as semantics features to uncover weak functions in large-scale open source programs. First, we extract function names and classify into weak and benign datasets. Then, we construct deep neural networks and compare the performances of different models. According to the experimental results, our method performs well for both C/C++ and Python programs, with the $F_{2}$ -score reaching 0.91 and 0.915, respectively. Ultimately, we evaluate the method by comparing with other approaches using the libraries FFmpeg 0.6 and LibTIFF 4.0.6. The results show that the LAVDNN could narrow the range of functions to be analyzed and report more weak functions without any prior vulnerability information. As a lightweight-assisted tool, the LAVDNN significantly reduces the false positive rate and hardly misses weak functions.

Correcting coherent errors with surface codes

Surface codes are building blocks of quantum computing platforms based on 2D arrays of qubits responsible for detecting and correcting errors. The error suppression achieved by the surface code is usually estimated by simulating toy noise models describing random Pauli errors. However, Pauli noise models fail to capture coherent processes such as systematic unitary errors caused by imperfect control pulses. Here we report the first large-scale simulation of quantum error correction protocols based on the surface code in the presence of coherent noise. We observe that the standard Pauli approximation provides an accurate estimate of the error threshold but underestimates the logical error rate in the sub-threshold regime. We find that for large code size the logical-level noise is well approximated by random Pauli errors even though the physical-level noise is coherent. Our work demonstrates that coherent effects do not significantly change the error correcting threshold of surface codes. This gives more confidence in the viability of the fault-tolerance architecture pursued by several experimental groups.

High-Threshold Low-Overhead Fault-Tolerant Classical Computation and the Replacement of Measurements with Unitary Quantum Gates.

von Neumann's classic "multiplexing" method is unique in achieving high-threshold fault-tolerant classical computation (FTCC), but has several significant barriers to implementation: (i)the extremely complex circuits required by randomized connections, (ii)the difficulty of calculating its performance in practical regimes of both code size and logical error rate, and (iii)the (perceived) need for large code sizes. Here we present numerical results indicating that the third assertion is false, and introduce a novel scheme that eliminates the two remaining problems while retaining a threshold very close to von Neumann's ideal of 1/6. We present a simple, highly ordered wiring structure that vastly reduces the circuit complexity, demonstrates that randomization is unnecessary, and provides a feasible method to calculate the performance. This in turn allows us to show that the scheme requires only moderate code sizes, vastly outperforms concatenation schemes, and under a standard error model a unitary implementation realizes universal FTCC with an accuracy threshold of p<5.5%, in which p is the error probability for 3-qubit gates. FTCC is a key component in realizing measurement-free protocols for quantum information processing. In view of this, we use our scheme to show that all-unitary quantum circuits can reproduce any measurement-based feedback process in which the asymptotic error probabilities for the measurement and feedback are (32/63)p≈0.51p and 1.51p, respectively.

Binary Embedding with Additive Homogeneous Kernels

Binary embedding transforms vectors in Euclidean space into the vertices of Hamming space such that Hamming distance between binary codes reflects a particular distance metric. In machine learning, the similarity metrics induced by Mercer kernels are frequently used, leading to the development of binary embedding with Mercer kernels (BE-MK) where the approximate nearest neighbor search is performed in a reproducing kernel Hilbert space (RKHS). Kernelized locality-sensitive hashing (KLSH), which is one of the representative BE-MK, uses kernel PCA to embed data points into a Euclidean space, followed by the random hyperplane binary embedding. In general, it works well when the query and data points in the database follow the same probability distribution. The streaming data environment, however, continuously requires KLSH to update the leading eigenvectors of the Gram matrix, which can be costly or hard to carry out in practice. In this paper we present a completely randomized binary embedding to work with a family of additive homogeneous kernels, referred to as BE-AHK. The proposed algorithm is easy to implement, built on Vedaldi and Zisserman's work on explicit feature maps for additive homogeneous kernels. We show that our BE-AHK is able to preserve kernel values by developing an upper- and lower-bound on its Hamming distance, which guarantees to solve approximate nearest neighbor search efficiently. Numerical experiments demonstrate that BE-AHK actually yields similarity-preserving binary codes in terms of additive homogeneous kernels and is superior to existing methods in case that training data and queries are generated from different distributions. Moreover, in cases where a large code size is allowed, the performance of BE-AHK is comparable to that of KLSH in general cases.

Simple scheme for encoding and decoding a qubit in unknown state for various topological codes.

We present a scheme for encoding and decoding an unknown state for CSS codes, based on syndrome measurements. We illustrate our method by means of Kitaev toric code, defected-lattice code, topological subsystem code and 3D Haah code. The protocol is local whenever in a given code the crossings between the logical operators consist of next neighbour pairs, which holds for the above codes. For subsystem code we also present scheme in a noisy case, where we allow for bit and phase-flip errors on qubits as well as state preparation and syndrome measurement errors. Similar scheme can be built for two other codes. We show that the fidelity of the protected qubit in the noisy scenario in a large code size limit is of , where p is a probability of error on a single qubit per time step. Regarding Haah code we provide noiseless scheme, leaving the noisy case as an open problem.

Breakdown of surface-code error correction due to coupling to a bosonic bath

We consider a surface code suffering decoherence due to coupling to a bath of bosonic modes at finite temperature and study the time available before the unavoidable breakdown of error correction occurs as a function of coupling and bath parameters. We derive an exact expression for the error rate on each individual qubit of the code, taking spatial and temporal correlations between the errors into account. We investigate numerically how different kinds of spatial correlations between errors in the surface code affect its threshold error rate. This allows us to derive the maximal duration of each quantum error correction period by studying when the single-qubit error rate reaches the corresponding threshold. At the time when error correction breaks down, the error rate in the code can be dominated by the direct coupling of each qubit to the bath, by mediated subluminal interactions, or by mediated superluminal interactions. For a 2D Ohmic bath, the time available per quantum error correction period vanishes in the thermodynamic limit of a large code size $L$ due to induced superluminal interactions, though it does so only like $1/\sqrt{\log L}$. For all other bath types considered, this time remains finite as $L\rightarrow\infty$.

Modular code generation from synchronous block diagrams

We study modular, automatic code generation from hierarchical block diagrams with synchronous semantics. Such diagrams are the fundamental model behind widespread tools in the embedded software domain, such as Simulink and SCADE. Code is modular in the sense that it is generated for a given composite block independently from context (i.e., without knowing in which diagrams the block is to be used) and using minimal information about the internals of the block. In previous work, we have shown how modular code can be generated by computing a set of interface functions for each block and a set of dependencies between these functions that is exported along with the interface. We have also introduced a quantified notion of modularity in terms of the number of interface functions generated per block, and showed how to minimize this number, which is essential for scalability. Finally, we have exposed the fundamental trade-off between modularity and reusability (set of diagrams the block can be used in). In this paper we explore another trade-off: modularity vs. code size. We show that our previous technique, although it achieves maximal reusability and is optimal in terms of modularity, may result in code replication and therefore large code sizes, something often unacceptable in an embedded system context. We propose to remedy this by generating code with no replication, and show that this generally results in some loss of modularity. We show that optimizing modularity while maintaining maximal reusability and zero replication is an intractable problem (NP-complete). We also show that this problem can be solved using a simple iterative procedure that checks satisfiability of a sequence of propositional formulas. We report on a new prototype implementation and experimental results. The latter demonstrate the practical interest in our methods.

Merged Dictionary Code Compression for FPGA Implementation of Custom Microcoded PEs

Horizontal Microcoded Architecture (HMA) is a paradigm for designing programmable high-performance processing elements (PEs). However, it suffers from large code size, which can be addressed by compression. In this article, we study the code size of one of the new HMA-based technologies called No-Instruction-Set Computer (NISC). We show that NISC code size can be several times larger than a typical RISC processor, and we propose several low-overhead dictionary-based code compression techniques to reduce its code size. Our compression algorithm leverages the knowledge of “don't care” values in the control words and can reduce the code size by 3.3 times, on average. Despite such good results, as shown in this article, these compression techniques lead to poor FPGA implementations because they require many on-chip RAMs. To address this issue, we introduce an FPGA-aware dictionary-based technique that uses the dual-port feature of on-chip RAMs to reduce the number of utilized block RAMs by half. Additionally, we propose cascading two-levels of dictionaries for code size and block RAM reduction of large programs. For an MP3 application, a merged, cascaded, three-dictionary implementation reduces the number of utilized block RAMs by 4.3 times (76%) compared to a NISC without compression. This corresponds to 20% additional savings over the best single level dictionary-based compression.

SCALABLE AND EFFICIENT IMPLEMENTATIONS OF THE LDPC DECODER USING RECONFIGURABLE MODELS

In this paper we propose constant-time parallel algorithms for implementing the message-passing decoder of LDPC codes on a two dimensional R-Mesh and an LARPBS. The R-Mesh and LARPBS are dynamically reconfigurable models that provide hardware reuse and flexibility to problem changes. The same hardware can implement the decoder in both probability and logarithm domains over different channels. Moreover, to decode an alternate code, we may simply set up the required connections between the bit-nodes and check-nodes by modifying the initialization phase of the proposed algorithms. No extra wiring or hardware changes are required, as compared to other existing approaches. We illustrate that the R-Mesh and the LARPBS are efficient models for parallel implementation of the decoder in terms of time complexity, flexibility to problem changes and simplicity of routing messages. We also demonstrate that it is possible to optimally scale large block code sizes down to a smaller, available machine size if using an LR-Mesh or HVR-Mesh, two variants of the R-Mesh model.

Optical orthogonal codes with large crosscorrelation and their performance bound for asynchronous optical CDMA systems

Optical orthogonal codes (OOCs) are commonly used as signature codes for optical code-division multiple-access (OCDMA) communication systems. Many OOCs have been proposed and investigated. Asynchronous OCDMA systems using conventional OOCs have a very limited number of subscribers and few simultaneous users. Recently, we reported a new code family with large code size by relaxing the crosscorrelation constraint to 2. In this paper, by further loosening the crosscorrelation constraint, we adopt the random greedy algorithm to construct a code family which has larger code size and more simultaneous users. We also derive an upper bound of the number of simultaneous users for a given code length, code weight, and bit error rate. The study shows that it is possible to have codes approaching this bound.

Performance and power evaluation of C++ object-oriented programming in embedded processors

The development of high-performance and lower power portable devices relies on both the underlying hardware architecture and technology as well as on the application software that executes on embedded processor cores. One way to confront the increasing complexity and decreasing time-to-market of embedded software is by means of modular and reusable code, forcing software designers to use objected oriented programming languages such as C++ [6]. However, the object-oriented approach is known to introduce a significant performance penalty compared to classical procedural programming. In this paper, the object oriented programming style is evaluated in terms of both performance and power for embedded applications. Profiling results indicate that C++ programs apart from being slower than their corresponding C versions, consume significantly more energy. Further analysis shows that this is mainly due to the increased instruction count, larger code size and increased number of accesses to the data memory for the object-oriented versions.

Partial-prefix synchronizable codes

A new class of codes for frame synchronization is proposed. Commonly, the beginning of every fixed or variable-length frame is identified by a given contiguous sequence called a prefix. To avoid the occurrence of the prefix elsewhere in the frame, a prefix synchronizable code (PS-code) is used. PS-codes have the property that the prefix does not occur in any codeword or in any concatenation of codewords in any position other than the first position. The new codes, termed partial-prefix synchronizable codes (PPS-codes), use a fixed sequence of symbols that is interspersed with symbols that carry information. The contiguous sequence from the first fixed symbol to the last fixed symbol is called a partial-prefix. Consequently, not one but a set of possible prefixes is used, and none of these prefixes is allowed to occur at any other than the first position of a codeword. The cardinality of PPS-codes is determined, and coding algorithms are proposed which have a computational complexity proportional to the length of the codewords. It is demonstrated that in comparison with PS-codes, PPS-codes have similar coding and prefix detection complexity, but they have a larger code size and have better error control capabilities.

Compact and efficient presentation conversion code

The inefficient presentation conversion code is a major difficulty for using a distributed-applications development environment (such as a CORBA-, Java-RMI-, DCE-, or ASN.1-based environment) to build high-speed network applications. The stub compilers included in these environments generate code that is either very slow or has a large code size. This paper presents a technique for automatically generating compact and efficient presentation conversion code. This is achieved by using a hybrid of two implementation alternatives for presentation conversion routines (interpreted and procedure-driven code). The optimization is modeled as a knapsack problem. A Markov model is used in combination with heuristic branch prediction rules for estimating execution frequencies. An optimization stage based on these ideas was implemented in the ASN.1 compiler Mavros. Experimental evaluation of this implementation shows that investing only 25% of the code size of fully optimized code results in a performance improvement of 55%-68%.

Making compaction-based parallelization affordable

Compaction-based parallelization suffers from long compile time and large code size because of its inherent code explosion problem. If software pipelining is performed for loop parallelization along with compaction, as in the authors' compiler, the code explosion problem becomes more serious. The authors propose the software lookahead heuristic for use in software pipelining, which allows inter-basic-block movement of code within a prespecified number of operations, called the software lookahead window, on any path emanating from the currently processed instruction at compile time. Software lookahead enables instruction-level parallelism to be exploited in a much greater code area than a single basic block, but the lookahead region is still limited to a constant depth by means of a user-specifiable window, and thus code explosion is restricted. The proposed scheme has been implemented in the authors' VLIW parallelizing compiler. To study the code explosion problem and instruction-level parallelism for branch-intensive code, they compiled five AIX utilities: sort, fgrep, sed, yacc, and compress. It is demonstrated that the software lookahead heuristic effectively alleviates the code explosion problem while successfully extracting a substantial amount of inter-basic-block parallelism.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>