Large Capacity Storage System Research Articles

Integrating thermal properties and degradation modelling of batteries into the scheduling of hybrid power plants with photovoltaics

Renewable energy penetration in the energy mix has risen sharply in the last decade, and brought with it an increased deployment of large-capacity storage systems. The result is a need for optimised management strategies that integrate and safely operate the whole energy production chain, including precise models for each element that they control. This paper presents the results of a study on detailed state-of-charge, thermal and degradation modelling of Battery Energy Storage Systems for hybrid photovoltaic-battery power plants. The objective is to quantify the error associated with not taking into account a precise model for these parameters in industrial applications. The use case of optimal battery scheduling in a capacity firming framework and a low-voltage grid is considered to quantify the impact of these models. The proposed models for these parameters were developed and then validated against experimental measures from five hybrid power plants. The models were then applied to calculate optimal battery schedules, and showed lower than expected state-of-health loss values. The impact of including the thermal modelling in the scheduling process was also observed to be weaker than expected.

A 25.6-Gb/s Interface Employing PAM-4-Based Four-Channel Multiplexing and Cascaded Clock and Data Recovery Circuits in Ring Topology for High-Bandwidth and Large-Capacity Storage Systems

This article presents a pulse-amplitude modulation (PAM)-4-based 25.6-Gb/s serial interface for high-bandwidth (BW) and large-capacity storage systems consisting of NAND flash memory. A conventional interface with multi-drop bus topology between the NAND flash memories and their controller has an inevitable tradeoff between BW and capacity if we assume a reasonable PCB design in which the numbers of pins and wires near the NAND controller is limited. Although a daisy-chain-based interface can resolve this tradeoff, it requires the additional overheads of bridge chips and procedures for distinguishing between bridge chips. In order to address these challenges, this article presents three key techniques: 1) ring topology; 2) PAM-4-based four-channel multiplexing; and 3) cascaded clock and data recovery (CDR) circuits with phase-error-dependent bang-bang phase detector (PED-BBPD). The fabricated transceiver for the proposed interface using a 28-nm CMOS process achieves energy efficiency of 3.69 pJ/b at 25.6-Gb/s PRBS31 with a bit error rate (BER) of less than <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$10^{-15}$ </tex-math></inline-formula> through a short channel with 1.84-dB loss. The proposed interface mitigates the overhead of the bridge chips with higher data rate than previous works, and it can achieve a state-of-the-art figure of merit of 1.80 PKG Gb/s/mW, defined as “No. of NAND packages (PKGs) <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times $ </tex-math></inline-formula> data rate/power consumption,” with a controller and four bridge chips.

A 12.8-Gb/s Daisy Chain-Based Downlink I/F Employing Spectrally Compressed Multi-Band Multiplexing for High-Bandwidth, Large-Capacity Storage Systems

Toward the aim of realizing high-bandwidth, large-capacity nand flash memory-based storage systems, this paper presents a novel daisy-chain downlink interface (I/F) between a controller and a large number of nand packages. The daisy-chain I/F employs a tapered-bandwidth architecture with bridge-by-bridge data extraction based on a proposed spectrally compressed multi-band multiplexing (SCM2) technique to achieve low power consumption. By using the proposed downlink I/F, a nand controller can handle 32 low-cost nand packages while achieving 12.8-Gb/s throughput using two data wires. The fabricated prototype downlink I/F achieved a bit error rate (BER) of 10−12 with power consumption of 252.1 mW for the transmitter and 375.7 mW for all four receivers together.

Evaluation and Performance Modeling of a Burst Buffer Solution

Hierarchical storage architectures are required to meet both, capacity and bandwidth requirements for future high-end storage architectures. In this paper we present the results of an evaluation of an emerging technology, DataDirect Networks' (DDN) Infinite Memory Engine (IME). IME allows to realize a fast buffer in front of a large capacity storage system. We collected benchmarking data with IOR and with the HPC application NEST. The IOR bandwidth results show how well network bandwidth towards such fast buffer can be exploited compared to the external storage system. The NEST benchmarks clearly demonstrate that IME can reduce I/O-induced load imbalance between MPI ranks to a minimum while speeding up I/O as a whole by a considerable factor. In addition to these direct measurements, a performance model for NEST is developed. In combination with a generic and abstract burst buffer architecture, this model generates predictions about appropriate burst buffer and I/O parameters to achieve specific performance goals for NEST on HPC clusters of varying size. Specifically, it is investigated in which parameter range burst buffers are able to counteract the widening performance gap between compute and I/O.

An Optimization Calculation Method of Wind Farm Energy Storage Capacity based on Economic Dispatch

At present, large-capacity storage systems can theoretically smooth fluctuations of wind power output, but its economy is a huge bottleneck in practical applications. From the perspective of optimal economic dispatching of wind-storage power system. Conversion cost of spinning reserve capacity of thermal power due to energy storage reduce wind power forecast error and smooth fluctuation of wind power output, published cost of curtailed wind energy storage reduced and discharged cost of thermal power unit’s pollution and environmental management cost was mainly considered, a mathematical model was used to optimize economic dispatching, improved prediction accuracy and smoothed fluctuation of wind power output to satisfy the required standards of the State Grid was set up, a certain regional power grid with wind power in Xinjiang was taken as the example and simulated by employing genetic algorithm(GA). The result show that energy storage capacity is most economical when it accounts for 9.6% of the wind farm installed capacity, and corresponding capacity optimization method is practical, effective and promising in application.

The Design and Implementation of a High-Speed and Large-Capacity NAND Flash Storage System

Now, the quality of higher speed and larger capacity are required to the real-time storage system. This paper designs a high-speed and large-capacity storage system which uses FPGA as the master of SOPC system controlling NAND Flash chips. This system puts forward an advanced storage structure which has several NAND Flashes with multi-buses, forming a parallel pipeline design. By using the key technologies of bad block management and the ECC algorithm, which greatly avoids the influence of the invalid block to the storage system and reduces the probability of error data as well. It can not only improve the storage bandwidth and capacity substantially, but also ensure the reliability of the storage system effectively. As a result, the storage system achieves the capacity of 1.5TB and the bandwidth of 1280MBps. Also, this system uses high-speed exchange interface to link to the external network, which achieve the real-time transmission and control of data, and make the storage system standard, universal, and scalable.

ノンリニア編集 ノンリニア編集システムを構成する技術 高速・高信頼性・大容量ストレージシステム

ノンリニア編集 ノンリニア編集システムを構成する技術 高速・高信頼性・大容量ストレージシステム