Label Bits Research Articles

Deep Learning for Waveform Level Receiver Design With Natural Redundancy

High-speed information transmission system demands more powerful communication receivers. In this paper, we integrate deep learning algorithms into constructing waveform level receiver, which is capable of harnessing natural redundancy (NR) in raw message sources. Owing to end-to-end learning paradigm of neural network (NN), the proposed NN receiver can accomplish joint symbol timing synchronization and demodulation based on oversampled waveform sequences directly. The prevalent bidirectional LSTM (BiLSTM) and Transformer structures, suitable for excavating sequential correlation of complex sources and waveform sequences, are considered as the backbone of NN receivers. Under the cases of clean label and noisy label, we conceive two novel training algorithms and interpret their principles in theory. The clean label bits are accessible from original source encoding schemes, while noisy label bits are available from the decision results of canonical receivers with independently noised waveform sequences. When noisy labels possess sufficiently small error rates, optimized NN receiver is competitive with that adopting the accurate labels. As for Markov sources and natural language text sources, simulation results show that the proposed NN receivers’ performances are superior to the classical receivers without a priori knowledge, especially when high spectral efficiency modulation schemes are encountered and random noise is significant.

Probabilistically Shaped PAM-8 Transmission With Simplified Volterra Equalizer

Intensity-modulation direct-detection (IM/DD) probabilistically shaped (PS) 8-level pulse-amplitude modulation (PAM) signal is promising for high-speed intra-data-center networks. However, the challenges of a PS-PAM-8 transmission system are complicated distribution matcher (DM) and nonlinear equalizer. In this work, we propose a simple PS-PAM-8 transmission system, where the probabilistic amplitude shaping (PAS) encoder consists of an energy-level-assigned (ELA)-based DM and a low-density parity-check (LDPC) encoder. In the ELA-based DM, a simple lookup table is designed to realize an approximate bilateral Maxwell-Boltzmann distribution by assigning energy levels to various symbols. Consequently, the DM encoded bits are used as the amplitude bits, and DM label bits and LDPC check bits are designated as sign bits to implement PAS encoding. In addition, a simplified Volterra equalizer (SVE) is introduced to eliminate the inter-symbol interference and improve the receiver sensitivity of PS-PAM-8 signal, where the SVE only includes the 2-order kernel to reduce its complexity. We experimentally demonstrated the proposed PS-PAM-8 scheme and verified its outperformance over uniform PAM-8 signal in the back-to-back and 2-km standard single mode fiber (SSMF) transmission. Compared to the conventional linear equalizer, the SVE contributes approximate 1-dB improvement of the receiver sensitivity in the PS-PAM-8 2-km SSMF transmission, for the error-free performance of post forward error correction bit error ratio.

Low-Power Optical Packet Switching for 100-Gb/s Burst Optical Packets With a Label Processor and 8 × 8 Optical Switch

We demonstrate error-free 100-Gb/s optical packet switching with low power consumption by using a combination of a label processor and 8 × 8 broadcast-and-select (B&S) optical switch. To achieve energy-efficient label processing, an optical-trigger-pulse generator that consumes energy only for a very short duration is realized, whereas the optoelectronic serial-to-parallel converter used to interface the fast label bits to a slow CMOS processor has been improved to operate with a reduced trigger pulse energy of 0.35 pJ. Moreover, the electro-absorption-modulator-based B&S optical switch is significantly enhanced by introducing a surface ground electrode for eliminating electrical crosstalk and integrated spot-size converters with easy fabrication process. The total power consumption of the full 8 × 8 optical packet switch is estimated to be as low as 27.3 W or 3.4 W/100-Gb/s port.

Burst-mode optical label processor with ultralow power consumption.

A novel label processor subsystem for 100-Gbps (25-Gbps × 4λs) burst-mode optical packets is developed, in which a highly energy-efficient method is pursued for extracting and interfacing the ultrafast packet-label to a CMOS-based processor where label recognition takes place. The method involves performing serial-to-parallel conversion for the label bits on a bit-by-bit basis by using an optoelectronic converter that is operated with a set of optical triggers generated in a burst-mode manner upon packet arrival. Here we present three key achievements that enabled a significant reduction in the total power consumption and latency of the whole subsystem; 1) based on a novel operation mechanism for providing amplification with bit-level selectivity, an optical trigger pulse generator, that consumes power for a very short duration upon packet arrival, is proposed and experimentally demonstrated, 2) the energy of optical triggers needed by the optoelectronic serial-to-parallel converter is reduced by utilizing a negative-polarity signal while employing an enhanced conversion scheme entitled the discharge-or-hold scheme, 3) the necessary optical trigger energy is further cut down by half by coupling the triggers through the chip's backside, whereas a novel lens-free packaging method is developed to enable a low-cost alignment process that works with simple visual observation.

Novel flat datacenter network architecture based on scalable and flow-controlled optical switch system

We propose and demonstrate an optical flat datacenter network based on scalable optical switch system with optical flow control. Modular structure with distributed control results in port-count independent optical switch reconfiguration time. RF tone in-band labeling technique allowing parallel processing of the label bits ensures the low latency operation regardless of the switch port-count. Hardware flow control is conducted at optical level by re-using the label wavelength without occupying extra bandwidth, space, and network resources which further improves the performance of latency within a simple structure. Dynamic switching including multicasting operation is validated for a 4 x 4 system. Error free operation of 40 Gb/s data packets has been achieved with only 1 dB penalty. The system could handle an input load up to 0.5 providing a packet loss lower that 10(-5) and an average latency less that 500 ns when a buffer size of 16 packets is employed. Investigation on scalability also indicates that the proposed system could potentially scale up to large port count with limited power penalty.

FPGA-Based Label Processor for Low Latency and Large Port Count Optical Packet Switches

We present a field-programmable gate array (FPGA)-based label processor for in-band optical labels with a processing time independent of the number of label bits. This allows for implementing an optical packet switching architecture that scales to a large port count without compromising the latency. As a proof of concept, we have employed an FPGA board with 100 MHz clock to validate the operation of the label processor in a 160 Gb/s optical packet switching system. Experimental results show successful three label bits processing and 160 Gb/s packets switching with 1 dB power penalty and 470 ns of latency. Projections on the label processor performance by using more powerful FPGAs indicate that 60 label bits ( optical addresses) can be processed within 31 ns.

Optical RF Tone In-Band Labeling for Large-Scale and Low-Latency Optical Packet Switches

We propose an RF tone in-band labeling technique that is able to support large-scale and low-latency optical packet switch. This approach is based on N in-band wavelengths, each carrying M radio frequency (RF) tones. The wavelengths and the tones have a binary value, and are able to encode 2N×M possible routing address. We develop an optical label processor for the RF tone in-band optical label based on parallel and asynchronous processing. It allows the optical packet switch with an exponential increase of number of ports at the expense of limited increase in the latency and the complexity. By using RF tone in-band labeling technique, we demonstrate error free (bit error rate <; 10-9) optical packet switching operation for both 160 Gb/s packets and 40 Gb/s packets. We further investigate the scalability, the latency and the optical power fluctuation tolerance of the proposed RF tone in-band labeling technique. We show that 30 label bits are able to be delivered using single in-band wavelength, and the label processor introduces an extra latency of less than 7 ns.

A New Loopback Method of All-Optical Label Processing for Label Bit Scalability

We propose and demonstrate a new method to expand the label bit in an all-optical label processor with a multistage switching fabric. It utilizes a loopback configuration, where a probe pulse is fed back to the same switching fabric with wavelength conversion and the output probe pulse is discriminated by arrayed waveguide gratings. The feasibility of the loopback scheme was demonstrated for the two-bit pattern in the two-bit label using a single semiconductor optical amplifier-based Mach-Zehnder interferometer 1x2 all-optical switch. It is effective to reduce the number of switching elements and will expand the number of label bits.

All-Optical Label Recognition Using Self-Routing Architecture of Mach-Zehnder Interferometer Optical Switches with Semiconductor Optical Amplifiers

We propose a new label recognition system for photonic label switching using self-routing of labels. Binary-coded labels in on-off keying format are considered. The system consists of an all-optical demultiplexer (DeMUX) and an address recognition unit (ARU) consisting of tree-structured switches. The system uses self-routing propagation of an indication bit controlled with address bits. The indication bit is placed in advance of the address bits in the label. In DeMUX, all-optical switches in a configuration of Mach-Zehnder interferometer with semiconductor optical amplifiers (SOA-MZI) are controlled by the indication bit pulse to separate each of the label bits. The indication bit pulse is routed to the destination output port corresponding to the code of the address in ARU. It is shown that all the binary number codes can be recognized with this system. The operation principle is verified by numerical simulation using coupled-mode theory and a rate equation. Moreover, the switching crosstalk is also evaluated.

All-Optical Asynchronous Serial-to-Parallel Converter Circuit for DPSK Optical Packets

We propose a novel asynchronous all-optical circuit for extraction and serial-to-parallel conversion of label bits from differential phase-shift keying (DPSK) packets. The circuit requires only two optical switches regardless of the number of bits to be extracted and parallelized from the packet. Experimental evidence of practical use of the circuit to four bit labels at 10 Gb/s is provided. The circuit is scalable with the number of bits, operates at low input power, and is suitable for photonic integration. The asynchronous nature of the circuit allows us to efficiently extract/read one specific label field of variable length without processing the entire label, leading to a simplified architecture of the label processing circuit

Optimal differential energy watermarking of DCT encoded images and video

This paper proposes the differential energy watermarking (DEW) algorithm for JPEG/MPEG streams. The DEW algorithm embeds label bits by selectively discarding high frequency discrete cosine transform (DCT) coefficients in certain image regions. The performance of the proposed watermarking algorithm is evaluated by the robustness of the watermark, the size of the watermark, and the visual degradation the watermark introduces. These performance factors are controlled by three parameters, namely the maximal coarseness of the quantizer used in pre-encoding, the number of DCT blocks used to embed a single watermark bit, and the lowest DCT coefficient that we permit to be discarded. We follow a rigorous approach to optimizing the performance and choosing the correct parameter settings by developing a statistical model for the watermarking algorithm. Using this model, we can derive the probability that a label bit cannot be embedded. The resulting model can be used, for instance, for maximizing the robustness against re-encoding and for selecting adequate error correcting codes for the label bit string.