The performance requirements of image processing applications have led to increase in the computing power of implementation platforms, in particular when real-time constraints are to be met. Image processing applications may consist of different standards, or different algorithms used at different stages of the processing chain. The computing paradigm of reconfigurable architectures promises a trade-off between flexibility and performance. Reconfigurable architectures can exploit fine-grain (more suitable for low-level and medium-level operations in the image processing chain) and coarse-grain parallelism (more suitable for high-level operations in the image processing chain). Many reconfigurable architectures have been constructed specifically for image processing using different processors and dedicated circuits such as ASICs and FPGAs. This special issue on Reconfigurable Architecture for Real-Time Image Processing presents articles addressing reconfigurable computing for real-time image processing, programming frameworks with FPGA-style mapping as well as real-time and embedded image processing applications and implementations. This special issue includes nine papers that are briefly outlined below: The first paper, by Denoulet and Merigot, presents a massively parallel SIMD architecture based on reconfigurability and asynchronism called Associative Mesh. The introduced virtualized associative mesh achieves real-time execution for split and merge segmentation, watershed segmentation and motion detection. The second paper, by Kessal, Karabernou and Demigny, focuses on the Ardoise project. The goal of this project is to realize a dynamically reconfigurable platform. This paper proposes a methodology that can be easily adapted to common SoC architecture. The third paper, by Sen, Hemaraj, Plishker, Shekhar and Bhattacharya, presents a novel architecture that enables dynamically-reconfigurable image registration. It also addresses some data-flow-motivated parallel architectures for image registration. The fourth paper, by Meng, Freeman, Pears and Bailey, details the implementation of a human action recognition system on a reconfigurable, FPGA based video processing architecture. The fifth paper, by Jiang, Crookes and Bouridane, describes a parallel-matching processor architecture to perform high-speed biometric fingerprint database retrieval. The processor was implemented on Xilinx Virtex-E and runs up to 65 MHz. The sixth paper, by Chandrasekaran, Amira, Minghua and Bermak, covers the presentation of an architecture for the Finite Ridgelet Transform. It presents a parallel architecture as well as FPGA and ASIC implementations. The seventh paper, by Srinam and Eng, presents various implementations of the Kolmogorov phase screen generator. The FPGA hardware implementation provides a speedup of more than 60 times of the original algorithm. The eight paper, by Saponara, Casula and Fanucci proposes to combine the application specific instruction-set processor (ASIP) paradigm with the reconfigurable hardware one. The ninth paper, by Seetharaman, Venkataramani and Lakshminarayanan, describes how to get the benefits of M. Akil (&) Department of Computer Science, Institut Gaspar-Monge, Unite mixte de recherche CNRS-UMLVPE-ESIEE (UMR 8049), ESIEE, Cite Descartes, BP 99, 93162 Noisy-le-Grand Cedex, France e-mail: akilm@esiee.fr