Kintex-7 Field Programmable Gate Array Research Articles

Stochastic Computing Convolutional Neural Network Architecture Reinvented for Highly Efficient Artificial Intelligence Workload on Field-Programmable Gate Array.

Stochastic computing (SC) has a substantial amount of study on application-specific integrated circuit (ASIC) design for artificial intelligence (AI) edge computing, especially the convolutional neural network (CNN) algorithm. However, SC has little to no optimization on field-programmable gate array (FPGA). Scaling up the ASIC logic without FPGA-oriented designs is inefficient, while aggregating thousands of bitstreams is still challenging in the conventional SC. This research has reinvented several FPGA-efficient 8-bit SC CNN computing architectures, i.e., SC multiplexer multiply-accumulate, multiply-accumulate function generator, and binary rectified linear unit, and successfully scaled and implemented a fully parallel CNN model on Kintex7 FPGA. The proposed SC hardware only compromises 0.14% accuracy compared to binary computing on the handwriting Modified National Institute of Standards and Technology classification task and achieved at least 99.72% energy saving per image feedforward and 31× more data throughput than modern hardware. Unique to SC, early decision termination pushed the performance baseline exponentially with minimum accuracy loss, making SC CNN extremely lucrative for AI edge computing but limited to classification tasks. The SC's inherent noise heavily penalizes CNN regression performance, rendering SC unsuitable for regression tasks.

Prototype of a digitizer module based on multicycle-encoding FPGA ADC for a small animal PET

Current research in small animal positron emission tomography (PET) scanners focus on obtaining better spatial resolution and higher sensitivity. These enhancements of scanner performance result in a corresponding increase in the complexity of the electronics, which usually manifests through an increase in the number of electronics channels. Analog-to-digital converters (ADCs) implemented in field programmable gate arrays (FPGAs) are an effective way to simplify electronics complexity. In this paper, a resource-saving multicycle-encoding structure of an FPGA-based ADC with automated calibration is proposed, which achieves a sampling rate of 250 Msps. A digitizer module prototype containing 64 charge measurement channels based on the FPGA ADC is designed using a Kintex-7 FPGA. The effective number of bits (ENOB) achieved using the FPGA ADC is 4.26 bits under a 10.0555 MHz sine wave input. The charge measurement resolution of each channel is better than 5‰ full width half maximum under a 0.8 V signal input and 3% under inputs in the range 0.1 V to 1.2 V. The integral nonlinearity of each channel is within ± 1%.

Readout Firmware of the Readout System for the MWDC at the ETF in HIRFL-CSR

Three multiwire drift chamber (MWDC) detectors and readout electrical equipment had been installed in 2018 as part of the cooler storage ring external target facility (ETF) project to gather track data in the ETF. In addition to its high efficiency and adaptability, the electronic device requires high precision in terms of position and energy resolution, as well as good flexibility and efficiency of the electronics. In this paper, we propose an electronic readout technique for MWDC detectors and show the implementation of a 32-channel signal processing in a single Xilinx Kintex-7 Field-Programmable Gate Array. Furthermore, we also present a thorough description of the readout firmware, with a focus on the deserialization mechanism and data processing algorithms. Additionally, we conducted a series of initial tests is conducted. The results show that the proposed technique can meet the application requirement.

An FPGA-Based Hierarchical Parallel Real-Time Simulation Method for Cascaded Solid-State Transformer

The cascaded H-bridge (CHB)-based solid-state transformer (SST) is a core interface device for power conversion in the distribution network. However, the complicated structures and higher switching frequencies bring significant challenges to real-time simulation and hardware-in-loop (HIL) testing. This article proposes a field-programmable gate array (FPGA)-based hierarchical parallel real-time simulation method for cascaded SST, which mainly includes highly parallel solving at the operation level, module level, and system level. A dual-port equivalent model of the cascaded SST is constructed based on the hierarchical parallel real-time simulation method. A cascaded SST containing 42 modules (630 components) can be simulated on a single FPGA with a minimum of 400 ns time-step. The information of the ports of the equivalent model and the information of the internal nodes of the cascaded SST can be obtained, which is the same as the simulation of detailed model. The real-time simulation of cascaded SST with input-series-output-parallel (ISOP) structure is carried out on a Xilinx Kintex-7 FPGA. The simulation results show that the real-time simulation waveforms are almost consistent with those in PSCAD/EMTDC software package.

A 128-channel time-to-digital converter based on the 24-phase shift-clock sampling method for RPC

The Resistive Plate Chamber (RPC) are widely used in high energy physics (HEP) experiments. In recent years, new designs and application scenarios of RPCs abound, and an advanced time-to-digital converter (TDC) system is in demand. The TDC implemented in the field-programmable gate array (FPGA) is widely used in HEP experiments with changeable conditions as a flexible time measurement method. This article presents a multi-phase shift-clock sampling FPGA-based TDC with 128 channels. The TDC module is implemented in a Xilinx Kintex-7 FPGA. The sampling clock period (2.22 ns) is subdivided into 24 phases to achieve finer time resolution. The TDC performance measurements show that the root-mean-square (RMS) time resolution of the TDC module in the time interval measurement is 45.3 ∼ 57.7 ps, and the integral nonlinearity (INL) is smaller than 0.2368 least significant bit (LSB). In addition, some target designs are made to adapt to the application scenarios. This article also shows measurement results acquired from an RPC by this TDC. This TDC was used to measure the RPC efficiency plateau and the TOT of the RPC readout signal.

A Novel Design of Symmetric Daub-4 Wavelet Filter Bank for Image Analysis

The orthogonal wavelet filter banks (FBs) consume large resources for hardware implementation due to their irrational coefficients. This results in reduction in speed of operation, huge memory requirement and increased power dissipation. In order to solve these issues, a low complex symmetric Daub-4 (8-tap) orthogonal wavelet FB is proposed in this brief. This is achieved by slightly altering the perfect reconstruction (PR) condition to make proposed FB symmetric and to obtain dyadic filter coefficients. The proposed wavelet FB is multiplier free and achieves considerably reduction in hardware and dynamic power consumption by reducing number of adders and shifters. This is verified by implementing the proposed wavelet FB on Kintex-7 field programmable gate array (FPGA) using vivado 2019.2 software from Xilinx. The proposed FB is tested for its suitability in applications such as image compression and medical image retrieval. Simulations results prove that the designed wavelet FB gives better performances in terms of PSNR for image compression and retrieval accuracy (ARP, ARR) for medical image retrieval on the benchmark images as compared to state-of-art methods.

Throughput/Area Optimized Architecture for Elliptic-Curve Diffie-Hellman Protocol

This paper presents a high-speed and low-area accelerator architecture for shared key generation using an elliptic-curve Diffie-Hellman protocol over GF(2233). Concerning the high speed, the proposed architecture employs a two-stage pipelining and a Karatsuba finite field multiplier. The use of pipelining shortens the critical path which ultimately improves the clock frequency. Similarly, the employment of a Karatsuba multiplier decreases the required number of clock cycles. Moreover, an efficient rescheduling of point addition and doubling operations avoids data hazards that appear due to pipelining. Regarding the low area, the proposed architecture computes finite field squaring and inversion operations using the hardware resources of the Karatsuba multiplier. Furthermore, two dedicated controllers are used for efficient control functionalities. The implementation results after place-and-route are provided on Virtex-7, Spartan-7, Artix-7 and Kintex-7 FPGA (field-programmable gate arrays) devices. The utilized FPGA slices are 5102 (on Virtex-7), 5634 (on Spartan-7), 5957 (on Artix-7) and 6102 (on Kintex-7). In addition to this, the time required for one shared-key generation is 31.08 (on Virtex-7), 31.68 (on Spartan-7), 31.28 (on Artix-7) and 32.51 (on Kintex-7). For performance comparison, a figure-of-merit in terms of throughputarea is utilized which shows that the proposed architecture is 963.3 and 2.76 times faster as compared to the related architectures. In terms of latency, the proposed architecture is 302.7 and 132.88 times faster when compared to the most relevant state-of-the-art approaches. The achieved results and performance comparison prove the significance of presented architecture in all those shared key generation applications which require high speed with a low area.

Calibration of gain and timing mismatch for TI-ADCs with signals in all Nyquist zones using adaptive noise canceller

This paper presents a novel all-digital background calibration technique for general Time-Interleaved Analog-to-Digital Converters (TIADCs). Calibration of gain and timing mismatch of TIADCs using the estimation technique is designed based on the principle of the Adaptive Noise Canceller (ANC). In this ANC, there are two stages in gain, timing mismatch estimation in which a cascade structure of the correction and estimation is proposed to guarantee that our calibration achieves high performance. Besides the first Nyquit zone, the input signal at different Nyquist zones is also experimented. It is shown through the result that our calibration performs excellently on all chosen Nyquist zones. It achieves the SNDR (Signal to Noise Ratio) and SFDR (Spurious Free Dynamic Range) improvement of 19dB and 49dB, respectively. Moreover, the synthesized design with hardware co-simulation carried on the Xilinx Kintex-7 field-programmable gate array (FPGA) platform consumes only 7.36 % of the hardware resources of the FPGA chip and reduces the mismatch tone level to -87 dB. In addition, our convergence speed of SNDR during calibration is approximately 1/3 others.

A High-Speed Low-Cost Hardware Implementation for Depth Estimation Using Disparity Fusion Method

Depth estimation using stereo images can be achieved by calculating the disparity values between the left and the right images captured by two parallel cameras. Reconstructing depth information from 2D images is crucial in many applications, such as self-driving vehicles and robot navigation. Furthermore, most of these applications are employed with resource-constrained devices and have real-time requirements. In this paper, a high-speed, low-cost hardware implementation for disparity estimation is proposed. We adopted the novel disparity fusion method in our architecture, which can significantly reduce the number of calculations in the overall process. A refinement method is also designed to reduce the error rate of the resulting depth map and improve the tolerance to light noise. The proposed algorithm was implemented with the Kintex-7 field-programmable gate array. Its performance was tested by using the Middlebury-Version 2 and -Version 3 datasets. The proposed algorithm provides an operating speed of 118 fps with an error rate of only 6.36%. Compared with other state-of-the-art designs used for similar applications, the proposed method can achieve a 34.6% reduction in the error rate while providing the highest speed with competitive hardware cost.

Bubble-Proof Algorithm for Wave Union TDCs

Nowadays state-of-the-art time-to-digital converters (TDCs) are commonly implemented in field-programmable gate array (FPGA) devices using different variations of the wave union method. To take full advantage of this method many design challenges need to be overcome, one of which is an efficient data encoding. In this work, we describe in detail an effective algorithm to decode raw output data from a newly designed multisampling wave union TDC. The algorithm is able to correct bubble errors and detect any number of transitions, which occur in the wave union TDC output code. This allows us to reach a mean resolution as high as 0.39 ps and a single shot precision of 2.33 ps in the Xilinx Kintex-7 FPGA chip. The presented algorithm can be used for any kind of wave union TDCs and is intended for partial hardware implementation.

Design and Validation of Low-Power Secure and Dependable Elliptic Curve Cryptosystem

The elliptic curve cryptosystem (ECC) has been proven to be vulnerable to non-invasive side-channel analysis attacks, such as timing, power, visible light, electromagnetic emanation, and acoustic analysis attacks. In ECC, the scalar multiplication component is considered to be highly susceptible to side-channel attacks (SCAs) because it consumes the most power and leaks the most information. In this work, we design a robust asynchronous circuit for scalar multiplication that is resistant to state-of-the-art timing, power, and fault analysis attacks. We leverage the genetic algorithm with multi-objective fitness function to generate a standard Boolean logic-based combinational circuit for scalar multiplication. We transform this circuit into a multi-threshold dual-spacer dual-rail delay-insensitive logic (MTD3L) circuit. We then design point-addition and point-doubling circuits using the same procedure. Finally, we integrate these components together into a complete secure and dependable ECC processor. We design and validate the ECC processor using Xilinx ISE 14.7 and implement it in a Xilinx Kintex-7 field-programmable gate array (FPGA).

A Highly Linear FPGA-Based TDC and a Low-Power Multichannel Readout ASIC With a Shared SAR ADC for SiPM Detectors

This article presents a low-power highly linear multichannel data acquisition (DAQ) system for silicon photomultiplier (SiPM) readout. A low-input impedance current-mode front-end with a programmable current gain is developed to achieve high-precision charge readout over a large dynamic range. An integrated 10-bit successive-approximation-register (SAR) analog-to-digital converter (ADC) shared by 16 readout channels in a time-multiplexed manner is designed to reduce the overall chip area and power consumption of the SiPM readout. Implementation challenges of field-programmable gate array (FPGA)-based time-to-digital converters (TDCs) including bubble error, zero length bins, interclock region nonlinearity, and chain overflow, are addressed for high accuracy timing measurement. Multichain averaging is developed to improve the TDC linearity. Fabricated in a 180-nm CMOS process, the current-mode 16-channel readout application-specific integrated circuit (ASIC) achieves 3.6% maximum gain nonlinearity over an input dynamic range of 800 pC with dissipating 3.89 mW of power per readout channel, and the ADC achieves an SFDR of 58.34 dB and an SNDR of 51.37 dB at 16 MS/s. Implemented in a Xilinx 28-nm Kintex-7 FPGA, the 32-channel TDC achieves a 15-ps root mean square (RMS) resolution, a differential nonlinearity (DNL) of less than 4 ps, and an integral nonlinearity (INL) of less than 10 ps.

Measurement and evaluation of the Single Event Effects of high-performance SerDes circuits

This paper characterizes the Single Event Effect (SEE) sensitivities of the Serializer/Deserializer (SerDes) module on the advanced 28 nm Xilinx Kintex-7 Field Programmable Gate Array (FPGA). A systematical SEE measurement method is proposed and implemented to evaluate the SEE sensitivity of the SerDes circuits. In our experiments, an extremely low Single Event Upset (SEU) Linear Energy Transfer (LET) threshold of the SerDes circuits was investigated, and both the recoverable and unrecoverable Single Event Functional Interrupts (SEFIs) were clearly distinguished and classified. In the experiments, it was found that the SEUs and recoverable SEFIs of the TX and RX in the same channel were closely related due to their shared clock and control circuits. Based on this detailed survey, a further discussion of the mechanisms of the SEU, recoverable SEFI, and unrecoverable SEFI is also provided. The SEE sensitivity of the high-speed SerDes circuits presented in this paper will promote the effective utilization of error mitigation strategies in order to control the risks of applications in radiation environments.

A ring-oscillator based multi-mode time-to-digital converter on Xilinx Kintex-7 FPGA

Taking the system clock as the reference, a ring-oscillator based Vernier-type time stamping method is proposed for the implementation of time-to-digital converters (TDCs) on field programmable gate array (FPGA). A module with this method called time-marker is implemented on a Xilinx Kintex-7 FPGA and tested with 43 ps time resolution and less than 50 ns measurement dead time. To illustrate this time-marker can be used as the building block for TDC construction to provide high time measurement performance with low resource consumption, a multi-mode TDC using eight time-markers is implemented with performance evaluation. The TDC has three flexible configuration modes for performance enhancements in three aspects. In the multi-channel mode, it becomes eight independent TDC channels with average 34 ps time interval RMS precision and 50 ns measurement dead time; in the high-precision mode, it is one TDC channel with 14 ps RMS precision and 50 ns measurement dead time; and in the high-throughput mode, it is one TDC channel with 33 ps RMS precision and 6.25 ns measurement dead time. In addition, the temperature dependence of the performance is evaluated.

A Tunable Parameter, High Linearity Time-to-Digital Converter Implemented in 28-nm FPGA

This article presents a high linearity time-to-digital converter (TDC) with tunable parameters, based on a field-programmable gate array (FPGA) device. Specifically, a nonuniform monotonic multiphase (NUMMP) method is proposed to reestablish equivalent delay units with nonuniform delay time to overcome the limitation of the intrinsic delay and the uniformity of delay element in FPGA firstly. Then, the raw data frame composed of the equivalent delay units is marked by a time scale marking (TSM) method. Thirdly, a feature extraction (FE) method is proposed to extract the marked raw data frame to form a feature frame, which can reduce the data volume by 79.1%. After that, the feature frames are decoded by a proposed coarse-fine decoding (CFD) algorithm, which can increase the decoding speed, shorten the dead time to 8 clock cycles and reduce the amount of decoding calculation by 80%. Finally, the proposed TDC has been verified with a Xilinx Kintex-7 FPGA. The measurement results demonstrate that the proposed NUMMP TDC with highly adjustable linearity and resolution has been realized. For a high linearity configuration with a LSB of 20 ps, the differential nonlinearity (DNL) and the integral nonlinearity (INL) are only +0.06/-0.05 and +0.08/-0.15 LSB, respectively. And for a high-resolution configuration with a LSB of 1.87 ps, the root mean square (RMS) for the resolution can achieve 2.79 ps, and the values of the DNL and INL are +1.30/-0.54 and +3.51/-2.21 LSB, respectively.

A high resolution multi-phase clock Time-Digital Convertor implemented on Kintex-7 FPGA

Time-digital Converter (TDC) aims to measure the arrival time of the leading edge of the pulse signal. Our recent work presented a high resolution multi-phase TDC based on the Kintex-7 Field Programmable Gate Array (FPGA) device. A simple I/O tile based circular input buffer is employed to oscillate the input signal periodically, and then a multi-phase TDC based on ISERDES core with a 625 ps bin size is used to accomplish the multiple measurements for getting higher resolution performance. In this paper, the design concept, architecture, as well as kernel implementation considerations are all discussed. To evaluate the TDC's performance, we built a verification system based on Kintex-7 FPGA. Initial test results indicate that the TDC's effective bin size is successfully reduced from 625 ps to 78.125 ps, and the measured dual-channel time resolution is better than 35 ps RMS.

High-Level synthesis assisted design and verification framework for automotive radar processors

In radar-based advanced driver assistance systems, baseband processing is necessary to detect the speed, distance, and angle of elevation of the target (e.g., vehicle, pedestrian, traffic sign, etc.). The target and the source often move at high speeds; therefore, the computation rate must be sufficiently high to perform actions (e.g., braking) in real-time. Software-based implementations of such systems fall short of the required performance, which has led to an increase in the popularity of custom hardware implementations, e.g., on field-programmable gate arrays (FPGAs). FPGAs also serve as platforms to develop software concurrent with system-on-chip (SoC) development, thereby decreasing the time to market. High-level synthesis (HLS) tools are gaining considerable attention in the very-large-scale integration design community because of their flexibility. In this paper, we propose a novel design and verification framework for a RADAR processing SoC. The framework is assisted by an HLS-based design scheme for the processor and supports the application of a real-world stimulus to register transfer-level design implementation running on FPGAs. Customer use cases for the distance and velocity calculations are executed in a pre-silicon environment using range and Doppler processing on the Xilinx Kintex-7(XC 7K 480T) FPGA. Our findings show that the proposed framework, based on MATLAB HDL Coder and HDL Verifier, is superior to similar implementations from prior research in terms of speed and FPGA resources. This is owing to the usage of appropriate HLS directives and the usage of a novel design method based on application-specific bit width for intermediate data nodes.

FPGA Implementation of A∗ Algorithm for Real-Time Path Planning

The traditional A∗ algorithm is time-consuming due to a large number of iteration operations to calculate the evaluation function and sort the OPEN list. To achieve real-time path-planning performance, a hardware accelerator’s architecture called A∗ accelerator has been designed and implemented in field programmable gate array (FPGA). The specially designed 8-port cache and OPEN list array are introduced to tackle the calculation bottleneck. The system-on-a-chip (SOC) design is implemented in Xilinx Kintex-7 FPGA to evaluate A∗ accelerator. Experiments show that the hardware accelerator achieves 37–75 times performance enhancement relative to software implementation. It is suitable for real-time path-planning applications.

A Hierarchical Scrubbing Technique for SEU Mitigation on SRAM-Based FPGAs

The SRAM-based field-programmable gate array (FPGA) is extremely susceptible to single event upsets (SEUs) on configuration memory which can lead to soft error and malfunction of the circuit. Facing the ever-growing number of configuration bits in modern FPGAs, traditional scrubbing is getting harder to find errors in time, resulting in mismatching between the SEU sensitivity and scrubbing performance. This article proposes a hierarchical scrubbing technique that makes full use of the SEU sensitivity based on the adaptive mean time to detect (MTTD) for each frame. It distinguishes the configuration frames with multipriority and uses different scrubbing methods for different priorities. Also, a model has been built for solving the MTTD allocating problem and enabling an effective scrubbing when SEU occurrence. Moreover, the corresponding hardware architecture is supported and the fault injection-based evaluation on a Xilinx Kintex-7 FPGA is done. The result shows that it can improve mean upsets to failure from 1.56 × to 146.93 × , which is proportional to the mean time to failure (MTTF) improvement.

FPGA Design of Elliptic Curve Cryptosystem (ECC) for Isomorphic Transformation and EC ElGamal Encryption

Attacking or tampering with sensitive data continues to increase risks to economic processes or human activities. These risks are significant key factors to improve the development and implementation of security systems. Therefore, improving cryptography is essentially needed to enhance the security of critical data. For example, elliptic curve cryptography (ECC) over the Galois field GF(2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">163</sup> ) is one of the public-key (asymmetric) cryptographic techniques, in which demands mapping a message (163-bit) to a point in the prime subgroup of the elliptic curve. To the best of our knowledge, mapping methods are not yet available on Field-Programmable Gate Arrays (FPGAs). Also, asymmetric encryption schemes often do not consider encrypting/decrypting data packets because of their computation complexity and performance limitations. In this letter, we propose and develop a concurrent reconfigurable cryptosystem to encrypt and decrypt stream of data using ECC on FPGA. First, we present hardware design and implementation to map a plain message on the elliptic curve based on isomorphic transformation, then second, we architect the elliptic curve ElGamal public-key encryption method by using point addition and multiplication on Koblitz elliptic curve on FPGA. Our proposed cryptosystem is synthesized and implemented on Intel Cyclone 10 GX and Xilinx Kintex-7 FPGAs to evaluate throughput, and it achieves 25.73-57.1 Mbps.