Kinds Of Processors Research Articles

Fuzzy classification of OpenCL programs targeting heterogeneous systems

Heterogeneous systems featuring multiple kinds of processors are becoming increasingly attractive due to their high performance and energy savings over their homogeneous counterparts. With the OpenCL as a unified programming language providing program portability across different types of accelerators, finding the best task-to-device mapping will be the key to achieve such a high performance. We introduce in this work the design of a fuzzy logic classifier and the evaluation of its performance in classifying OpenCL workloads in a CPU-GPU-FPGA heterogeneous environment based on carefully analyzed kernel features. The classifier is designed as part of a scheduling scheme. Results demonstrate substantial improvement in accuracy when compared to other classifiers such as the K-Nearest- Neighbor (KNN), Support-Vector-Machine (SVM), Random-Forest (RF), Naïve-Bayes (NB) and the Bayes-Network (BN) with low computational complexity, facilitating run-time operation.

The use of streak observations to detect space debris

ABSTRACTMan-made space debris orbit around the Earth at many altitudes in different orbits and many launches add further debris to already congested orbits. The European Space Agency (ESA) GSTP-funded Optical IN-SITU Monitor project started in 2016 and aims to analyse the end-to-end processing pipeline from image acquisition to the extracted positions of space debris. A camera will take images and an on-board data processor will filter and compress the images obtained, which – in case of a future flight model of the instrument – shall be downlinked to the ground station. For the image filtering and compression, several data reduction algorithms are considered and also two different kinds of processors are considered. The difficulty of the images is to differentiate between stars in the background (which have to be filtered out) and the debris. A short overview of the project is presented in this paper: its current status, the hardware choices and the data reduction algorithm trade-off.

Low-level trace correlation on heterogeneous embedded systems

Tracing is a common method used to debug, analyze, and monitor various systems. Even though standard tools and tracing methodologies exist for standard and distributed environments, it is not the case for heterogeneous embedded systems. This paper proposes to fill this gap and discusses how efficient tracing can be achieved without having common system tools, such as the Linux Trace Toolkit (LTTng), at hand on every core. We propose a generic solution to trace embedded heterogeneous systems and overcome the challenges brought by their peculiar architectures (little available memory, bare-metal CPUs, or exotic components for instance). The solution described in this paper focuses on a generic way of correlating traces among different kinds of processors through traces synchronization, to analyze the global state of the system as a whole. The proposed solution was first tested on the Adapteva Parallella board. It was then improved and thoroughly validated on TI’s Keystone 2 System-on-Chip (SoC).

IMPLEMENTATION OF 32-BIT HIGH-VALENCY LING ADDER IN MODIFIED FIR FILTER USING APC-OMS APPROACH

Ling Adder is an advanced architecture of Parallel prefix adders. Parallel Prefix adders are used for efficient VLSI implementation of binary number additions. Ling architecture offers a faster carry computation stage compared to the conventional parallel prefix adders. Ling adders help to reduce the complexity as well as the delay of the adder further. In many computers and other kinds of processors, adders are used not only in the Arithmetic Logic Unit (ALUs), but also in other parts of the processor. Thus the delay in adders has to be decreased as maximum as possible to make the system faster. In particular, valency or the number of inputs to a single node is explored as a design parameter. High-valency Ling adders have superior area x delay characteristics over previously reported Ling-based or non-Ling based adders for the same input size. In DSP, even the multipliers require a large number of logic gates that consumes more area, power and delay. Hence, the lookup table can be used for performing computation which requires less area. Therefore, APC and OMS are the two techniques implemented in Lookup table so as to reduce the size to one-fourth of its conventional multiplier. This proposed combination of both Lookup table Multiplier and Ling adder has a better area and delay measurement.

Design of 32 bit Parallel Prefix Adders

In this paper, we propose 32 bit Kogge-Stone, Brent-Kung, Ladner-Fischer parallel prefix adders. In general N-bit adders like Ripple Carry Adders (slow adders compare to other adders), and Carry Look Ahead adders (area consuming adders) are used in earlier days. But now the most Industries are using parallel prefix adders because of their advantages compare to other adders. Parallel prefix adders are faster and area efficient. Parallel prefix adder is a technique for increasing the speed in DSP processor while performing addition. We simulate and synthesis different types of 32-bit prefix adders using Xilinx ISE 10.1i tool. By using these synthesis results, we noted the performance parameters like number of LUTs and delay. We compare these three adders in terms of LUTs (represents area) and delay values. Keywords− prefix adder, carry operator, Kogge-Stone, Brent-Kung, Ladner-Fischer. I. Introduction Arithmetic circuits are the ones which perform arithmetic operations like addition, subtraction, multiplication, division, parity calculation. Most of the time, designing these circuits is the same as designing muxers, encoders and decoders. In electronics, an adder or summer is a digital circuits(7) that performs addition of numbers. In many computers and other kind of processors, adders are other parts of the processor, many computers and other kinds of processors, where they are used to calculate addresses, table and similar. The binary adder(7,10) is the one type of element in most digital circuit designs including digital signal processors(DSP) and microprocessor data path units. Therefore fast and accurate operation of digital system depends on the performance of adders (6). Hence improving the performance of adder is the main area of research in VLSI(10) system design. The Conventional adders discussed in section II. The details of R Kogge- Stone adder, Brent-Kung adder and Ladner- Fischer adders are discussed, and the implementation of proposed system is described in section III. The performance and simulation results were presented and discussed in section IV.

A dataflow-like programming model for future hybrid clusters

It is expected that the first exascale supercomputer will be deployed within the next 10 years, however both its CPU architecture and programming model are not known yet. Multicore CPUs are not expected to scale to the required number of cores per node, but hybrid multicore CPUs consisting of different kinds of processing elements are expected to solve this issue. They come at the cost of increased software development complexity with \eg, missing cache coherency and on-chip NUMA effects. It is unclear whether MPI and OpenMP will scale to exascale systems and support easy development and scalable and efficient programs. One of the programming models considered as an alternative is the the so-called partitioned global address space~(PGAS) model, which is targeted at easy development by providing one common memory address space across all cluster nodes. In this paper we first outline current and possible future hardware and introduce a new abstract hardware model able to describe hybrid clusters. We discuss how current shared memory, GPU and PGAS programming models can deal with the upcoming hardware challenges and describe how synchronization can generate unneeded inter- and intra-node transfers in case the memory consistency model is not optimal. As a major contribution, we introduce our variation of the PGAS model allowing implicit fine-grained pair-wise synchronization among the nodes and the different kinds of processors. We furthermore offer easy deployment of RDMA transfers and provide communication algorithms commonly used in MPI collective operations, but lift the requirement of the operations to be collective. Our model is based on single assignment variables and uses a data-flow like synchronization mechanism. Reading uninitialized variables results in the reading thread to be blocked until data are made available by another thread. That way synchronization is done implicitly when data are read. Explicit tiling is used to reduce synchronization overhead and to increase cache and network utilization. Broadcast, scatter and gather are modeled based on data distribution among the nodes, whereas reduction and scan follow a combining PRAM approach of having multiple threads write to the same memory location. We discuss the GauAŸ-Seidel stencil, bitonic sort, FFT and a manual scan implementation in our model. We implemented a proof-of-concept library showing the usability and scalability of the model. With this library the GauAŸ-Seidel stencil scaled well in initial experiments on an 8-node machine and we show that it is easy to keep two GPUs and multiple cores busy when computing a scan.

An Approximation Algorithm and Dynamic Programming for Reduction in Heterogeneous Environments

Network of workstation (NOW) is a cost-effective alternative to massively parallel supercomputers. As commercially available off-the-shelf processors become cheaper and faster, it is now possible to build a cluster that provides high computing power within a limited budget. However, a cluster may consist of different types of processors and this heterogeneity complicates the design of efficient collective communication protocols. For example, it is a very hard combinatorial problem to find an optimal reduction schedule for such heterogeneous clusters. Nevertheless, we show that a simple technique called slowest-node-first (SNF) is very effective in designing efficient reduction protocols for heterogeneous clusters. First, we show that SNF is actually a 2-approximation algorithm, which means that an SNF schedule length is always within twice of the optimal schedule length, no matter what kind of cluster is given. In addition, we show that SNF does give the optimal reduction time when the cluster consists of two types of processors, when the ratio of communication speed between them is at least two. When the communication speed ratio is less than two, we develop a dynamic programming technique to find the optimal schedule. Our dynamic programming utilizes the monotone property of the objective function, and can significantly reduce the amount of computation time. Finally, combined with an approximation algorithm for broadcast 2004, we propose an all-reduction algorithm which sends the reduction answer to all processors, with approximation ratio 3.5. We conduct three groups of experiments. First, we show that SNF performs better than the built-in MPI_Reduce in a test cluster. Second, we observe a factor of 93 times saving in computation time to find the optimal schedule, when compared with a naive dynamic programming implementation. Thirdly, we apply the theoretical results to a branch-and-bound search and show that they can reduce the search time of the optimal reduction schedule by a factor of 500, when the cluster has three kinds of processors.

Skeletons and Asynchronous RPC for Embedded Data and Task Parallel Image Processing

Developing embedded parallel image processing applications is usually a very hardware-dependent process, often using the single instruction multiple data (SIMD) paradigm, and requiring deep knowledge of the processors used. Furthermore, the application is tailored to a specific hardware platform, and if the chosen hardware does not meet the requirements, it must be rewritten for a new platform. We have proposed the use of design space exploration [9] to find the most suitable hardware platform for a certain application. This requires a hardware-independent program, and we use algorithmic skeletons [5] to achieve this, while exploiting the data parallelism inherent to low-level image processing. However, since different operations run best on different kinds of processors, we need to exploit task parallelism as well. This paper describes how we exploit task parallelism using an asynchronous remote procedure call (RPC) system, optimized for low-memory and sparsely connected systems such as smart cameras. It uses a futures [16]-like model to present a normal imperative C-interface to the user in which the skeleton calls are implicitly parallelized and pipelined. Simulation provides the task dependency graph and performance numbers for the mapping, which can be done at run time to facilitate data dependent branching. The result is an easy to program, platform independent framework which shields the user from the parallel implementation and mapping of his application, while efficiently utilizing on-chip memory and interconnect bandwidth.

Optimizing the configuration of a heterogeneous cluster with multiprocessing and execution-time estimation

Although heterogeneous clusters are flexible and cost-effective, they entail intrinsic difficulties in optimization. Whereas it is simple to invoke multiple processes on fast processing elements (PEs) to alleviate load imbalance, the optimal process allocation is not obvious. Communication time is another problem. Though it is sometimes better to exclude slow PEs to avoid performance degradation, it is generally difficult to find the optimal PE configuration. In this study, the execution time is first modeled from the measurement results of various configurations. The derived models are then used to estimate the optimal PE configuration and process allocation. We implemented various models for HPL (High Performance Linpack benchmark) on a heterogeneous cluster, and estimated the optimal configurations for various problem sizes. In the case of a heterogeneous cluster of Athlon and Pentium-II, the execution time of the estimated optimal configuration was 0–7.4% longer than that of the actual optimal configuration. In a heterogeneous cluster of three kinds of processors that includes dual-processors, the excess time was 13.6–31.5%.

Code size reduction technique and implementation for software-pipelined DSP applications

Software pipelining technique is extensively used to exploit instruction-level parallelism of loops, but also significantly expands the code size. For embedded systems with very limited on-chip memory resources, code size becomes one of the most important optimization concerns. This paper presents the theoretical foundation of code size reduction for software-pipelined loops based on retiming concept. We propose a general Code-size REDuction technique (CRED) for various kinds of processors. Our CRED algorithms integrate the code size reduction with software pipelining. The experimental results show the effectiveness of the CRED technique on both code size reduction and code size/performance trade-off space exploration.

The multiplication of very large integers using the discrete fast Fourier transform

Year after year, there is an incredible increase in computation power delivered by parallelism and new kinds of processors. The length of integers involved in the computations in public-key cryptosystems will probably be more than one thousand bits within the next ten years to warranty a good security level. The proposal is to present a possible software solution for 1024, 1279, 2048 and 4096-bit numbers which combine software and general purpose hardware. The algorithm implemented makes use of the Discrete fast Fourier Transform ( DFT ) and produces first results which can be compared to others like Karatsuba's or modular arithmetic. Considering these results for cryptographic applications using asymmetric systems for key exchanges one can take advantage of such a method for modular exponentiation but only for operations involving more than 1024 bits. While using a quad-transputer board equipped with the new T9000 family transputers, software modular exponentiation involving 1024-bit numbers should take under 0.5 s, 2048 bits under 2 s and 4096 bits less than 8 s which takes more time but insures the future of the just necessary security ! Expected results for this method show possible software applications for highly secure key exchange protocols using general purpose new chips ( INMOST9000 transputer or Intel 1860 when used in piped mode ).