Jog Insertion Research Articles

A Faster One-Dimensional Topological Compaction Algorithm with Jog Insertion

We consider the problem of one-dimensional topological compaction with jog insertions. By combining both geometric and graph-theoretic approaches we present a faster and simpler algorithm to improve over previous results. The compaction algorithm takes as input a sketch consisting of a set F of features and a set W of wires, and minimizes the horizontal width of the sketch while maintaining its routability. The algorithm consists of the following steps: constructing a horizontal constraint graph, computing all possible jog positions, computing the critical path, relocating the features, and reconstructing a new sketch homotopic to the input sketch, which is suitable for detailed routing. The algorithm runs in O(|F| ⋅ |W|) worst-case time and space, which is asymptotically optimal in the worst case. Experimental results are also presented.

Chip compaction method with automatic jog insertion

The realization of an electronic circuit in the smallest possible area is the key to a successful LSI design. As a result, research on one-dimensional compaction methods has been active on reducing the area of a given IC layout. Further, it is desirable to reduce the area with jogs in wiring patterns. Compaction methods have been proposed that automatically add jogs effectively in the channel routing region for area reductions. These methods include the plane-sweep method developed in computational geometry and are fast and flexible enough to adapt to complex design rules. However, it is not only very difficult but inefficient to apply these methods to the entire chip area including functional blocks. This paper proposes a chip compaction method which inserts jogs while maintaining the advantages of the compaction methods based on the plane-sweep method. The proposed method is based on the shortest path search under a constraint graph and is capable of dealing efficiently with functional blocks. Experimental results will show the effectiveness of the method.

Insertion of jog series in layout compaction

One-dimensional compaction can substantially benefit from automatic jog insertion. An algorithm was developed, that iteratively reduces the length of the critical paths through the constraint graph. Its two novel features are the insertion of series of jogs and the simultaneous shortening of parallel critical paths in the graph. The algorithm is implemented in the compaction and design rule adaptation programs MLR and HIMALAYA and has successfully been applied to cells with more than 10,000 transistors.

A generic algorithm for one-dimensional homotopic compaction

One-dimensional homotopic compaction problems model the task of VLSI layout compaction with automatic jog insertion. They have the following form: given a routable layout, find a layout of minimum width reachable by a continuous motion of layout components that displaces each rigid component horizontally and preserves routability. We define a configuration space for this problem, and prove that if routability is characterized bycut conditions, then the set of reachable configurations is a closed, convex polyhedron. We also present a polynomial-time algorithm that finds the constraints defining this polyhedron and solves them to produce an optimal configuration. A homotopic router can recover the compacted layout from this configuration. We illustrate our strategy in thesketch model of VLSI layout, where it yields a compaction algorithm with worst-case running timeO(N 4) on input of sizeN.

Geometric approach to VLSI layout compaction

AbstractWe present a new geometric approach to VLSI layout compaction in this paper. In contrast to existing compaction algorithms, we rely on the geometric method and bypass both compaction grids and constraint graphs during the entire compaction process.A systematic and efficient way is introduced to enumerate all possible jogs. For the given layout topology we prove that the geometric algorithm yields the minimum‐area layout in one‐dimensional compaction with automatic jog insertion. In the final output, only necessary jogs are inserted and the total wire length is minimized as a secondary goal. Furthermore, the integration of local compaction tools into a layout CAD system and the practical extensions of our algorithm are addressed.

Shiftcompaction—quasi‐two‐dimensional compaction method for symbolic layout

AbstractA quasi‐two‐dimensional method called shiftcompaction has been developed as a compaction method for symbolic layout. Shiftcompaction takes a one‐dimensional compaction result as an input and tries to reduce the layout width by cutting off critical paths by moving elements on these paths perpendicularly to the compaction direction.In other words, it is a method for realizing process efficiency and effective layout compaction by restricting the objectives to be investigated for two‐dimensional translation to the layout elements that determine the current layout width. Furthermore, with a combination of a jog insertion operation, it can achieve denser layout compaction.Since those layout elements to be translated in the anti‐compaction direction are determined based on analysis of placement constraints in the anti‐compaction direction, it is possible in shiftcompaction to control the layout width in the anti‐compaction direction. As the results of compaction experiments, when, for example, a layout with 57 blocks and 110 wires was compacted, a 19 percent smaller layout area than a one‐dimensional compaction was obtained. This result is 6 percent smaller than that due to combination of one‐dimensional compaction and jog insertion. This verifies the effectiveness of the compaction method presented here.

A faster compaction algorithm with automatic jog insertion

The work of F.M. Maley (Proc. Chapel Hill Conf. on VLSI, p.261-83, 1985) on one-dimensional compaction with automatic jog insertion is refined. More precisely, an algorithm with running time O((n/sup 2/+k)log n), where k=O(n/sup 3/) is a quantity which measures the difference between the input and output sketch, is given, and Maley's O(n/sup 4/) algorithm is improved. The compaction algorithm takes as input a layout sketch, the wires in a layout sketch are flexible and only indicate the topology of the layout. The compactor minimizes the horizontal width of the layout while maintaining its routability. The exact geometry of the wires is filled in by a router after compaction. >