JK Flip-flop Research Articles

Engineered Gate based Nanoscaled JK Flip Flop: Design, Simulation and Applications

Engineered Gate based Nanoscaled JK Flip Flop: Design, Simulation and Applications

Programmable Synchronous 2-Bit Counter in Quantum-Dot Cellular Automata

Quantum-dot Cellular Automata (QCA) is a newly-developed nanoscale electron device that has the potential to replace the conventional transistor in the future. Owing to the unique field-coupling mechanism of QCA, several constraints must be fulfilled during the design of QCA sequential circuits, which makes the construction of sequential circuits a relatively intractable issue in QCA research. In this paper, a programmable synchronous 2-bit counter in QCA is proposed, which is consisted of combinational logic and falling edge-triggered JK flip-flops. The count mode of the programmable counter can be changed on-demand by mode control signals. Moreover, an initial state setting method of the QCA circuit is also proposed during the design of the counter so that the effects of random initial states can be avoided. Simulation with QCADesigner software demonstrates the validity of the proposed counter.

Multiple-Controlled Toffoli and Multiple-Controlled Fredkin Reversible Logic Gates-Based Reversible Synchronous Counter Design

The counters that change their transition using a clock signal are called synchronous counters. While designing a synchronous counter circuit, the power consumption and the delay are the major issues. Several synchronous counters were designed previously with the help of flip flops, but they did not provide good results. The existing synchronous counters increased power consumption and delay and decreased the speed. To overcome these issues, in this manuscript, a reversible synchronous counter is designed utilizing Multiple-Controlled Toffoli (MCT) and Multiple-Controlled Fredkin (MCF) reversible logic gates. Here, three JK flip-flop designs, such as JK1, JK2, and JK3 are designed for a reversible synchronous counter. Then JK1 and JK2 are structured by MCT. Whereas the JK3 flip-flop design is designed under MCF reversible logic gates. Coding is carried out Verilog, and then the proposed Reversible synchronous counter design (RSCD) is synthesized and implemented on FPGA using a Xilinx ISE 14.5 System generator. Here, performance metrics, such as delay, power, maximum counting rate, and total equivalent gate counts are examined. The efficiency of the proposed RSCD-MCT-MCF design attains gate counts of 23.45%, 28.94%, and 29.04% and is compared to the existing designs, such as Effective Designing of Reversible Synchronous Counters in Nanoscale (SCD-MTG), effective designing for reversible sequential circuits (SCD-3TG-4FG), designing of synchronous decimal counter utilizing reversible Toffoli–FredkinNetlist (SCD-TOF2).

The flip-flop neuron: a memory efficient alternative for solving challenging sequence processing and decision-making problems

Sequential decision-making tasks that require information integration over extended durations of time are challenging for several reasons, including the problem of vanishing gradients, long training times and significant memory requirements. To this end, we propose a neuron model fashioned after the JK flip-flops in digital systems. A flip-flop is a sequential device that can store state information of the previous history. We incorporate the JK flip-flop neuron into several deep network architectures and apply the networks to difficult sequence processing problems. The proposed architectures include flip-flop neural networks (FFNNs), bidirectional flip-flop neural networks (BiFFNNs), convolutional flip-flop neural networks (ConvFFNNs), and bidirectional convolutional flip-flop neural networks (BiConvFFNNs). Learning rules of proposed architectures have also been derived. We have considered the most popular benchmark sequential tasks like signal generation, sentiment analysis, handwriting generation, text generation, video frame prediction, lung volume prediction, and action recognition to evaluate the proposed networks. Finally, we compare the results of our networks with the results from analogous networks with Long Short-Term Memory (LSTM) neurons on the same sequential tasks. Our results show that the JK flip-flop networks outperform the LSTM networks significantly or marginally on all the tasks, with only half of the trainable parameters.

Design of QCA based N-bit single layer shift register using efficient JK Flip Flop for nano-communication applications

Quantum-dot Cellular Automata (QCA) is a technology that has the potential to create nano communication systems that are both highly efficient in power consumption and compact in size When compared to CMOS enabled electronic devices, QCA can achieve faster operation speed, higher density and lower power dissipation which becomes a boon, in digital logic design. In this paper, proposed work of designing sequential circuits using QCA has been achieved. An efficient JK flip-flop design along with 2-bit, 3-bit, 4-bit and 8-bit shift registers which can be further scaled up to N-bits using the same proposed design of flip-flop is observed. Also, the fault tolerance of proposed JK flip-flop design against single cell addition and deletion defects are presented in this paper. After conducting a performance comparison and thorough analysis of energy dissipation, it has been determined that the proposed designs bear lower cost and lower energy dissipations. Using QCADesigner tool, the validation of functions and processes of all proposed sequential designs has been done accordingly.

A Simple Method To Fire 3 Phase Stepped Wave Bridge Inverter Using 555 Timer, Counter By JK Flip-Flop And Decoder By And Gate

With the recent trend of economy where making one system is involved with lower cost devices used to make the same, this project involves no costly microcontroller or microprocessor IC or board for firing one 3 phase inverter in 180 degree mode. Rather simple 555 timer, JK Flipflop, AND gates, diodes used for firing one Transistorised 3 phase inverter in 180 degree conduction mode. The theoretical briffing with project circuits in MULTISIM and output are given in the following content.

7 Gbit/s optical JK flip flop design with two optical AND gates and NOR gates

7 Gbit/s optical JK flip flop design with two optical AND gates and NOR gates

Realization of all-optical JK flipflop in mid-IR wavelengths using triple-core photonic quasi-crystal fiber

Realization of all-optical JK flipflop in mid-IR wavelengths using triple-core photonic quasi-crystal fiber

Test bed for all-optical universal JK flip-flop (FF) and master-slave JK FF using ripple ring resonator (RRR) with Z-domain mathematical pedestal, and its application as synchronous up-counter

All-optical universal JK flip-flop (FF) is designed and demonstrated using ripple ring resonator (RRR). Four InGaAsP-InP optical microring resonators (OMRRs) are used to design the proposed JK FF test bed. Master-slave configuration for the same is also presented to overcome race-around condition. The system performance is analysed over different quality metrics. Two-bit synchronous up-counter is discussed as an application of presented JK FF. The test bed is compact and feasible to integrate as a photonic chip. Different sequential logic circuits can be designed with the help of presented low dimension, high speed all-optical RRR based JK FF.

An Accumulator using Electron Tunneling Through Tunnel Junction

Instead of an existing logical Technology, by using an emerging technology we will be able to make an electronic circuit with high speed, low cost, high concentration density, light in weight, reduced gate numbers and low power consumption. This technology is based on the linear threshold logic condition and electron-tunneling event. At the time of implementing a circuit, a multi-inputs but one-output based logic-node will be brought in our consideration. In this work, we have designed a 1-bit accumulator and then implemented it. To develop an accumulator, some small components like 2-input AND, 3-input AND, 3-input OR, 8-input OR, 9-input OR gate and above all a JK Flip-flop (for 1-bit) are to be collected and connected them in logical order to obtain the proper circuit. After verifying all their characteristics with the results obtained from the simulator, we have built a 1-bit accumulator. All the small components are provided in due places. They are analyzed, detected their threshold logic equations, shown their threshold logic gates (TLGs), tabulated their truth tables, drawn their input-output waveforms, given their respective circuits with exact parameter values. In the accumulator, there are nine control variables S1 through S9 in view of performing the operations (i) Addition, (ii) clear, (iii) complement, (iv) AND, (v) OR, (vi) XOR, (vii) Right-shift, (viii) Left-shift and (ix) increment with positive triggering clock pulses. Whether our present work’s circuits are faster or slower with respect to the similar circuits of CMOS based- and Single electron transistor (SET) based circuits are compared and observed that our TLG based circuits are faster than the CMOS and SET based circuits. The power consumed for tunneling event for a circuit is measured and sensed that it would remain in the range of 10meV to 250meV which is low. All the circuits we have presented in this work are of ‘generic multiple input threshold logic gate’ which is elaborately discussed.

Design Of Clocked Jk Flip Flop Using Air Hole Structured Photonic Crystal

In this paper an advanced air-hole type photonic crystal is used to design a clocked JK flip flop. A uniform GaAs photonic crystal that has the refractive index of 2.95 with air hole structure is utilized. Photonic crystal is created with multi-mode interference (MMI) for three input ports which represent three inputs Clock, J and K. The given structure is resulted with 8.657 contrast ratio and the power output is 6.24dB. The response time of the structure is less than 0.27 ps. The overall design and the results are discussed through the experimental implementation and the numerically simulation to confirm its operation and feasibility. The response time of the structure is very less. The simplicity of the crystal, contrast ratio, power output and quick response time makes more suitable to be a part of optical integrated circuits.

Investigations with all optical sequential circuit at higher data rate

Abstract All optical signal processing is one of the growing area, finds relevance where fast computing speed is one of the vital concern. Optical sequential logic system is the backbone of the ultrafast processing network. Accordingly, this article explores proposed optical sequential schemes for the JK and T-type optical flip flop’s investigation at higher data rate. The outputs have been verified for the JK and T-type flip flops. Numerical simulations showed ER of 11.6 and 10 dB for the executed designs. Design have been investigated for variation in pump current, data rate (10–100 Gbps), peak power, bias voltage yielded the optimal performance with ER of over 12 dB. This schematic is simple excludes expensive optoelectronic translation and outcomes are well helpful for the design of complex sequential logic operations.

Modeling and analysis of all-optical 2-bit and 4-bit synchronous up counter using silicon waveguide based all-optical JK flip-flop in Z domain

Placing reliance on Silicon waveguide based OMRR, this paper has brought a simple design of optically pumped 2-bit and higher bit counters using optical J–K flip flop.The present paper has used the non-linerarity characteristic of OMRR. A Pump pulse is applied from the top which causes switching operation. The Counter Circuit has been achieved by using the delay line signal process approach. Circuit’s performance has been assessed vide exploration of Z-domain model. The validity and viability of the present model is determined by evaluating the performance parameters such as Free Spectral Range, Q-factor, Amplitude modulation, ON-OFF ratio, Extinction Ratio (ER), Fineness and Contrast Ratio during simulation.

Thin Film Sequential Circuits: Flip-Flops and a Counter Based on p-SnO and n-InGaZnO

Oxide semiconductors have emerged as ideal candidate materials for flexible electronics and circuits. However, complementary flip-flops, which are the essential building blocks in sequential circuits, based on all-oxide thin-film transistors (TFTs) have not yet been demonstrated. Here, we employed n-type indium gallium zinc oxide and p-type tin monoxide to achieve J-K flip-flop (JK-FF) and D-type edge-triggered FF (D-FF). The operation properties of the JK-FF and D-FF were characterised both statically and dynamically. The output signals of the D-FF show great robustness. The D-FF shows very short propagation delay times of 17 and 40 μs from “0” to “1” and from “1” to “0”, respectively. Based on the D-FFs, a two-bit counter with 90 transistors was designed and fabricated successfully, acting as either up-counter or down-counter. To the best of our knowledge, this counter has the highest integration among the reported thin-film complementary sequential circuits based on all-oxide transistors to date.

Positive edge-triggered JK flip-flop using silicon-based micro-ring resonator

This paper details the novel design, simulation and analysis of the digital photonic positive edge-triggered JK flip-flop using silicon micro-ring resonator as its core component. The designed silicon micro-ring resonator uses free carrier plasma dispersion electro-optic effect properties in its ring waveguide being structured as a PIN diode. There are altogether four silicon micro-ring resonators used in our proposed design, with each ring operates as specific logic mode operation. Time varying simulation have also been carried out, where two predetermined inputs for both J and K inputs, with a clock signal for CLK input, was injected into the circuit with the data rate of 1 Gbps. Its output is observed via multi-channel oscilloscope, where results are obtained with the simulation data sampling rate of 1.6 THz.

Skyrmion-based JK flip–flop with a wedge-shaped circular track

Magnetic skyrmion can be used as information carrier of logic devices because of its nano size and topological properties. Here, we introduce a wedge-shaped circular track structure, in which the cycle motion of skyrmion in the ferromagnetic track is induced by the gradient of voltage-controlled magnetic anisotropy. Compared with the straight track, the process of generation and annihilation of skyrmion is avoided due to the recycling of skyrmion. Furthermore, the logic of the JK flip–flops is successfully implemented in the wedge-shaped circular track, which provides guidance for the design of skyrmion-based sequential logic devices.

Designing of Counters using JK Flip-Flop in Quantum Dot Cellular Automata

In the post-CMOS condition an enormous development was played by the qca progress. As the CMOS improvement has a scaling tangle in focal nanometer drives, the best choice for CMOS progress was a quantum-spot cell automata progress. It has the combined thought of quantum mechanics &cell automata. QCA (quantum bit cell automata) was a quantum wonder that gives another computational stage to structure electronic circuits using quantum contacts &move information at nano level as a substitution of standard CMOS based movement. In standard CMOS improvement, transistors are used to make any robotized circuit yet in QCA, qca cells are used to make moved circuits &wire. In this paper, we proposed the breeze around counters using JK flip-flop. 2-piece &4-piece counters are executed using the QCA Technology. The perspective was filtered through &the solace of the circuit was surrendered by using QCA sketcher contraption.

Compact QCA based JK Flip-Flop for Digital System

Considering the roadmap of silicon, the high rate of shrinkage in dimensions of typical MOS circuits, genuine difficulties endanger this innovation. A quantum-dot cellular automaton (QCA) is an outstanding and conceivable answer for substitution of CMOS technology. Sequential circuits contain combinational circuits and memory elements which store binary information. Latches and Flip-flop circuits are the basic components of computerized circuits, along these lines. The area and energy of the sequential circuits has to be minimal for speed applications. Traditional implementation of JK flip-flop circuits requires more cells and consumes more energy. This paper proposes a compact and low energy JK Flip-flop, designed in CAD tool, QCADesigner. Analysis of energy was performed using the CAD tool, QCADesigner-E. The experimental results obtained in the proposed paper demonstrate the reduction in the cell count which in turn brings down the complexity of the circuit when compared to the reference QCA based JK Flip-flop circuits and it also shows a reduction in energy and area.

Novel Characterizations of the JK Bistables (Flip Flops)

The JK flip flop is a flexible type of bistable elements that has extensive uses in digital electronics and control circuits. It is usually described by its characteristic equation or next-state table (used for analysis purposes) and its excitation table (used for synthesis purposes). This paper explores a variety of novel characterizations of JK flip flops. First, equational and implicational descriptions are presented, and methods of logic deduction are utilized to produce complete statements of all propositions that are true for a general JK flip flop. Next, methods of Boolean-equation solving are employed to find all possible ways to express the excitations in terms of the present state and next state. The concept of Boolean quotient is used to impose certain requirements so as to find particularly useful expressions of the excitations. Relations of JK flip flops to other types of flip flops are also explored. This paper is expected to provide an immediate pedagogical benefit, and to help facilitate the analysis and synthesis of sequential digital circuits.

New Divider Design for Stochastic Computing

Stochastic computing (SC) is an unconventional computing paradigm which enables low power and massive parallelism in various applications. The numerical values in SC are represented as random bit-streams and interpreted as probabilities. The SC design provides the low-cost arithmetic units, while suffering from long latency and accuracy degradation. The division operation is the most challenging in SC. Chen et al. have recently developed a stochastic divider, called correlated divider (CORDIV), by exploiting the conditional probability. It has been proved that the CORDIV has a lower hardware cost than the previous designs and provides good accuracy performance. This brief presents a new stochastic divider, which includes one saturating subtractor and one JK flip flop. The subtractor is designed by taking advantage of correlation among inputs. Simulation results reveal that the proposed divider has the same accuracy performance as CORDIV. However, the new divider has competitive advantages over CORDIV. With applications to the piecewise linear function implementation, the proposed design is superior to the finite state machine (FSM)-based method in terms of accuracy and hardware cost.