Jitter In Ring Oscillators Research Articles

Random Telegraph Noise Modeling for Circuit Analysis: RTN in Ring Oscillators

In highly scaled MOSFETs, random telegraph noise (RTN) can decrease the reliability and yield of circuits. RTN is produced by charge trapping, which in large devices results in <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1/f$ </tex-math></inline-formula> noise. We derived analytical formulations for modeling the impact of RTN in the delay of inverters and in the jitter of ring oscillators. We show that the parameters of interest when characterizing RTN for circuit analysis are the distribution of current deviations and the density of traps in the space of area, energy and in log-space of time-constants. The model gives a direct relation between jitter variance in oscillators (or delay variance in inverters) and the power spectral density of RTN, which includes <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1/f$ </tex-math></inline-formula> noise. The formulations can be written using time- or frequency-domain parameters.

Frequency-Boost Jitter Reduction for Voltage-Controlled Ring Oscillators

Ring oscillators (ROs) are popular due to their small area, modest power, wide tuning range, and ease of scaling with process technology. However, their use in many applications is limited due to poor phase noise and jitter performance. Thermal noise and flicker noise contribute jitter that decreases inversely with oscillation frequency. This paper describes a frequency-boost technique to reduce jitter in ROs. We boost the internal oscillation frequency and introduce a frequency divider following the oscillator to maintain the desired output frequency. This approach offers reduced jitter as well as the opportunity to trade off output jitter with power for dynamic performance management. The oscillator has 32 operating modes, corresponding to different values for the ring size and frequency division. In a 0.5- $\mu \text{m}$ CMOS process, the highest oscillation frequency achieved is 25 MHz with a root-mean-square period jitter of 54 ps and a power consumption of $817~\mu \text{W}$ at 5 V supply. A jitter model for current-starved oscillators was derived and verified by measurement; a direct relationship between oscillation frequency and jitter was derived and measured. Compared with other oscillators, this design achieves the highest performance in terms of jitter per unit interval and figure-of-merit. The performance is expected to improve in more advanced technologies. The results are summarized to offer design guidance based on the frequency-boost technique.

Theory and implementation of a very high throughput true random number generator in field programmable gate array

The contribution of this paper is proposing a new entropy extraction mechanism based on sampling phase jitter in ring oscillators to make a high throughput true random number generator in a field programmable gate array (FPGA) practical. Starting from experimental observation and analysis of the entropy source in FPGA, a multi-phase sampling method is exploited to harvest the clock jitter with a maximum entropy and fast sampling speed. This parametrized design is implemented in a Xilinx Artix-7 FPGA, where the carry chains in the FPGA are explored to realize the precise phase shifting. The generator circuit is simple and resource-saving, so that multiple generation channels can run in parallel to scale the output throughput for specific applications. The prototype integrates 64 circuit units in the FPGA to provide a total output throughput of 7.68 Gbps, which meets the requirement of current high-speed quantum key distribution systems. The randomness evaluation, as well as its robustness to ambient temperature, confirms that the new method in a purely digital fashion can provide high-speed high-quality random bit sequences for a variety of embedded applications.

Note: The design of thin gap chamber simulation signal source based on field programmable gate array.

The Thin Gap Chamber (TGC) is an important part of ATLAS detector and LHC accelerator. Targeting the feature of the output signal of TGC detector, we have designed a simulation signal source. The core of the design is based on field programmable gate array, randomly outputting 256-channel simulation signals. The signal is generated by true random number generator. The source of randomness originates from the timing jitter in ring oscillators. The experimental results show that the random number is uniform in histogram, and the whole system has high reliability.

An ultra-compact LC-VCO using a stacked-spiral inductor

This paper proposes an ultra compact LC-VCO. Due to the speed-up of CMOS digital circuits, jitter of ring oscillators is becoming a critical problem. Even though an LC-VCO has a better phase noise, a layout size of on-chip inductor is a problem as a clock generator. Thus, the proposed LC-VCO consists of a very compact stacked-spiral inductor and active components placed are beneath the inductor. The VCO is implemented by a 65-nm CMOS process, and the chip area is only 594µm2. This VCO achieves a phase noise of -93dBc/Hz@1MHz, power consumption of 0.36mW, and FOMA of 210dBc/Hz.

Analytical Equations for Nonlinear Phase Errors and Jitter in Ring Oscillators

In this paper, we present a simple analytical equation for capturing phase errors in 3-stage ring oscillators. The model, based on a simple but useful idealization of the ring oscillator, is provably exact for small noise perturbations. Despite its simplicity and purely analytical form, our model correctly captures the time- dependent sensitivity of oscillator phase to external perturbations. It is thus well suited for estimating both qualitative and quantitative features of ring oscillator phase response to internal noises, as well as to power, ground and substrate interference. The nonlinear nature of the model makes it suitable for predicting injection locking as well. Comparisons of the new model with existing phase models are provided, and its application for correct prediction of thermal jitter demonstrated. Requiring knowledge only of the amplitude and frequency of the oscillator, the model is ideally suited for early design exploration at the system and circuit levels.

Jitter in ring oscillators

Jitter in ring oscillators is theoretically described, and predictions are experimentally verified. A design procedure is developed in the context of time domain measures of oscillator jitter in a phase-locked loop (PLL). A major contribution is the identification of a design figure of merit /spl kappa/, which is independent of the number of stages in the ring. This figure of merit is used to relate fundamental circuit-level noise sources (such as thermal and shot noise) to system-level jitter performance. The procedure is applied to a ring oscillator composed of bipolar differential pair delay stages. The theoretical predictions are tested on 155 and 622 MHz clock-recovery PLL's which have been fabricated in a dielectrically isolated, complementary bipolar process. The measured closed-loop jitter is within 10% of the design procedure prediction.