Irregular Applications Research Articles

A hierarchical data partitioning strategy for irregular applications: a case study in digital pathology

A hierarchical data partitioning strategy for irregular applications: a case study in digital pathology

Semi-automated minimization of brick-mortar segmentation errors in 3D historical wall reconstruction

In current practices of geometric modeling and building information modeling (BIM) of architectural heritage, point cloud data acquired from site surveys is segmented into parts that correspond to actual building elements. Deep learning methods are used to automate the segmentation processes; however, each historical building presents unique challenges due to distinct construction techniques, irregular applications, deformations, and wear on the surveyed surfaces, and due to these peculiarities, segmented point cloud data may display local errors in the detection of individual architectural elements. This paper presents a method for post-processing segmented point cloud data to semi-automatically detect building elements such as bricks in historical walls. Results show that this approach, which involves testing neighborhoods of points and classified areas to identify and correct misclassified points, diminishes segmentation errors and reconstructs bricks close to their original form.

Autovesk: Automatic Vectorized Code Generation from Unstructured Static Kernels Using Graph Transformations

Leveraging the SIMD capability of modern CPU architectures is mandatory to take full advantage of their increased performance. To exploit this capability, binary executables must be vectorized, either manually by developers or automatically by a tool. For this reason, the compilation research community has developed several strategies for transforming scalar code into a vectorized implementation. However, most existing automatic vectorization techniques in modern compilers are designed for regular codes, leaving irregular applications with non-contiguous data access patterns at a disadvantage. In this article, we present a new tool, Autovesk, that automatically generates vectorized code from scalar code, specifically targeting irregular data access patterns. We describe how our method transforms a graph of scalar instructions into a vectorized one, using different heuristics to reduce the number or cost of instructions. Finally, we demonstrate the effectiveness of our approach on various computational kernels using Intel AVX-512 and ARM SVE. We compare the speedups of Autovesk vectorized code over GCC, Clang LLVM, and Intel automatic vectorization optimizations. We achieve competitive results on linear kernels and up to 11× speedups on irregular kernels.

CSMV: A highly scalable multi-versioned software transactional memory for GPUs

This paper introduces CSMV (Client Server Multiversioned), a multi-versioned Software TM (STM) for GPUs that adopts an innovative client-server design. By decoupling the execution of transactions from their commit process, CSMV provides two main benefits: (i) it enables the use of fast on chip memory to access the global metadata used to synchronize transaction (ii) it allows for implementing highly efficient collaborative commit procedures, tailored to take full advantage of the architectural characteristics of GPUs.Via an extensive experimental study, we show that CSMV achieves up to 3 orders of magnitude speed-ups with respect to state of the art STMs for GPUs and that it can accelerate by up to 20× irregular applications running on state of the art STMs for CPUs.

Lifeline-based load balancing schemes for Asynchronous Many-Task runtimes in clusters

A popular approach to program scalable irregular applications is Asynchronous Many-Task (AMT) Programming. Here, programs define tasks according to task models such as dynamic independent tasks (DIT) or nested fork-join (NFJ). We consider cluster AMTs, in which a runtime system maps the tasks to worker threads in multiple processes.Thereby, dynamic load balancing can be achieved via cooperative work stealing, coordinated work stealing, or work sharing. A well-performing cooperative work stealing variant is the lifeline scheme. While previous implementations of this scheme are restricted to single-worker processes, a recent hybrid extension combines it with intra-process work sharing between multiple workers. The hybrid scheme, which was proposed for both DIT and NFJ, comes at the price of a higher complexity.This paper investigates whether this complexity is indispensable for multi-worker processes by contrasting the hybrid scheme with a novel pure work stealing extension of the lifeline scheme to multiple workers. We independently implemented the extension for DIT and NFJ. In experiments based on four benchmarks, we observed the pure scheme to be on a par or even outperform the hybrid one by up to 18% for DIT and up to 5% for NFJ.Building on this main result, we studied a modification of the pure scheme, which prefers local over global victims, and more heavily loaded over less loaded ones. The modification improves the performance of the pure scheme by up to 15%. Finally, we explored whether the lifeline scheme can profit from a change to coordinated work stealing. We developed a coordinated multi-worker implementation for DIT and observed a performance improvement over the cooperative scheme by up to 17%.

A Fine-grained Asynchronous Bulk Synchronous parallelism model for PGAS applications

The Partitioned Global Address Space (PGAS) model is well suited for executing irregular applications on cluster-based systems, due to its efficient support for short, one-sided messages. Separately, the actor model has been gaining popularity as a productive asynchronous message-passing approach for distributed objects in enterprise and cloud computing platforms, typically implemented in languages such as Erlang, Scala or Rust. To the best of our knowledge, there has been no past work on using the actor model to deliver both productivity and scalability to irregular PGAS applications with large number of small messages.In this paper, we introduce a new programming system for PGAS applications, in which point-to-point remote operations can be expressed as fine-grained asynchronous actor messages. In our approach, the programmer does not need to worry about programming complexities related to message aggregation and termination detection. Our approach can be viewed as extending the classical Bulk Synchronous Parallelism model with fine-grained asynchronous communications within a phase or superstep. We believe that our approach offers a desirable point in the productivity-performance space for PGAS applications, with more scalable performance and higher productivity relative to past approaches. Specifically, for seven irregular mini-applications from the Bale Kernels and three graph kernels executed using 2048 cores in the NERSC Cori system, our approach shows geometric mean performance improvements of ≥20× relative to standard PGAS versions (UPC and OpenSHMEM) while maintaining comparable productivity to those versions.This is an extended version of the conference paper “A Productive and Scalable Actor-Based Programming System for PGAS Applications” (Paul et al., 2022)[1] from ICCS 2022.

Exploring Memory Access Similarity to Improve Irregular Application Performance for Distributed Hybrid Memory Systems

With the increasing problem complexity, more irregular applications are deployed on high-performance clusters due to the parallel working paradigm, and yield irregular memory access behaviors across nodes. However, the irregularity of memory access behaviors is not comprehensively studied, which results in low utilization of the integrated hybrid memory system compositing of stacked DRAM and off-chip DRAM. To address this problem, we devise a novel method called <i>Similarity-Managed Hybrid Memory System</i> ( <i>SM-HMS</i> ) to improve the hybrid memory system performance by leveraging the memory access similarity among nodes in a cluster. Within <i>SM-HMS</i> , two techniques are proposed, <i>Memory Access Similarity Measuring</i> and <i>Similarity-based Memory Access Behavior Sharing</i> . To quantify the memory access similarity, memory access behaviors of each node are vectorized, and the distance between two vectors is used as the memory access similarity. The calculated memory access similarity is used to share memory access behaviors precisely across nodes. With the shared memory access behaviors, <i>SM-HMS</i> divides the stacked DRAM into two sections, the <i>sliding window section</i> and the <i>outlier section</i> . The shared memory access behaviors guide the replacement of the <i>sliding window section</i> while the <i>outlier section</i> is managed in the LRU manner. Our evaluation results with a set of irregular applications on various clusters consisting of up to 256 nodes have shown that <i>SM-HMS</i> outperforms the state-of-the-art approaches, <i>Cameo</i> , <i>Chameleon</i> , and <i>Hyrbid2</i> , on job finish time reduction by up to <inline-formula><tex-math notation="LaTeX">$58.6\%$</tex-math></inline-formula> , <inline-formula><tex-math notation="LaTeX">$56.7\%$</tex-math></inline-formula> , and <inline-formula><tex-math notation="LaTeX">$31.3\%$</tex-math></inline-formula> , with <inline-formula><tex-math notation="LaTeX">$46.1\%$</tex-math></inline-formula> , <inline-formula><tex-math notation="LaTeX">$41.6\%$</tex-math></inline-formula> , and <inline-formula><tex-math notation="LaTeX">$19.3\%$</tex-math></inline-formula> on average, respectively. <i>SM-HMS</i> can also achieve up to <inline-formula><tex-math notation="LaTeX">$98.6\%$</tex-math></inline-formula> ( <inline-formula><tex-math notation="LaTeX">$91.9\%$</tex-math></inline-formula> on average) of the ideal hybrid memory system performance.

Irregular accesses reorder unit: improving GPGPU memory coalescing for graph-based workloads

GPGPU architectures have become the dominant platform for massively parallel workloads, delivering high performance and energy efficiency for popular applications such as machine learning, computer vision or self-driving cars. However, irregular applications, such as graph processing, fail to fully exploit GPGPU resources due to their divergent memory accesses that saturate the memory hierarchy. To reduce the pressure on the memory subsystem for divergent memory-intensive applications, programmers must take into account SIMT execution model and memory coalescing in GPGPUs, devoting significant efforts in complex optimization techniques. Despite these efforts, we show that irregular graph processing still suffers from low GPGPU performance. We observe that in many irregular applications the mapping of data to threads can be safely changed. In other words, it is possible to relax the strict relationship between thread and data processed to reduce memory divergence. Based on this observation, we propose the Irregular accesses Reorder Unit (IRU), a novel hardware extension tightly integrated in the GPGPU pipeline. The IRU reorders data processed by the threads on irregular accesses to improve memory coalescing, i.e., it tries to assign data elements to threads as to produce coalesced accesses in SIMT groups. Furthermore, the IRU is capable of filtering and merging duplicated accesses, significantly reducing the workload. Programmers can easily utilize the IRU with a simple API, or let the compiler issue instructions from our extended ISA. We evaluate our proposal for state-of-the-art graph-based algorithms and a wide selection of applications. Results show that the IRU achieves a memory coalescing improvement of 1.32x and a 46% reduction in the overall traffic in the memory hierarchy, which results in 1.33x speedup and 13% energy savings on average, while incurring in a small 5.6% area overhead.

Lightweight asynchronous scheduling in heterogeneous reconfigurable systems

The trend for heterogeneous embedded systems is the integration of accelerators and general-purpose CPU cores on the same die. In these integrated architectures, like the Zynq UltraScale+ board (CPU+FPGA) that we target in this work, hardware support for shared memory and low-overhead synchronization between the accelerator and the CPU cores make the case for exploring strategies that exploit a tight collaboration between the CPUs and the accelerator. In this paper we propose a novel lightweight scheduling strategy, FastFit, targeted to FPGA accelerators, and a new scheduler based on it, named MultiFastFit, which asynchronously tackles heterogeneous systems comprised of a variety of CPU cores and FPGA IPs. Our strategy significantly reduces the overhead to automatically compute the near-optimal chunksizes when compared to a previous state-of-the-art auto-tuned approach, which makes our approach more suitable for fine-grained applications. Additionally, our scheduler MultiFastFit has been designed to enable the efficient co-execution of work among compute devices in such a way that all the devices are busy while minimizing the load unbalance.Our approaches have been evaluated using four benchmarks carefully tuned for the low-power UltraScale+ platform. Our experiments demonstrate that the FastFit strategy always finds the near-optimal FPGA chunksize for any device configuration at a reasonable cost, even for fine-grained and irregular applications, and that heterogeneous CPU+FPGA co-executions that exploit all the compute devices are usually faster and more energy efficient than the CPU-only and FPGA-only executions. We have also compared MultiFastFit with other state-of-the-art scheduling strategies, finding that it outperforms other auto-tuned approach up to 2x and it achieves similar results to manually-tuned schedulers without requiring an offline search of the ideal CPU-FPGA partition or FPGA chunk granularity.

Hardware Acceleration of High-Performance Computational Flow Dynamics Using High-Bandwidth Memory-Enabled Field-Programmable Gate Arrays

Scientific computing is at the core of many High-Performance Computing applications, including computational flow dynamics. Because of the utmost importance to simulate increasingly larger computational models, hardware acceleration is receiving increased attention due to its potential to maximize the performance of scientific computing. Field-Programmable Gate Arrays could accelerate scientific computing because of the possibility to fully customize the memory hierarchy important in irregular applications such as iterative linear solvers. In this article, we study the potential of using Field-Programmable Gate Arrays in High-Performance Computing because of the rapid advances in reconfigurable hardware, such as the increase in on-chip memory size, increasing number of logic cells, and the integration of High-Bandwidth Memories on board. To perform this study, we propose a novel Sparse Matrix-Vector multiplication unit and an ILU0 preconditioner tightly integrated with a BiCGStab solver kernel. We integrate the developed preconditioned iterative solver in Flow from the Open Porous Media project, a state-of-the-art open source reservoir simulator. Finally, we perform a thorough evaluation of the FPGA solver kernel in both stand-alone mode and integrated in the reservoir simulator, using the NORNE field, a real-world case reservoir model using a grid with more than 10 5 cells and using three unknowns per cell.

An adaptive self‐scheduling loop scheduler

AbstractMany shared‐memory parallel irregular applications, such as sparse linear algebra and graph algorithms, depend on efficient loop scheduling (LS) in a fork‐join manner despite that the work per loop iteration can greatly vary depending on the application and the input. Because of the importance of LS, many different methods (e.g., workload‐aware self‐scheduling) and parameters (e.g., chunk size) have been explored to achieve reasonable performance, and many of these methods require expert prior knowledge about the application and input before runtime. This work proposes a new LS method that requires little to no expert knowledge to achieve speedups close to those of tuned LS methods by self‐managing chunk size based on a heuristic of throughput and using work‐stealing to recover from workload imbalances. This method, named iCh, is implemented into libgomp for testing. It is evaluated against OpenMP's guided, dynamic, and taskloop methods and is evaluated against BinLPT and generic work‐stealing on an array of applications that includes: a synthetic benchmark, breadth‐first search, K‐Means, the molecular dynamics code LavaMD, and sparse matrix‐vector multiplication. On a 28 thread Intel system, iCh is the only method to always be one of the top three LS methods. On average across all applications, iCh is within of the best method and is even able to outperform other LS methods for breadth‐first search and K‐Means.

Benchmarking the performance of irregular computations in AutoDock-GPU molecular docking

Irregular applications can be found in different scientific fields. In computer-aided drug design, molecular docking simulations play an important role in finding promising drug candidates. AutoDock is a software application widely used for predicting molecular interactions at close distances. It is characterized by irregular computations and long execution runtimes. In recent years, a hardware-accelerated version of AutoDock, called AutoDock-GPU, has been under active development. This work benchmarks the recent code and algorithmic enhancements incorporated into AutoDock-GPU. Particularly, we analyze the impact on execution runtime of techniques based on early termination. These enable AutoDock-GPU to explore the molecular space as necessary, while safely avoiding redundant computations. Our results indicate that it is possible to achieve average runtime reductions of 50% by using these techniques. Furthermore, a comprehensive literature review is also provided, where our work is compared to relevant approaches leveraging hardware acceleration for molecular docking.

Reducing queuing impact in streaming applications with irregular dataflow

Throughput-oriented streaming applications on massive data sets are a prime candidate for parallelization on wide-SIMD platforms, especially when inputs are independent of one another. Many such applications are represented as a pipeline of compute nodes connected by directed edges. Here, we study applications with irregular dataflow, i.e., those where the number of outputs produced per input to a node is data-dependent and unknown a priori. We consider how to implement such applications on wide-SIMD architectures, such as GPUs, where different nodes of the pipeline execute cooperatively on a single processor.To promote greater SIMD parallelism, irregular application pipelines can utilize queues to gather and compact multiple data items between nodes. However, the decision to introduce a queue between two nodes must trade off benefits to occupancy against costs associated with managing the queue and scheduling the nodes at its endpoints. Moreover, once queues are introduced to an application, their relative sizes impact the frequency with which the application switches between nodes, incurring scheduling and context-switching overhead.This work examines two optimization problems associated with queues. First, given a pipeline with queues between each two nodes and a fixed total budget for queue space, we consider how to choose the relative sizes of inter-node queues to minimize the frequency of switching between nodes. Second, we consider which pairs of successive nodes in a pipeline should have queues between them to maximize overall application throughput. We give an empirically useful approximation to the first problem that allows for an analytical solution and formulate a performance model for the second that directs implementation toward higher-performing strategies.We implemented our analyses and resulting optimizations in applications built using Mercator, a framework we designed to support irregular streaming applications on NVIDIA GPUs. We demonstrate that these optimizations yield meaningful performance improvements for several benchmark Mercator applications.

On The Importance Of The Human Body, Nitrates

Currently, the role of food security in maintaining public health is high. Gastrointestinal and many other diseases can develop if the composition of food does not meet sanitary and hygienic requirements. As a result of the development of agro-industry, as a result of excessive and irregular application of nitrogen fertilizers, the amount of nitrate in fruits and vegetables is increasing. The negative and positive effects of nitrates on the body have been identified, and it has been found that nitrates consumed on a daily basis are important in maintaining our health.

Principle of Conservation of the Administrative Act and Revocation of Public Procurement in a City in Perú

Aims: The preservation of the act as a principle must be verified objectively through a review of the errors considered non-transcendental. The objective of this research is to determine the perception of officials on the application of the Principle of conservation of the administrative act and the ex officio nullity of the contracts entered into by the La Libertad Regional Government.&#x0D; Methodology: An approach quantitative, descriptive, explanatory was applied. The techniques applied were the interview, observation, documentary analysis and test on a sample of 60 workers linked to the functions of the public contracting process.&#x0D; Results: The results showed an irregular application of the principle of conservation of the administrative act and a resolution of procurements on a regular basis. The perception of the La Libertad Regional Government officials was negative, because not all the valid elements were found to preserve an administrative act.&#x0D; Conclusion: Deficiency was observed in the principle of the presumption of veracity, validity of the requirements to preserve the administrative act, non-existence of the judicial object and content, deficiency in the fulfillment of those prevented by law, deficiency in the fulfillment of the impediments provided for in the Law Contracting and violation of the regulations that.

Svelto: High-Level Synthesis of Multi-Threaded Accelerators for Graph Analytics

Graph analytics are an emerging class of irregular applications. Operating on very large datasets, they present unique behaviors, such as fine-grained, unpredictable memory accesses, and highly unbalanced task level parallelism, that make existing high-performance general-purpose processors or accelerators (e.g., GPUs) suboptimal. To address these issues, research and industry are developing a variety of custom accelerator designs for this application area, including solutions based on reconfigurable devices (Field Programmable Gate Arrays). These new approaches often employ High-Level Synthesis (HLS) to Speed up the development of the accelerators. In this paper, we propose a novel architecture template for the automatic generation of accelerators for graph analytics and irregular applications. The architecture template includes a dynamic task scheduling mechanism, a parallel array of accelerators that enables supporting task-level parallelism with context switching, and a related multi-channel memory interface that decouples communication from computation and provides support for fine-grained atomic memory operations. We discuss the integration of the architectural template in an HLS flow, presenting the necessary modifications to enable automatic generation of the custom architectures starting from OpenMP annotated code. We evaluate our approach first by synthesizing and exploring triangle counting, a common graph algorithm, and then by synthesizing custom designs for a set of graph database benchmark queries, representing series of graph pattern matching routines. We compare the synthesized accelerators with previous state-of-the-art methodologies for the synthesis of parallel architectures, showing that the proposed approach allows reducing resource usage by optimizing the number of accelerators replicas without any performance penalty.

Consensus on the application of negative pressure wound therapy of diabetic foot wounds.

Because China is becoming an aging society, the incidence of diabetes and diabetic foot have been increasing. Diabetic foot has become one of the main health-related killers due to its high disability and mortality rates. Negative pressure wound therapy (NPWT) is one of the most effective techniques for the treatment of diabetic foot wounds and great progress, both in terms of research and its clinical application, has been made in the last 20 years of its development. However, due to the complex pathogenesis and management of diabetic foot, irregular application of NPWT often leads to complications, such as infection, bleeding and necrosis, that seriously affect its treatment outcomes. In 2020, under the leadership of Burns, Trauma and Tissue Repair Committee of the Cross-Straits Medicine Exchange Association, the writing group for ‘Consensus on the application of negative pressure wound therapy of diabetic foot wounds’ was established with the participation of scholars from the specialized areas of burns, endocrinology, vascular surgery, orthopedics and wound repair. Drawing on evidence-based practice suggested by the latest clinical research, this consensus proposes the best clinical practice guidelines for the application and prognostic evaluation of NPWT for diabetic foot. The consensus aims to support the formation of standardized treatment schemes that clinicians can refer to when treating cases of diabetic foot.

Potential problems in the use of patient reported outcome measures (PROMs) and reporting of PROM data in sports science.

To use an inadequate patient reported outcome measure (PROM) or use a PROM in an inappropriate way potentially influences the quality of measurement. The objectives of this study were to define potential inadequate uses of PROMs in sports research studies and estimate how often they occur. A consensus group consisting of medical researchers, statisticians, and psychometricians identified and defined potentially irregular applications of PROMs. Occurrence of these in 349 consecutive articles in sports medicine in which PROMs were used as primary outcomes was reviewed. In all, 14 different potential problems were defined, and one or several occurred in 172 of the articles (49%). These were as follows: using a PROM that was developed for a different patient group (100 cases), using two or more PROMs with identical questions (94), aggregation of domain sum scores (82), combinations of subjective and objective measures (27), using a PROM to diagnose or evaluate the individual patient (7), using a PROM for a single limb (3), recall bias (3), exclusion of domains or items (3), construction of a PROM for a specific occasion (2), categorization of the scale (2), and mixing different versions of a PROM (1). Adaption of scale scores (e. g., to percentage) when results are reported (144) carries a risk of miscalculation and distorted impression of results. Data related to uncertainty about completing the PROM and the handling of missing data were not provided in the manuscripts. In conclusion, potential problems in the use and reporting of PROMs are common in sports research, and this can influence the validity of reported results.

Introduction to the TOPC Special Issue on Innovations in Systems for Irregular Applications, Part 2

Introduction to the TOPC Special Issue on Innovations in Systems for Irregular Applications, Part 2

Automated Bug Detection for High-level Synthesis of Multi-threaded Irregular Applications

Field Programmable Gate Arrays (FPGAs) are becoming an appealing technology in datacenters and High Performance Computing. High-Level Synthesis (HLS) of multi-threaded parallel programs is increasingly used to extract parallelism. Despite great leaps forward in HLS and related debugging methodologies, there is a lack of contributions in automated bug identification for HLS of multi-threaded programs. This work defines a methodology to automatically detect and isolate bugs in parallel circuits generated with HLS. The technique relies on hardware/software Discrepancy Analysis and exploits a pattern-matching algorithm based on Finite State Automata to compare multiple hardware and software threads. Overhead, advantages, and limitations are evaluated on designs generated with an open-source HLS compiler supporting OpenMP.