Irreducible All-one Polynomial Research Articles

A Novel Multiplier Hardware Organization for Finite Fields Defined by All-One Polynomials

In this brief, a novel, energy-efficient hardware organization for a finite-field multiplier based on irreducible all-one polynomials (AOPs) is proposed. The proposed AOP multiplier organization deploys three distinct submodules, which constitute a left-shifting network (reduction), an AND network (multiplication), and a three-input XOR tree (accumulation). Previously reported state-of-the-art implementation distributes these operations to systolic arrays, which are elegant in layout but do not yield the most efficient solution. The advantages of the proposed organization compared with those reported in the literature include reduced cost and power dissipation for a given clock frequency constraint (or increased clock frequency for a given power constraint) and the absence of bypassing problems due to fewer pipeline stages. Both the previously reported and the proposed organizations have been implemented in Verilog for three different binary-field sizes using the TSMC 90 nm standard cell library and have been synthesized for three distinct frequency targets using Cadence Genus Synthesis tool. The proposed organization achieves 18%, 31%, and 19% reduction in average leakage, dynamic capacitance, and area, respectively, compared with state-of-the-art schemes and thus can be considered for energy-efficient, compact portable systems, including wireless sensors.

Low-Space Bit-Parallel Systolic Structure for AOP-Based Multiplier Suitable for Resource-Constrained IoT Edge Devices

Security and privacy issues with IoT edge devices hinder the application of IoT technology in many applications. Applying cryptographic protocols to edge devices is the perfect solution to security issues. Implementing these protocols on edge devices represents a significant challenge due to their limited resources. Finite-field multiplication is the core operation for most cryptographic protocols, and its efficient implementation has a remarkable impact on their performance. This article offers an efficient low-area and low-power one-dimensional bit-parallel systolic implementation for field multiplication in GF(2n) based on an irreducible all-one polynomial (AOP). We represented the adopted multiplication algorithm in the bit-level form to be able to extract its dependency graph (DG). We choose to apply specific scheduling and projection vectors to the DG to extract the bit-parallel systolic multiplier structure. In contrast with most of the previously published parallel structures, the proposed one has an area complexity of the order O(n) compared to the area complexity of the order of O(n2) for most parallel multiplier structures. The complexity analysis of the proposed multiplier structure shows that it exhibits a meaningful reduction in area compared to most of the compared parallel multipliers. To confirm the results of the complexity analysis, we performed an ASIC implementation of the proposed and the existing efficient multiplier structures using an ASIC CMOS library. The obtained ASIC synthesis report shows that the proposed multiplier structure displays significant savings in terms of its area, power consumption, area-delay product (ADP), and power-delay product (PDP). It offers average savings in space of nearly 33.7%, average savings in power consumption of 39.3%, average savings in ADP of 24.8%, and savings in PDP of 31.2% compared to the competitive existing multiplier structures. The achieved results make the proposed multiplier structure more suitable for utilization in resource-constrained devices such as IoT edge devices, smart cards, and other compact embedded devices.

Novel Pipelined Scalable Systolic Multiplier Based on Irreducible All-One Polynomials

A planned productive structure issued for the systolic execution of authoritative based limited field duplication over G F(2 m) in light of final 56-bit AOP is proposed in this work. We extricated a recursive increase calculation and utilized it to plan an intermittent and confined piece level reliance outline (DG) for systolic registering. The intermittent piece level DG is changed into a very smal grained DG, and the pipe coating is utilized for snappier mapping into a parallel systolic design. It doesn't require any overall correspondences for measured decline, in contrast to most current developments. The suggested bit-parallel systolic structure is similar to the parallel systolic structure, however the quantity of registers is altogether lower.

Low-Latency, Low-Area, and Scalable Systolic-Like Modular Multipliers for $GF(2^{m})$ Based on Irreducible All-One Polynomials

In this paper, an efficient recursive formulation is suggested for systolic implementation of canonical basis finite field multiplication over GF(2 m ) based on irreducible AOP. We have derived a recursive algorithm for the multiplication, and used that to design a regular and localized bit-level dependence graph (DG) for systolic computation. The bit-level regular DG is converted into a fine-grained DG by node-splitting, and mapped that into a parallel systolic architecture. Unlike most of the existing structures, it does not involve any global communications for modular reduction. The proposed bit-parallel systolic structure has the same cycle time as that of the best existing bit-parallel systolic structure, but involves significantly less number of registers. The proposed bit-parallel design has a scalable latency of l + ⌈log 2 s⌉ +1 cycles which is considerably low compared with those of existing systolic designs. Moreover, the proposed time-multiplexed structure is designed specifically for scalability of throughput and hardware-complexity to meet the area-time trade-off in resource-constrained applications while maintaining or reducing the overall latency. The ASIC synthesis report shows that the proposed bit-parallel structures offers nearly 30% saving of area and nearly 38% saving of power consumption over the best of the existing AOP-based systolic finite field multiplier.

Novel bit-parallel multiplier for [formula omitted] defined by all-one polynomial using generalized Karatsuba algorithm

In this paper, a novel bit-parallel multiplier for finite field GF(2m) defined by irreducible all-one polynomial (AOP) is proposed. We utilize a generalized Karatsuba algorithm (KA) to reduce the number of coefficient multiplications and the redundant representation to simplify polynomial modular reduction. Explicit formulae with respect to the space and time complexity of the proposed multiplier are given. By evaluating the asymptotic lower bound of the complexity, the selection of the generalized KA and decomposition of m are investigated to obtain the optimal result. Consequently, theoretical complexity analysis proved that our architecture requires even fewer logic gates than previous proposals, while it still maintains relatively low time delay. For a special class of GF(2m) generated with AOPs, it even matches the best known multipliers found in the literatures.

Low-Complexity Multiplier for $GF(2^{m})$ Based on All-One Polynomials

This paper presents an area-time-efficient systolic structure for multiplication over GF(2m) based on irreducible all-one polynomial (AOP). We have used a novel cut-set retiming to reduce the duration of the critical-path to one XOR gate delay. It is further shown that the systolic structure can be decomposed into two or more parallel systolic branches, where the pair of parallel systolic branches has the same input operand, and they can share the same input operand registers. From the application-specific integrated circuit and field-programmable gate array synthesis results we find that the proposed design provides significantly less area-delay and power-delay complexities over the best of the existing designs.

Bit-Parallel Polynomial Basis Multiplier for New Classes of Finite Fields

In this paper, three small classes of finite fields GF$(2^m)$ are found for which low complexity bit-parallel multipliers are proposed. The proposed multipliers have lower complexities compared to those based on the irreducible pentanomials. It is also shown that there does not always exist an irreducible all-one polynomial, equally-spaced polynomial, or trinomial for the new classes of fields.

Montgomery exponent architecture based on programmable cellular automata

This study presents an efficient exponent architecture for public-key cryptosystems using Montgomery multiplication based on programmable cellular automata (PCA). Multiplication is the key operation in implementing circuits for cryptosystem, as the process of encrypting and decrypting a message requires modular exponentiation which can be decomposed into multiplications. Efficient multiplication algorithm and simple architecture are the key for implementing exponentiation. Thus we employ Montgomery multiplication algorithm and construct simple architecture based on irreducible all one polynomial (AOP) in GF(2 m ). The proposed architecture has the advantage of high regularity and a reduced hardware complexity based on combining the characteristics of the irreducible AOP and PCA. The proposed architecture can be efficiently used for public-key cryptosystem.

Low-Complexity Bit-Parallel Multipliers for a Class of Gf(2m) Based on Modified Booth’s Algorithm

This investigation presents an effective algorithm for computing multiplication over a class of GF(2m) based on both irreducible all one polynomials (AOPs) and equally spaced polynomials (ESPs). The proposed AOP-based multiplier uses the modified Booth’s algorithm to develop a new multiplexer-based bit-parallel multiplier that is simple and modular and such properties are important for VLSI hardware implementation. The multiplier requires [m/4](m+1) MUX4×1 and (1.5m2 +0.5m-1) XOR gates. Its time delay is not greater than TM +(3+log2[m/4])TX, where TM and TX are the time delays of MUX4X1 and 2-input XOR gate, respectively. For a certain degree, an irreducible ESP with a high degree can be obtained from a corresponding irreducible AOP with a relatively very low degree. Using the subword parallel processing, the proposed AOP-based multiplier with low degree can also be adopted to realize ESP-based multipliers with high degrees.

Low Complexity Bit-Parallel Multiplier for GF(2^m) Defined by All-One Polynomials Using Redundant Representation

This paper presents a new bit-parallel multiplier for the finite field GF(2/sup m/) defined by an irreducible all-one polynomial. In order to reduce the complexity of the multiplier, we introduce a redundant representation and use the well-known multiplication method proposed by Karatsuba. The main idea is to combine the redundant representation and the Karatsuba method to design an efficient bit-parallel multiplier. As a result, the proposed multiplier requires about 25 percent fewer AND/XOR gates than the previously proposed multipliers using an all-one polynomial, while it has almost the same time delay as the previously proposed ones.

Design of Montgomery Multiplication Architecture Based on Programmable Cellular Automata

This study presents a Montgomery multiplication architecture that uses an irreducible all one polynomial (AOP) in GF(2m) based on a programmable cellular automata (PCA). The proposed architecture has the advantage of high regularity and a reduced latency based on combining the characteristics of the irreducible AOP and PCA. The proposed architecture can be used to implement modular exponentiation, division, and inversion architectures.

A new construction of Massey-Omura parallel multiplier over GF(2/sup m/)

The Massey-Omura multiplier of GF(2/sup m/) uses a normal basis and its bit parallel version is usually implemented using m identical combinational logic blocks whose inputs are cyclically shifted from one another. In the past, it was shown that, for a class of finite fields defined by irreducible all-one polynomials, the parallel Massey-Omura multiplier had redundancy and a modified architecture of lower circuit complexity was proposed. In this article, it is shown that, not only does this type of multiplier contain redundancy in that special class of finite fields, but it also has redundancy in fields GF(2/sup m/) defined by any irreducible polynomial. By removing the redundancy, we propose a new architecture for the normal basis parallel multiplier, which is applicable to any arbitrary finite field and has significantly lower circuit complexity compared to the original Massey-Omura normal basis parallel multiplier. The proposed multiplier structure is also modular and, hence, suitable for VLSI realization. When applied to fields defined by the irreducible all-one polynomials, the multiplier's circuit complexity matches the best result available in the open literature.

Low complexity bit-parallel multipliers for a class of finite fields

New implementations of bit-parallel multipliers for a class of finite fields are proposed. The class of finite fields is constructed with irreducible AOPs (all one polynomials) and ESPs (equally spaced polynomials). The size and time complexities of our proposed multipliers are lower than or equal to those of the previously proposed multipliers of the same class.

Modular construction of low complexity parallel multipliers for a class of finite fields GF(2/sup m/)

Structures for parallel multipliers of a class of fields GF(2/sup m/) based on irreducible all one polynomials (AOP) and equally spaced polynomials (ESP) are presented. The structures are simple and modular, which is important for hardware realization. Relationships between an irreducible AOP and the corresponding irreducible ESPs have been exploited to construct ESP-based multipliers of large fields by a regular expansion of the basic modules of the AOP-based multiplier of a small field. Some features of the structures also enable a fast implementation of squaring and multiplication algorithms and therefore make fast exponentiation and inversion possible. It is shown that, if for a certain degree, an irreducible AOP as well as an irreducible ESP exist, then from the complexity point of view, it is advantageous to use the ESP-based parallel multiplier. >