IP Integration Research Articles

The Effectiveness of Meta-Universe on Beauty Brands

Famous worldwide corporations have used the meta-universe marketing technique in recent years: Givenchy built a virtual beauty salon, Givenchy Beauty House, and Mac linked virtual idols. AYAYI, Estee Lauder launched the world's most famous paintings of digital collections, L'Oreal created Reds of Worth Non-Fungible Token (NFT) art, and so on, leading to the research question: how does the meta-universe empower beauty businesses to achieve greater marketing and sales? The study concluded that: First, the quality of the consumer environment is strongly tied to sales via the employment of Virtual Reality (VR) and Augmented Reality (AR) technologies to enhance the realism of the consumer environment in the meta-universe scene. Second, as the meta-universe community is built to suit customers' social requirements, social demands are becoming increasingly prominent in consumer demand. Third, the added value of the brand is to increase market competitiveness through the integration of IP and NFT promotions to increase the added value of the brand. The main contribution of this article is to propose new ideas for beauty brands to boost brand creation and consumption using meta-universe marketing.

Driving Adoption of Advanced IC Packaging in Automotive Applications

For years automotive semiconductors, have been governed by small, low power Integrated Circuits (ICs) purpose built for specific functions. These Microcontroller Units (MCUs), deployed on the edge of the compute topology are typically low-power, low-performance parts. Built on legacy nodes (130nm+) on well-established packaging technology (often wirebond die on QFN-style packages), they demonstrated incremental improvements from a silicon and packaging perspective. With the adoption of software defined vehicles (SDV), the evolution of advanced driver assist systems (ADAS), and feature rich in-vehicle infotainment (IVI), the per vehicle compute power has grown exponentially per vehicle, colloquially, known as “data centers on wheels”. With this growth has come the need to adopt newer packaging techniques to improve system latency, bandwidth, compute power, and IP integration and reducing system footprint via 3D stacking – all fabricated on leading edge nodes. Advanced packaging has seen tremendous growth and adoption in the data center and client ecosystems – the next hurdle is addressing the safety and reliability focused requirements of automotives; extended useful lifespan of 10yrs+, and weathering harsher environmental conditions of thermal extremes, vibration, and EMC, and mixed IP integration. This talk will address the areas of focus for adopting heterogenous integration and advanced automotive packaging for automotives such as, qualification and formulation of materials to minimize traditional packaging yield concerns, introduction of new thermal interface materials aligned with new liquid cooled ECUs and testing to ensure zero defects across chiplets and memory; with broader test coverage and the adoption of Known Good Die (KGD). Additionally, the talk will cover the importance of driving industry standardization regarding die-to-die communication protocols, form factors, power delivery, system integration, and qualifying/enveloping new failure modes from the current baseline AEC-Q100 requirements brought on by various 2.5D and 3D packaging.

Integration of hydrochemical and induced polarization analysis for leachate localization in a municipal landfill

Landfills have been identified as a significant concern to the surrounding surface and groundwater ecosystem because of the discharge of leachate. To tackle the uncertain localization of the contamination plume due to low sampling densities, a combination of hydrochemical analysis and induced polarization survey (IP) is employed to characterize the leachate in a municipal landfill. The polarization effect in the contaminated area is significantly higher than expected for landfill sites, but relatively low chargeability zones (<100 mV/V) indicating the distribution of leachate are observed inside high conductivity (>600 mS/m) areas. With reliable geophysical results confirmed by similar formation factors from both field and laboratory data, the abnormal high polarization effect is influenced by installed steel sheet piles next to the survey cable. In addition, we successfully identify linear relationship between the geophysical responses and dominant inorganic conservative compounds (Cl- and Na+) from the leachate plume. The gentle variations of borehole chemical parameters show that the plume is not affected by a continuous contamination source any more, indicating that the steel sheet pile effectively cut off the contamination from the leachate tanks. In conclusion, the integration of IP and hydrochemical data is an excellent way to locate contaminated zones and monitor the behaviors of leachate plume in the landfill.

Implementing the Individual Placement and Support approach in institutional settings for employment and mental health services – perceptions and challenges from a case study in Denmark

ABSTRACT ‘Individual Placement and Support’ (IPS) is a supported employment approach targeted at people with severe mental health problems. A central principle in IPS is the integration of mental health and employment services. In Denmark, IPS has been implemented through cross-sectoral collaboration between municipal public employment services and regional mental health services. This study examines the implementation of IPS through a case-study of four IPS units. The study is theoretically informed by an institutional logic approach, and based on document analysis and interviews with stakeholders in IPS units, public employment services and mental health services. The findings show how the IPS units came under pressure to adjust the model in order to fit into the common strategies of public employment services, which favoured internships and wage subsidies. The integration of IPS with mental health services was also found to be challenging as mental health services regarded IPS as a parallel service rather than a mutual responsibility. Parts of the standardised procedures set by the IPS fidelity scale were challenged by managers from both sectors. In spite of these challenges, both sectors regarded IPS as an innovative and meaningful approach and supported the sustainability of the programme.

DSR and OLSR routing protocol based performance evaluation and integration on MIP with MANET

This paper describes the integration of mobile IP in mobile ad hoc network (MIPMANET) in large area network (LAN) between 8 nodes, where latency, delay, throughput is considered for the quality of service (QoS) consideration. For the best result of MIPMANET, the Dynamic Source Routing Protocol (DSR) and Optimized Link State Routing Protocol (OLSR) are considered. Although MANET has other routing protocols, the DSR performs better in MIPMANET integration in NS2. Mobile IP is applied for doing the dynamic topology to static topology as the nodes are flexible in an ad-hoc network. Simulation result suggests that the MANET performs better in DSR with MIP as the amount of packet drop is low and throughput is high

Towards a Conceptual Case for Harmonisation of Intellectual Property Laws Within the East African Community

This article attempts to build a conceptual justification for harmonisation of intellectual property laws within the East African Community (EAC). In this regard, the article establishes the conceptual link between IP and regional integration to provide a general context regarding the place of IP in regional economic integration. To establish and expound on the linkages, several claims and arguments are made in the article. First, that there exists a critical role for the law in establishing and developing regional economic integration. Second, that since IP rights are principally constructs of the law, it follows that such rights and their principles are equally vital for regional economic integration. Third, and as a consequence of the foregoing general linkages, IP rights are indeed relevant for the attainment of the four freedoms of the EAC Common Market, namely, the free movement of capital, labour, goods and services. Fourth, considering their character as notions of law, legal and institutional differences in IP rights frameworks are in fact legal barriers to the realisation of the EAC Common Market objectives. This creates the need for harmonisation of such laws. KeyWords: Harmonisation, Intellectual Property, Regional Economic Integration, East African Community.

Generation of Abstract Driver Models for IP Integration Verification

This paper proposes a new application of formal methods in the domain of low-level software (firmware) development of Embedded Systems. The development of low-level device drivers is difficult because of the complex interaction between the device hardware, the driver core routines and the application programmer's interface (API). Also the development of firmware components using such drivers is difficult because the driver specification may be ambiguous or erroneous or it may be misinterpreted by the developer. In this paper, we propose an abstract FSM model (“AFSM”) to support systematic top-down development of low-level device drivers. The model serves as a formal specification that can be soundly refined into an implementation. The AFSM can also be generated semi-automatically in a bottom-up approach from the binary (machine code) of the driver. This allows for generating a formal documentation of a driver software that may be available as third-party IP for which no source code is available. The generated AFSM can serve as a technical reference during integration of such “black-box” driver IP and when developing firmware components that call the functions of the API. We present three case studies with industrial HW device and SW driver IPs demonstrating the potential of the proposed approach.

English

English

Distributed PID-Based Scheduling for 6TiSCH Networks

Industrial low-power networks are becoming the nexus of operational technologies and the Internet thanks to the standardization of networking layer interfaces. One of the main promoters of this shift is the IETF 6TiSCH WG, which addresses network management and IP integration of time synchronized channel hopping (TSCH) networks as those developed by the IEEE802.15.4 TG. The 6TiSCH WG is defining the operational interface and mechanism by which the network schedule can be distributed amongst the devices in the network. This operational sublayer, called 6top, supports distributed scheduling and enables implementers to define the scheduling policy, only standardizing the distribution mechanism. This letter proposes a novel distributed scheduling policy based on the well-known industrial control paradigm referred as proportional, integral, and derivative (PID) control. The proposed technique is completely decentralized, enabling each node to determine the number of cells to schedule to one another, according to its traffic demand. The mechanism is reactive to sudden or bursty traffic patterns, while staying conservative in over-provisioning cells.

Low Latency Synchronization Scheme Using Prediction and Avoidance of Synchronization Failure in Heterochronous Clock Domains

For the performance-efficient integration of IPs on an SoC utilizing heterochronous multi-clock domains, we propose a synchronization scheme that causes low latency overhead when data are crossing clock boundaries. The proposed synchronization scheme is composed of a clock predictor and a synchronizer. The clock predictor of a sender clock domain produces a predicted clock that is used in a receiver clock domain to detect possible synchronization failures in advance. When the possible synchronization failures are detected, a synchronizer at the receiver delays data-capture times to avoid the possible synchronization failures. From the simulation of the proposed scheme through SPICE modeling using a Chartered 0.18 mm CMOS process, we verified the functionalities and timing behavior of the clock predictor and the synchronizer. The simulation results show that the clock predictor produces a predicted clock before a synchronization failure, and the synchronizer samples data correctly using the predicted clock.

Source and IR-level optimisations in the HercuLeS high-level synthesis tool

HercuLeS is an extensible high-level synthesis environment for automatically mapping algorithms to hardware. It overcomes limitations of known work: insufficient representations, maintenance difficulties, necessity of code templates, lack of usage paradigms and vendor-dependence. Aspects that are highlighted include automatic IP integration and especially source- and intermediate-level optimising transformations. In this context, we present transformational patterns for loop and if-conversion optimisations. Further, we focus on constant multiplication and division by proposing a suitable scheme for their straightforward and decoupled utilisation in user applications. It is shown that loop optimisations provide benefits of up to 32% in cycle performance, while if-conversion delivers an average improvement of 6.5%. By applying arithmetic optimisations, a 3.3-5.9× speedup over sequential implementations is achieved. It is also shown that HercuLeS is highly competitive to state-of-the-art commercial tools.

Graphical Hardware Description as a High-Level Design Entry Method for FPGA-Based Data Acquisition Systems

Probably one of the most significant developments in the field of software-defined multifunction data acquisition systems and devices is the employment of FPGA (Field-Programmable GateArray) technology, resulting in a tremendous digital processing potential close to the I/O pin. FPGA technology is based on reconfigurable semiconductor devices which can be employed as processing targets in heterogeneous computing architectures for a variety of data acquisition applications. They can primarily be characterized by generic properties, such as deterministic execution, inherent parallelism, fast processing speed and high availability, stability and reliability. Therefore FPGAs areparticularly suitable for use in “intelligent” data acquisition applications that require either in-line digital signal co-processing or real-time system emulation in the field of advanced control, protocol aware communication, hardware-in-the-loop (HIL) as well as RF and wireless test. From the perspective of a domain expert however, primarily being focused on developing applications and algorithms, simple and intuitive design entry methods and tools are required that facilitate the FPGA configuration and design entry process. Traditional FPGA design entry methods and commercially available tools assume a comprehensive knowledge of hardware description languages (HDL),such as VHDL or Verilog®, and implement a process or function at register-level. In contrast, graphical hardware description languages for FPGAs, such as the integrated development environment NI LabVIEW® with FPGA module extension, abstract the design process by means of graphical objects, I/O nodes and interconnecting wires that represent the FPGA’s IP and implement processes, timing, I/O integration and data flow. This paper discusses the advantages of graphical system design for FPGAs over text-based alternatives, introduces interfaces for the integration of 3rd party IP, all backed up by a detailed illustration of a COTS FPGA-based multifunction DAQ target compared to a traditional DAQ architecture.

Research on Intercom System for Stage Dispatch Console Based on IP Network

Traditional theatre dispatch platform, which is designed by circuit switching technology, has its limitation and disadvantages. So this paper proposed an effective intercom system for stage dispatch console based on IP network. We analysed its functional requirements, hardware and software framework, and the key technologies during IP communication. Various network technologies can be synthetically used, so as to realize IP integration for the whole system. Our study is of great significance in providing stage manager with fast and centralized information, which can help improving the stage performance.

A Proposed Integration of Hierarchical Mobile IP based Networks in SCADA Systems

Recently, Supervisory Control and Data Acquisition systems have integrated and connected to the Internet to address the widening scope and to maximize the advantages in terms of control, data viewing and generation. With the aid of mobile IP technology, this paper discusses the integration of hierarchical mobile networks for SCADA systems.

Eliminating Timing Information Flows in a Mix-Trusted System-on-Chip

Editor's notes: Integration of untrusted third-party IPs into an SoC design is a major challenge in establishing trustworthiness of the entire SoC. This article presents an approach to ensure information flow isolation between trusted and untrusted IP cores.

Development of a SoC for Digital Television Set-Top Box: Architecture and System Integration Issues

This work presents the integration of several IPs to generate a system-on-chip (SoC) for digital television set-top box compliant to the SBTVD standard. Embedded consumer electronics for multimedia applications like video processing systems require large storage capacity and high bandwidth memory. Also, those systems are built from heterogeneous processing units, designed to perform specific tasks in order to maximize the overall system efficiency. A single off-chip memory is generally shared between the processing units to reduce power and save costs. The external memory access is one bottleneck when decoding high-definition video sequences in real time. In this work, a four-level memory hierarchy was designed to manage the decoded video in macroblock granularity with low latency. The use of the memory hierarchy in the system design is challenging because it impacts the system integration process and IP reuse in a collaborative design team. Practical strategies used to solve integration problems are discussed in this text. The SoC architecture was validated and is being progressively prototyped using a Xilinx Virtex-5 FPGA board.

A high-level methodology for automatically generating dynamic partially reconfigurable systems using IP-XACT and the UML MARTE profile

Dynamic Partial Reconfiguration (DPR) has been introduced in recent years as a method to increase the flexibility of FPGA designs. However, using DPR for building complex systems remains a daunting task. Recently, approaches based on Model-Driven Engineering (MDE) and UML MARTE standard have emerged which aim to simplify the design of complex SoCs, and in some cases, DPR systems. Nevertheless, many of these approaches lacked a standard intermediate representation to pass from high-levels of descriptions to executable models. However, with the recent standardization of the IP-XACT specification, there is an increasing interest to use it in MDE methodologies to ease system integration and to enable design flow automation. In this paper we propose an MARTE/MDE approach which exploits the capabilities of IP-XACT to model and automatically generate DPR SoC designs. We present the MARTE modeling concepts and how these models are mapped to IP-XACT objects; the emphasis is given to the generation of IP cores that can be used in the Xilinx EDK (Embedded Design Kit) environment, since we aim to develop a complete flow around their Dynamic Partial Reconfiguration design flow. Finally, we present a case study integrating the presented concepts, showing the benefits in design efforts compared with a purely VHDL approach and using solely EDK. Experimental results show a reduction of the design efforts required to obtain the netlist required for the DPR design flow from hours required in VHDL and Xilinx EDK, to less the one hour and minutes for IP integration.

Transgene Excision Has No Impact on In Vivo Integration of Human iPS Derived Neural Precursors

The derivation of induced human pluripotent stem cells (hiPS) has generated significant enthusiasm particularly for the prospects of cell-based therapy. But there are concerns about the suitability of iPS cells for in vivo applications due in part to the introduction of potentially oncogenic transcription factors via viral vectors. Recently developed lentiviral vectors allow the excision of viral reprogramming factors and the development of transgene-free iPS lines. However it is unclear if reprogramming strategy has an impact on the differentiation potential and the in vivo behavior of hiPS progeny. Here we subject viral factor-free, c-myc-free and conventionally reprogrammed four-factor human iPS lines to a further challenge, by analyzing their differentiation potential along the 3 neural lineages and over extended periods of time in vitro, as well as by interrogating their ability to respond to local environmental cues by grafting into the striatum. We demonstrate similar and efficient differentiation into neurons, astrocytes and oligodendrocytes among all hiPS and human ES line controls. Upon intracranial grafting in the normal rat (Sprague Dawley), precursors derived from all hiPS lines exhibited good survival and response to environmental cues by integrating into the subventricular zone, acquiring phenotypes typical of type A, B or C cells and migrating along the rostral migratory stream into the olfactory bulb. There was no teratoma or other tumor formation 12 weeks after grafting in any of the 26 animals used in the study. Thus neither factor excision nor persistence of c-myc impact the behavior of hiPS lines in vivo.

Synopsys’ DesignWare DDR PHY compiler eases integration of memory interface IP

Synopsys’ DesignWare DDR PHY compiler eases integration of memory interface IP

PERFORMANCE EVALUATION OF INTEGRATED MACRO AND MICRO MOBILITY PROTOCOLS FOR WIDE AREA WIRELESS NETWORKS

The success of next generation wireless networks will rely much on advanced mechanisms for seamless mobility support among emerging heterogeneous technologies. Currently, Mobile IP is the most promising solution for mobility management in the Internet. Several IP micro mobility approaches have been proposed to enhance the performance of Mobile IP which supports quality of service, minimum packet loss, limited handoff delay and scalability and power conservation but they are not scalable for macro mobility. A practical solution would therefore require integration of Mobile IP and Micro mobility protocols where Mobile IP handles macro mobility and micro mobility protocols handles micro mobility. In this paper an integrated mobility management protocol for IP based wireless networks is proposed and analyzed. Simulation results presented in this paper are based on ns 2.