Inverter-based Operational Transconductance Amplifier Research Articles

On the design of an ultra-low-power ultra-low-voltage inverter-based OTA

In this paper, an inverter-based Operational Transconductance Amplifier (OTA) is introduced. This design is tailored for applications demanding ultra-low power consumption and exceptionally reduced supply voltage. In addition to the utilization of composite transistors and forward-body-biasing, a feedforward path is also employed to enhance the voltage gain. The OTA is simulated in a 65 nm CMOS technology with a supply voltage of 0.3 V. Simulation results show a voltage gain of 42.57 dB and a power consumption of 1.06 nW.

Hybrid Inverter-Based Fully Differential Operational Transconductance Amplifiers

Inverter-based Operational Transconductance Amplifiers (OTAs) are versatile and friendly scalable analog circuit blocks. Especially for the new CMOS technological nodes, several recent applications have been extensively using them, ranging from Analog Front End (AFE) to analog-to-digital converters (ADC). This work tracks down the current advances in inverter-based OTAs design, comparing their basic fully differential structures, such as Nauta (N), Barthelemy (B), Vieru (V) and Mafredini (M) ones, and, in addition, mixing them up to propose new fully differential single-ended and two-stage hybrid versions. The new herein-proposed fully differential hybrid OTAs are the composition of Barthelemy/Nauta (B/N), Barthelemy/Manfredini (B/M), Nauta/Vieru (N/V), and Manfredini/Vieru (M/V) OTAs. All OTAs were designed using the same Global Foundries 180 nm open-source PDK and their performances are compared for post-layout simulations.

A 1–3 GHz CMOS mixer-first receiver frontend with dual-feedback OTA achieving 306 MHz IF bandwidth, 2.1 dB NF, and 33 dB gain

In this paper, a mixer-first receiver frontend with dual-feedback baseband is proposed. The negative resistive and positive capacitive feedback paths are both applied to single-stage inverter-based operational transconductance amplifier (OTA) with fewer poles, to cover a wide BB frequency range. The [Formula: see text]-path filtering at the RF side and second-order filtering at the BB side inhibit out-of-band blocker interferences. The receiver frontend is designed in 65 nm CMOS. Simulation results display an NF of 2.1 dB across 306 MHz IF bandwidth, and a maximum gain of 33 dB from 1 to 3 GHz LO frequency range. The in-band and out-of-band IIP3 are -13 and 16 dBm, respectively. The receiver core draws 40 mW at 1 GHz LO frequency.

A 0.6-V 11-uW PVT tolerant DTMOS inverter based OTA

This paper presents the design of a process-voltage-temperature (PVT) variation tolerant inverter-based operational transconductance amplifier (OTA) employing both a dynamic threshold MOS (DTMOS) technique and a constant voltage biasing (CVB) scheme. The proposed inverter-based OTA offers a higher bandwidth due to implemented DTMOS technique, which realizes higher input transconductance value than a conventional inverter-based OTA design. Simulation results show that the proposed OTA achieves superior slow-slow (SS) corner performance under PVT variations than the conventional inverter-based OTA while consuming only 11-uW and providing a figure of merit (FoM) of 7.0-MHz.pF/uA. As a result, DC gain and unity-gain bandwidth (UGBW) of the proposed OTA improve by 27% and 32% at SS corner under the PVT variations, respectively.

Self-Biased and Supply-Voltage Scalable Inverter-Based Operational Transconductance Amplifier with Improved Composite Transistors

This paper deals with a single-stage single-ended inverter-based Operational Transconductance Amplifiers (OTA) with improved composite transistors for ultra-low-voltage supplies, while maintaining a small-area, high power-efficiency and low output signal distortion. The improved composite transistor is a combination of the conventional composite transistor and forward-body-biasing to further increase voltage gain. The impact of the proposed technique on performance is demonstrated through post-layout simulations referring to the TSMC 180 nm technology process. The proposed OTA achieves 54 dB differential voltage gain, 210 Hz gain–bandwidth product for a 10 pF capacitive load, with a power consumption of 273 pW with a 0.3 V power supply, and occupies an area of 1026 μm2. For a 0.6 V voltage supply, the proposed OTA improves its voltage gain to 73 dB, and achieves a 15 kHz gain–bandwidth product with a power consumption of 41 nW.

Ultra-Low-Voltage Inverter-Based Operational Transconductance Amplifiers with Voltage Gain Enhancement by Improved Composite Transistors

This paper proposes topological enhancements to increase voltage gain of ultra-low-voltage (ULV) inverter-based OTAs. The two proposed improvements rely on adoption of composite transistors and forward-body-biasing. The impact of the proposed techniques on performance figures is demonstrated through simulations of two OTAs. The first OTA achieves a 39 dB voltage gain, with a power consumption of 600 pW and an active area of 447 μm2. The latter allies the forward-body-bias approach with the benefit of the independently biased composite transistors. By combining both solutions, voltage gain is raised to 51 dB, consuming less power (500 pW) at the cost of an increased area of 727 μm2. The validation has been performed through post-layout simulations with the Cadence Analog Design Environment and the TSMC 180 nm design kit, with the supply voltage ranging from 0.3 V to 0.6 V.

A 13.9-nA ECG Amplifier Achieving 0.86/0.99 NEF/PEF Using AC-Coupled OTA-Stacking

An ultra-low power electrocardiogram (ECG) recording front-end intended for implantable sensors is presented. The noise-limited, high power first stage of a two-stage amplifier utilizes stacking of operational transconductance amplifiers (OTAs) for noise and power efficiency improvements. The proposed technique involves upmodulated/chopped signals being applied to ac-coupled, stacked inverter-based OTAs that inherently sum the individual transconductances while reusing the same current, thereby enhancing the noise efficiency. Two prototype designs were fabricated in a 180-nm CMOS process. The three-stack version consumes 13.2 nW and occupies 0.18 mm2, whereas the five-stack implementation consumes 18.7 nW and occupies 0.24 mm2. State-of-the-art NEF and PEF metrics of less than unity, 0.86 and 0.99, respectively, are reported for the five-stack version. These correspond to ~3 $\times $ improvement in terms of energy efficiency compared to prior ultra-low power, sub-100-nW amplifiers.

A new family of CMOS inverter-based OTAs for biomedical and healthcare applications

This paper presents a new family of innovative operational transconductance amplifier (OTA) topologies based on CMOS inverter structures, with improved gain and energy-efficiency. This new family of OTA designs is suitable for biomedical and healthcare circuits and systems, due to the high energy-efficiency, improved gain and low level of noise contribution, when compared to the state-of-the-art in this field. In this paper, two fully-differential implementations are presented, a first one with a double CMOS branch biased by two pairs of voltage-combiners structures in both NMOS and PMOS configurations, and a second one with folded voltage-combiners specifically targeting low voltage applications, e.g., supplies below 1 V. The usage of voltage-combiners to bias the OTAs improves the gain and the gain-bandwidth product, therefore improving the energy-efficiency figure-of-merit. High values of figure-of-merit are achieved in both implementations, i.e., more than 1600 MHz × pF/mA and 2000 MHz × pF/mA, gain values above 53 dB and 50 dB under supply sources of 2 V and 0.7 V respectively. The folded voltage-combiners biased OTA is able to operate correctly under a voltage supply down to 0.7 V with proper DC biasing. The results are finally compared with state-of-the-art in this field and the potential of the circuits is fulfilled using a state-of-the-art layout-aware integrated-circuit optimization framework, AIDA, particularly relevant in order to overcome the device stacking problematic for lower voltages.

A 0.25-V fifth-order Butterworth low-pass filter based on fully differential difference transconductance amplifier architecture

This paper presents a fifth-order Butterworth low-pass filter based on the fully differential difference transconductance amplifier (FDDTA) building blocks. At first, the FDDTA has been stated and its operation has been evaluated. Then, a practical implementation using two fully differential inverter-based operational transconductance amplifiers (OTA) was investigated. This particular FDDTA implementation relies on two main features: the intrinsically matched transistors that assure similar transconductances and output conductances for both inverter-based OTA instances; and the inverter-based approach without internal nodes that reduces circuit complexity and power consumption since it requires no supplementary external calibration circuit such as tail current or bias voltage sources. Finally, the filter architecture, which consists of one inverter-based OTA input stage and five FDDTAs in a cascade connection has been evaluated, showing that it presents the expected fifth-order transfer function according to the Butterworth theory. The prototypes, implemented in a 130 nm CMOS process, operate in weak inversion supplied with 0.25 V and consumes 603 nW. Furthermore, they feature a DR of 57 dB in a 100 Hz bandwidth and a maximum THD of 54 dB, therefore, accomplishing specifications that suit for low-frequency applications.

A 0.4-V 10.9-$\mu$ W/Pole Third-Order Complex BPF for Low Energy RF Receivers

This paper presents a 0.4-V ultra-low power (ULP) third-order active-RC complex band-pass filter (CxBPF) for Bluetooth low energy receivers prototyped in a 180 nm CMOS process. The ULP is reached by using single-stage inverter-based operational transconductance amplifiers (OTA) instead of two or more stages OTA. The effects of the low voltage gain and resistive loading are reduced by using a process and temperature robust negative transconductor connected to the virtual ground. The ultra-low voltage operation is reached by using only two stacked transistors and PMOS bulk forward bias. The CxBPF operates well down to 0.4V power supply and the experimental results present power dissipation of only $10.9~\mu \text{W}$ /pole, 1 MHz bandwidth centered at 2 MHz, image rejection rate of 34 dB, and 12.7 fJ FoM.

A Precision, Energy-Efficient, Oversampling, Noise-Shaping Differential SAR Capacitance-to-Digital Converter

This paper introduces an oversampling, noise-shaping differential successive-approximation-register capacitance-to-digital converter (CDC) architecture for interfacing capacitive sensors. The proposed energy-efficient CDC achieves high-precision capacitive resolution by employing oversampling and noise shaping. The switched-capacitor (SC) integrator is inserted between the comparator and the charge-redistribution digital-to-analog converter to implement noise shaping and to make the interface circuit insensitive to parasitic capacitances. An inverter-based operational transconductance amplifier with a common-mode feedback circuit is employed to implement the SC integrator with subthreshold biasing for low voltage and low power. The ring-oscillator-based comparator is implemented to achieve high energy efficiency. The test chip is fabricated in a 0.18- $\mu \text{m}$ CMOS technology. The proposed CDC experimentally achieves 150 aF absolute resolution and 12.74-ENOB with an oversampling ratio of 15 and a sampling clock of 18.51 kHz. The fabricated prototype dissipates 1.2 and 0.39 $\mu \text{W}$ from analog and digital supplies, respectively, with an energy efficiency figure-of-merit of 187 fJ/conversion step.

A 0.25-V calibration-less inverter-based OTA for low-frequency Gm-C applications

This paper presents a calibration-less inverter-based operational transconductance amplifier (OTA) built with intrinsically matched CMOS inverters, therefore, dispensing any kind of calibration circuit. In addition, the circuit is implemented in IBM 130-nm CMOS processes using non-uniformly doped MOS transistors and is specially designed to suit low-frequency Gm-C applications such as biomedical applications. The intrinsically matched CMOS inverters design relies on the utilization of the distributed layout of halo-implanted MOS transistors operating in weak inversion. In this work we demonstrate that this technique stabilizes the switching point voltage of the CMOS inverter, reducing its statistical variation, besides allowing gain enhancement and its adjustment, which is desirable for the Gm-C design. Based on the original topology proposed by Bram Nauta (and its derivative works), focusing on the tunability of VHF filters, we adapt this topology for constant Gm applications. Moreover, the proposed circuit features a 2.46-μS transconductance when supplied with 0.25-V, dissipates 55-nW during operation making it suitable to low-power applications.

PVT compensated inverter‐based OTA for low‐voltage CT sigma‐delta modulators

An inverter-based operational transconductance amplifier (OTA) robust to process, voltage and temperature (PVT) variations is proposed in this Letter to enable the design of low-voltage power-efficient continuous-time sigma-delta modulators (CT-SDMs). The proposed OTA significantly reduces the unity gain-bandwidth variation across PVT corners while presenting a DC gain of 41.9 dB at nominal conditions when operated at 0.6 V. The effectiveness of the proposed circuit was verified in a 180 nm CMOS process by transistor-level simulations including PVT variations and mismatch. Also, a 0.6 V third-order CT-SDM is designed to verify the robustness against voltage and temperature variations.

A 0.9-V 100-<inline-formula> <tex-math notation="LaTeX">$\mu$ </tex-math> </inline-formula>W Feedforward Adder-Less Inverter-Based MASH <inline-formula> <tex-math notation="LaTeX">$\Delta\Sigma$ </tex-math> </inline-formula> Modulator With 91-dB Dynamic Range and 20-kHz Bandwidth

A 0.9-V $\Delta \Sigma $ modulator integrated into a 0.18- $\mu \text{m}$ CMOS technology for digitizing signals in low-power devices is presented in this paper. To do so, a cascade (multistage noise shaping) architecture based on an adder-less feedforward structure is proposed. The proposed modulator has a unity signal transfer function in both stages of the modulator in order to reduce the integrator’s output swings. To mitigate the failure of slow process corner in the weak inversion as well as to further diminish the power consumption of the presented modulator, a fully differential self- and bulk-biased inverter-based operational transconductance amplifier is proposed. Experimental results are shown to demonstrate the efficiency of the proposed $\Delta \Sigma $ converter, showing state-of-the-art performance, by featuring 88.7-dB signal-to-noise ratio, 86.4-dB signal-to-noise plus distortion ratio, and 91-dB dynamic range within a signal bandwidth of 20 kHz, with a power dissipation of $103.4~\mu \text{W}$ when the circuit is clocked at 5.12 MHz.

Inverter‐based low‐power delta–sigma modulator using correlated level shifting technique

A low-power delta–sigma modulator based on inverter operational-transconductance amplifiers (OTAs) using correlated level shifting technique (CLS) is presented. The CLS technique boosts the DC gain of inverter-based OTA from 42 to 79 dB and extends the linear output swing from 55 to 80% of the full scale. Simulation results show that design in 180 nm CMOS technology, the proposed second-order delta–sigma modulator achieves a signal-to-quantisation-noise ratio improvement of 10.4 dB compared to a conventional inverter-based modulator implementing the identical loop filter with the same oversampling ratio.

A Dynamic Zoom ADC With 109-dB DR for Audio Applications

This paper presents the first dynamic zoom ADC. Intended for audio applications, it achieves 109-dB DR, 106-dB signal-to-noise ratio, and 103-dB SNDR in a 20-kHz bandwidth, while dissipating only 1.12 mW. This translates into the state-of-the-art energy efficiency as expressed by a Schreier FoM of 181.5 dB. It also achieves the state-of-the-art area efficiency, occupying only 0.16 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> in the 0.16-μm CMOS. These advances are enabled by the use of concurrent fine and coarse conversions, dynamic error-correction techniques, and a dynamically biased inverter-based operational transconductance amplifier.

A THD-reduction high-efficiency audio amplifier using inverter-based OTAs with filter-output feedback

This paper presents an integrated low-voltage THD-reduction high-efficiency class-D audio amplifier using inverter-based operational transconductance amplifiers (OTAs). We propose a negative feedback loop which can compensate for external perturbations and improving output precision. The compensator increases the audio-frequency loop gain, and leads to a better rejection of audio-frequency disturbances. The use of inverter-based OTA and comparator provides low-voltage operation and low-power dissipation. The audio amplifier operates with a 1.5V supply voltage with maximum power efficiency of 90%. The proposed class-D amplifier was implemented using a TSMC 0.18-μm 1P6M CMOS process, and the active chip area is 1.87mm2.