Inversion Circuit Research Articles

Comparison of Magnetostrictive-Actuated Semi-Active Control Methods Based on Synchronized Switching

Three distinct synchronized switching circuits based on a magnetostrictive actuator are compared in this paper to examine their control mechanisms and circuit characteristics. These circuits include a semi-active shunt circuit, a semi-active current inversion and amplification circuit, and a semi-active automatic current inversion and amplification circuit. Each circuit type employs an additional electronic switch. The synchronized switching method enables the rational control of the circuit current generated by the magnetostrictive actuator to fulfill any desired control strategy. Simulation and experimental results on a 10-bay truss structure reveal that the three circuits can effectively adjust the polarity of the induced current as needed. The three circuits are then compared to thoroughly analyze their unique characteristics and explain their respective advantages and dis-advantages. Using the comparison results, various options available for control circuit design are demonstrated.

A Case for Synthesis of Recursive Quantum Unitary Programs

Quantum programs are notoriously difficult to code and verify due to unintuitive quantum knowledge associated with quantum programming. Automated tools relieving the tedium and errors associated with low-level quantum details would hence be highly desirable. In this paper, we initiate the study of program synthesis for quantum unitary programs that recursively define a family of unitary circuits for different input sizes, which are widely used in existing quantum programming languages. Specifically, we present QSynth, the first quantum program synthesis framework, including a new inductive quantum programming language, its specification, a sound logic for reasoning, and an encoding of the reasoning procedure into SMT instances. By leveraging existing SMT solvers, QSynth successfully synthesizes ten quantum unitary programs including quantum adder circuits, quantum eigenvalue inversion circuits and Quantum Fourier Transformation, which can be readily transpiled to executable programs on major quantum platforms, e.g., Q#, IBM Qiskit, and AWS Braket.

A Synchronous Current Inversion and Energy Extraction Circuit for Electromagnetic Energy Harvesting Enhancement

A Synchronous Current Inversion and Energy Extraction Circuit for Electromagnetic Energy Harvesting Enhancement

A 0.25-μm HV-CMOS Synchronous Inversion and Charge Extraction Interface Circuit With a Single Inductor for Piezoelectric Energy Harvesting

A 0.25-μm HV-CMOS Synchronous Inversion and Charge Extraction Interface Circuit With a Single Inductor for Piezoelectric Energy Harvesting

21 Level Asymmetric Inverter without Inversion Circuit with Reduced Switch Count for BLDC Motor Drive

21 Level Asymmetric Inverter without Inversion Circuit with Reduced Switch Count for BLDC Motor Drive

Extremely-Fast, Energy-Efficient Massive MIMO Precoding With Analog RRAM Matrix Computing

Signal processing in wireless communications, such as precoding, detection, and channel estimation, are basically about solving inverse matrix problems, which, however, are slow and inefficient in conventional digital computers, thus requiring a radical paradigm shift to achieve fast, real-time solutions. Here, for the first time, we apply the emerging analog matrix computing (AMC) to the linear precoding of massive MIMO. The real-valued AMC concept is extended to process complex-valued signals. In order to adapt the MIMO channel models to RRAM conductance mapping, a new matrix inversion circuit is developed. In addition, fully analog dataflow and optimized operational amplifiers are designed to support AMC precoding implementation. Simulation results show that the zero-forcing precoding is solved within 20 ns for a 16×128 MIMO system, which is two orders of magnitude faster than the conventional digital approach. Meanwhile, the energy efficiency is improved by 50×.

Depth Optimization of FLT-Based Quantum Inversion Circuit

Depth Optimization of FLT-Based Quantum Inversion Circuit

Lightweight 8‐bit S‐box and combined S‐box/S‐box−1 for cryptographic applications

SummaryIn this paper, a lightweight 8‐bit S‐box and combined S‐box/S‐box−1 with a security level equal to the AES S‐box is presented. From the viewpoint of hardware implementation, the S‐box has better hardware and timing complexities. The structure is based on an efficient field inversion and a low‐cost affine transformation. The field multiplications over in the inversion circuit are implemented by resource sharing to reduces logic gates. The original equations of the inversion over are optimally rewritten. In addition, a part of the S‐box called Part1 is optimized for reducing area and delay. This part consists of two addition operations, one multiplication, field squaring, and multiplication by constant λ, which all operations are over . The subblocks of Part1 are combined to generate a unified structure. Security analysis of the proposed S‐box showed that the structure has a security level equal to the Advanced Encryption Standard (AES) S‐box. The implementation results in 180‐ and 65‐nm Complementary metal oxide semiconductor (CMOS) technologies show the proposed S‐box and combined S‐box/S‐box−1 are comparable in terms of area, delay, and area × delay than most of the famous S‐boxes. The proposed S‐box is a high‐secure and area‐efficient S‐box as a good candidate for block ciphers.

Piezoelectric energy enhancement strategy for active fuzzy harvester with time-varying and intermittent switching

This study aims to increase the amount of electrical energy harvested from a piezoelectric vibration energy harvester under unloaded and high-load resistance conditions. Although increased piezoelectric charge due to the synchronized switch harvesting on inductor (SSHI) strategy damps mechanical vibrations, the mechanical vibration amplitude of a mechanical element in a harvester is assumed to be constant for most discussions regarding the active harvester with SSHI strategy. However, this assumption is not valid under excessive switching actions, in which case the performance of the harvester deteriorates. This problem is known as the vibration suppression effect. To address this problem, in this study, two switching strategies for the charge inversion circuit—namely, switching considering vibration suppression-threshold (SCVS-t) and adaptive SCVS-t (ASCVS-t)—are proposed through intermittent switching actions. During the harvesting process, intermittent switching using these strategies is performed based on the output voltage threshold, thus maintaining high mechanical vibration amplitude and excellent harvesting performance by avoiding excess switching. The ASCVS-t adopts a tuning algorithm for the time-varying threshold and can achieve appropriate intermittent switching and effective harvesting under various vibration conditions without pre-tuning. Experimental comparisons with conventional strategies confirm that the proposed strategies achieve 2.9 times and 2.0 times greater harvested energy storages than a standard harvester and conventional switching strategy, respectively.

High Throughput/Gate AES Hardware Architectures Based on Datapath Compression

This article proposes highly efficient Advanced Encryption Standard (AES) hardware architectures that support encryption and both encryption and decryption. New operation-reordering and register-retiming techniques presented in this article allow us to unify the inversion circuits in SubBytes and InvSubBytes without any delay overhead. In addition, a new optimization technique for minimizing linear mappings, named multiplicative-offset, further enhances the hardware efficiency. We also present a shared key scheduling datapath that can work on-the-fly in the proposed architecture. To the best of our knowledge, the proposed architecture has the shortest critical path delay and is the most efficient in terms of throughput per area among conventional AES encryption/decryption and encryption architectures with tower-field S-boxes. The proposed round-based architecture can perform AES encryption where block-wise parallelism is unavailable (e.g., cipher block chaining (CBC) mode); thus, our techniques can be globally applied to any type of architecture including pipelined ones. We evaluated the performance of the proposed and some conventional datapaths by logic synthesis with the NanGate 45-nm open-cell library. As a result, we can confirm that our proposed architectures achieve approximately 51-64 percent higher efficiency (i.e., higher bps/GE) and lower power/energy consumption than the other conventional counterparts.

The Research controller system of Brushless DC Motor Based on DSP

Brushless DC motor (BLDCM) is a new type of motor which integrates power semiconductor and permanent magnet materials. In this paper, a sensorless brushless DC motor control system based on DSP and CPLD is proposed. The working principles of the control circuit, power inversion circuit and rotor position identification circuit with the core of TMS320F2812 and MAX7000 (EPM7032) are analyzed in detail.The test results show that the system has the characteristics of strong anti-interference, good robustness, fast starting and high efficiency.

Highly efficient $$\textit{GF}(2^8)$$ GF ( 2 8 ) inversion circuit based on hybrid GF representations

This paper proposes a compact and highly efficient $$\textit{GF}(2^8)$$ inversion circuit design based on a combination of non-redundant and redundant Galois field (GF) (or finite field) arithmetic. The proposed design utilizes an optimal normal basis and redundant GF representations, called polynomial ring representation and redundantly represented basis, to implement $$\textit{GF}(2^8)$$ inversion using a tower field $$\textit{GF}((2^4)^2)$$ . The flexibility of the redundant representations provides efficient mappings from/to the $$\textit{GF}(2^8)$$ . This paper evaluates the efficacy of the proposed circuit by gate counts and logic synthesis with a 65-nm CMOS standard cell library in comparison with conventional circuits. Consequently, we show that the proposed circuit achieves approximately 25% higher area–time efficiency than the conventional best inversion circuit in our environment. We also demonstrate that AES S-Box with the proposed circuit achieves the best area–time efficiency.

Further Improving Efficiency of Higher Order Masking Schemes by Decreasing Randomness Complexity

Most cryptographic implementations are vulnerable to side-channel attacks. Among the countermeasures, masking is the most popular one. In the field of provable secure masking schemes, it is a tough task to design a masking scheme for the multiplication with related multiplicands. Among all the corresponding solutions, the one proposed by Coron et al. in FSE 2013 achieves the best efficiency. Furthermore, in CRYPTO 2015, we claim that this scheme can be extended to secure any quadratic functions and therefore enables secure evaluation of S-box, which significantly outperforms any other methods. In this paper, we further promote the efficiency of Coron’s scheme by decreasing the random generations according to two observations. First, by modifying each pair of intermediate values on two sides of a diagonal line, half of all the required random values can be removed. Second, some randomness can be reused. All random values in one out of two lines can be replaced with the same random value. According to these two observations, we propose two new schemes. The first proposal improves the original scheme with a 50% randomness reduction and satisfies a stronger compositional security notion ${d}$ -SNI, while the second proposal improves the original scheme with a 50%–75% randomness reduction and satisfies a weaker compositional security notion ${d}$ -TNI. We give the security proof for both schemes. Moreover, we give an example of the masked Advanced Encryption Standard (AES) inversion circuits where both the first and second proposals are applied, significantly outperforming the original AES inversion with a 43%–57% saving of random generations. This indicates that our proposals can be used to build secure and efficient implementations of cryptographic algorithms.

High-Quality Sine Wave Generation Using a Differential Boost Inverter at Higher Operating Frequency

Buck-converter-based topologies are used to generate high-frequency sinusoidal outputs. Buck-based inversion circuits such as voltage source inverters or class-D amplifiers have inherent control-to-output linearity in large-signal sense. However, in these topologies, the instantaneous output is always smaller than the dc-input during linear modulation. A differential boost inverter (DBI) is a boost-based topology that is used to generate a sinusoidal output. In DBI, the instantaneous output can be higher or lower than the dc-input voltage. DBI exhibits nonlinear control-to-output behavior in large-signal dynamic sense. Therefore, generating a high-frequency sinusoidal output using this topology is a challenge. The issues associated with a DBI for high-frequency sine wave generation are characterized in this paper. Conventional linear and nonlinear control techniques fail to produce a high-quality sine wave output at higher operating frequency. A nonlinear feedback linearization technique is proposed, which forces the output to be linear with respect to the reference even at higher operating frequency. This leads to a high-frequency high-quality sine wave generation using a DBI. The proposed modulator is verified using a laboratory prototype to generate a sine wave up to 2 kHz. A triangular wave of 100-Hz frequency is also generated by the proposed technique. Superior dynamic responses of a dynamic linearizing modulator controlled DBI for a step change in frequency, load current, input voltage, and reference are also experimentally verified.

Toward Formal Design of Practical Cryptographic Hardware Based on Galois Field Arithmetic

This paper presents a formal method for designing cryptographic processor datapaths on the basis of arithmetic circuits over Galois fields (GFs). The proposed method describes GF arithmetic circuits in the form of hierarchical graph structures, where nodes represent sub-circuits whose functions are defined by arithmetic formulae over GFs, and edges represent data dependency between nodes. In this paper, we first introduce the application of graph representation to arithmetic circuits over extension fields of ${\mbi {GF}}({{\mbi {p}}^{\mbi {m}}})$ $({\mbi {p}} \geq {\bf 2})$ and composite fields, which are commonly used in the design of cryptographic processors. The newly proposed graph representation can be formally verified through symbolic computation techniques based on polynomial reduction and Grobner basis. We then demonstrate the capabilities of the proposed approach through an experimental design of a 128-bit AES (Advanced Encryption Standard) datapath including multiplicative inversion circuits over the composite field ${\mbi {GF}}{(((2^2)^2)^2})$ . The results show that the proposed method can describe such practical datapaths, as well as that complete verification of such a datapath can be carried out within a short period of time.

Three-Phase Static Var Generator Based on Z-Source Network

The utility model provides a three-phase static var generator based on a Z source network. The three-phase static var generator comprises the Z source network, a main inversion circuit and a detection control module, wherein output ends of the Z source network are connected to a direct current side of the main inversion circuit; output ends of the main inversion circuit are connected to a three-phase power grid in parallel; and the detection control module is used for detecting voltages and currents of the three-phase power grid, the output ends of the main inversion circuit, and the Z source network, controlling the on-off state of a switch device of the main inversion circuit through driving signals, and further realizing the dynamic reactive compensation of the three-phase power grid. Unique X-type combination of small inductors and capacitors of the Z source network is used to replace the topological structure on the direct current side of an existing SVG, the defect that the SVG device is liable to be influenced by the insufficient voltage on the direct current side is overcome, a dead-zone circuit is effectively eliminated, and the output noises caused by the dead time are avoided, so that the SVG provided by the utility model is lower in cost, the reactive power compensation range is wider, the compensation effect is better, and the working reliability of the SVG is substantially improved.

피에조 액츄에이터 구동용 에너지 회수형 인버터의 특성과 구동 기법 연구

Piezo devices have large power density and simple structure compared with conventional electrical motors. Thus they can generate larger forces than the conventional actuators with small size. Their resopnses to commands are also very fast and thus the bandwidths are very wide. Thus the piezo devices are expected to be used widely in the future for actuating devices requiring fast response and large actuating force with small size. However, the piezo actuators need high voltage with high driving current due to their large capacitive property. In this paper, proposed is a simple method to drive piezo devices using voltage inversion circuit with coli inductance. The coil inductance carries the charges in the piezo device to the opposite side, inverting the polarity of the applied voltage, thus saving the power to drive the device with AC voltages. Experiments with real circuit demonstrates that the proposed scheme can improve the energy efficiency very much.

전압 극성 전환을 통한 피에조 소자의 에너지 회수형 구동 기법 연구

Piezo devices have large power density and simple structure. They can generate larger force than the conventional actuators. It has also wide bandwidth with fast response in a compact size. Thus the piezo devices are expected to be used widely in the future for small actuators with fast response time and large actuating force. However, the piezo actuators need high voltage with high driving current due to their large capacitive property. In this paper, we propose a simple method to drive piezo devices using voltage inversion circuit with coil inductance. Experiments with real circuit demonstrates that the proposed scheme can improve the energy efficiency very much.

SYSTEM AND METHOD FOR HARVESTING ENERGY FROM ENVIRONMENTAL VIBRATIONS

Embodiments of the present invention provide a system and a method for increasing the harvested energy from a piezoelectric element exposed to environmental vibrations via a two-prong system. In a first prong, a cantilever beam is tapered and shaped so as to increase and provide an approximately uniform strain on and along the beam, thus resulting in increased voltage. In a second prong of the system and method, a voltage compensating circuit, when used with a voltage inversion circuit of the prior art, increases the harvested power by injecting current to the piezoelectric element after each voltage inversion so as to increase the voltage level.

Intensity of electric field radiating from high-power pulsed electromagnetic wave generator for use in biological applications

Cancer treatment is one of several new applications which use nanosecond and subnanosecond high-voltage pulses. This study focuses on the design of a compact highpower pulsed electromagnetic wave generator using a nanosecond pulsed power generator to apply a high-intensity electric field for the treatment of cancer; the pulses cause apoptosis in cancer cells. We applied an L-C inversion circuit to the pulsed power generator to obtain a voltage waveform with a single frequency, which is applied to an antenna. A water gap switch and water capacitors were used in the L-C inversion circuit to obtain a pulsed voltage with a frequency element of 250 MHz. In this experiment, an electromagnetic wave was radiated underwater by a loop antenna. A measuring double loop antenna placed 0.15 m and 0.3 m from the radiating antenna detected electric field intensities of 112 kV/m and 49 kV/m, respectively. A focusing bowl was attached to the radiating antenna to obtain a higher electric field. The electric field intensity of the radiating antenna with the focusing bowl, 300 kV/m, was 6 times higher than that without the focusing bowl. The intensity distribution of the electric field focused by the focusing bowl was measured. A measuring small loop antenna detected peak electric field intensity of 11.3 kV/cm at a focal point. Areas with electric field intensity greater than 10.8 kV/cm were approximately 5 mm square and 3 mm wide in the x-z plane and y-axis, respectively.