Inverse Fast Fourier Transform Processor Research Articles

Energy Efficient Floating Point Fft/Ifft Processor For Mimo-Ofdm Applications

There are several methods to accomplish Fast Fourier Transform and Inverse Fast Fourier Transform processor for multiple inputs multiple output-orthogonal frequency division multiplexing applications. It requires high performance and low power implementation methodologies for reducing the hardware complexity and cost. In conventional fixed point arithmetic calculation is complex to utilize because the dynamic range of computations must be limited in order to overcome overflow and under flow problems. This paper presents floating point arithmetic optimization technique to implement radix-2 butterfly structures for the reduction of complex multipliers presented. Implementations of 32 bit floating point multiplier and floating point adder are presented by using single precision and compare the synthesis results with conventional system. In order to reduce the error we used floating point arithmetic for the butterfly structure. Energy efficient multiplier based on modified booth algorithm is used in radix-2 butterflies. By adopting this architecture the FFT/IFFT implementation using Xilinx FPGA Vertex-7 will improve the 25% logic utilization and the reduction in space utilization. Using arithmetic reduction the power delay product for radix 2 butterfly is reduced by 2.5% compared to normal implementation.

Noise Reduction Using Modified Wiener Filter in Digital Hearing Aid for Speech Signal Enhancement

Abstract Speech signals are usually affected by noises during the communication process. For suppressing the noise signal that is combined with the speech signal, a Wiener filter is adapted in digital hearing aids. Weiner filter plays an important role in noise suppression and enhancement by estimating the relation between the power spectra of the noise-affected speech signal and the noise signal. Power consumption and the hardware requirement are the important problems in adapting Weiner filter for major communication systems. In this work, we implemented an efficient Wiener filter and applied it for noise suppression along with a real-valued fast Fourier transform (FFT)/real-valued inverse FFT processor in digital hearing aids. The pipelined process was adopted for increasing the performance of the system. The proposed Wiener filter was designed to remove the iteration problems in the conventional Wiener filter. The division operation was replaced by an efficient inverse and multiplication operation in the proposed design. A modified architecture for matrix inversion with low computation complexity was implemented. The complete design computation was based on IEEE-754 standard single-precision floating-point numbers. The Wiener filter and the whole system architecture was implemented and designed on a Field Programmable Gate Array platform and simulated to validate the results in Xilinx ISE tools. An efficient reduction in power and area was obtained by adapting the proposed method for speech signal noise degradation. The performance of the proposed design was found to be 50.01% more efficient than that of existing designs.

Novel Shared Multiplier Scheduling Scheme for Area-Efficient FFT/IFFT Processors

This paper proposes a shared multiplier scheduling scheme (SMSS) for area-efficient fast Fourier transform (FFT)/inverse FFT processors. SMSS can significantly reduce the total number of complex multipliers up to 28%. The proposed mixed-radix multipath delay commutator processors can support 128/256 and 256/512-point FFTs using SMSS. The proposed processors have been designed and implemented with 90-nm CMOS technology, which can reduce the total hardware complexity by 20%. The proposed processors having eight-parallel data paths can achieve a high throughput rate up to 27.5 GS/s at 430 MHz. In addition, the proposed processors can support any FFT size using additional stages.

Static quantised radix-2 fast Fourier transform (FFT)/inverse FFT processor for constraints analysis

This research work focuses on the design of a high-resolution fast Fourier transform (FFT)/inverse FFT (IFFT) processors for constraints analysis purpose. Amongst the major setbacks associated with such high-resolution FFT processors are the high-power consumption resulting from the structural complexity and computational inefficiency of floating-point calculations. As such, a parallel pipelined architecture was proposed to statically scale the resolution of the processor to suite adequate trade-off constraints. The quantisation was applied to provide an approximation to address the finite word-length constraints of digital signal processing. An optimum operating mode was proposed, based on the signal-to-quantisation-noise ratio (SQNR) as well as the statistical theory of quantisation, to minimise the trade-off issues associated with selecting the most application-efficient floating-point processing capability in contrast to their resolution quality.

Low-Complexity PAPR Reduction Scheme Without Side Information for OFDM Systems

This paper proposes a novel peak to average power ratio (PAPR) reduction scheme that requires no side information in orthogonal frequency division multiplexing (OFDM) systems. Unlike the selective mapping (SLM) or the partial transmit sequence (PTS) scheme, the proposed scheme deals with post inverse fast Fourier transform (IFFT) symbols and thus requires only a single IFFT processor in the transmitter. Compared to other conventional schemes implemented with a single IFFT processor, such as the circularly shifted phase sequences (CSPS) or the optimised circularly shifted phase sequences (OCSPS) method, the proposed scheme achieves an even lower complexity since only phase rotation and cyclic shifting of OFDM symbols are performed. More importantly, the proposed scheme significantly outperforms the CSPS and the OCSPS methods in reducing PAPR as shown in simulation results. An added benefit of the proposed scheme is that it employs a linear receiver, such as a maximal likelihood (ML) detector, a minimum mean square error (MMSE) estimator, or a zero forcing (ZF) estimator, to demap quadrature amplitude modulation (QAM) symbols. Especially the ML detector demaps the QAM symbols with no side information. Simulation results also show that the bit error rate (BER) of the proposed scheme has no loss when the ML detector, the ZF or the MMSE estimator is used with hard-decision compared to that of the conventional OFDM system without any PAPR reduction scheme over Rayleigh fading channel.

A partially operated FFT/IFFT processor for low complexity OFDM modulation and demodulation of WiBro in-car entertainment system

Wireless broadband (WiBro) systems can provide high data rate wireless Internet access with personal subscriber station under the stationary or mobile environment. It is the orthogonal frequency division multiple access (OFDMA) in time division duplex (TDD) system with 768 useful subcarriers over a nominal bandwidth of 8.75 MHz at 2.3 GHz band and each frame is composed of 42 OFDM symbols, corresponding to 5 ms. For modulation and demodulation in the WiBro communication system, the fast Fourier transform (FFT) processing is the most speed and power consumption critical path. In this paper, we describe 4096 points FFT and inverse FFT processor for mobile in-car entertainment systems. To obtain low complexities, small computation power and distributed memory, partially operated over-sampling architecture is developed to meet the requirement of non-stopping and high-speed data throughput. From experiment results, we can show that our methods reduce the complexity about 37.8% and it is suitable to implementation in mobile devices for WiBro consumer application which is required small area and low-power such as multimedia data service.