Inverse Discrete Cosine Transform Algorithm Research Articles

Zero coefficient‐aware fast butterfly‐based inverse discrete cosine transform algorithm

The latest video coding standards, including Moving Picture Experts Group-4 (MPEG-4) advanced video coding (AVC)/H.264 and high-efficiency video coding (HEVC), use a discrete cosine transform (DCT) process as the core for compression efficiency, sacrificing the computational complexity at decoder. There have been a number of attempts to reduce the complexity of inverse DCT (IDCT). Butterfly-based factorisation remains the most commonly used method for such a reduction. In this study, the authors propose a zero (Z) coefficient-aware fast butterfly-based IDCT algorithm for video decoding. They focus on a reduction in the computational complexity of the butterfly-based 8 × 8 IDCT by removing the unnecessary computations of one-dimensional (1D) IDCT kernels, and adaptively applying IDCT kernels based on the number of non-Z DCT coefficients to speed-up 1D data. Their experimental results show that the average operation numbers using the proposed IDCT is approximately half that for the 8 × 8 IDCT implemented in the MPEG-4 AVC/H.264 and HEVC reference software. The improved computational complexity of the proposed method is demonstrated by measuring the running time, which requires only one-half of the IDCT time using the reference software.

Accelerating IDCT Algorithm on Xeon Phi Coprocessor

Inverse Discrete Cosine Transform (IDCT) is an important operation for image and videos decompression. How to accelerate the IDCT algorithm has been frequently studied. Recently Intel has proposed Xeon Phi coprocessors based on the many integrated core (MIC) architecture. Xeon Phi is integrated with 61 cores and 512-bit SIMD extension within each core, thus providing very high performance. In this paper, we employ the Knights Corner (a beta version of Xeon Phi) to accelerate the IDCT algorithm. By employing the 512-bit SIMD instruction and data pre-fetching optimization, our implementation achieves (1) averagely 5.82 speedup over the none-SIMD version, (2) averagely 27.3% performance benefit with the data pre-fetching optimization, and (3) averagely 1.53 speedup on one Knights Corner coprocessor over the implementation on one octal-core Intel Xeon E5-2670 CPU.

High throughput and energy efficient two‐dimensional inverse discrete cosine transform architecture

This study presents an energy efficient and high throughput two-dimensional inverse discrete cosine transform (IDCT) architecture, suitable for high speed and high quality image and video processing applications. The proposed architecture is based on the Arai–Agui–Nakajima IDCT algorithm. The high throughput rate is accomplished through the high degree of pipelining in the multipliers of the architecture. The distribution properties of the input signal, that is, the high percentage of zero coefficients, are exploited in order to lower power consumption. In particular, whenever an all zero column enters the architecture, the corresponding pipeline stages are adjacently deactivated in order to lower switching activity. Furthermore, a novel approach, regarding the transposition structure, is introduced. The all zero columns are not loaded in the transposition memory. Instead, they are encoded through a single bit in a parallel data path, thereby reducing the power consumption of the transposition process by 19%. The proposed architecture, implemented in a 65 nm field programmable gate array, provides a throughput rate of 2.722 Gpixel/s for a power consumption of 0.831 W. The experimental results and the comparison with previous work validate the efficiency and the suitability of the proposed implementation for high speed and high quality video decoding applications.

Zero coefficient-aware IDCT algorithm for fast video decoding

Ever since many well-known image and video coding standards such as JPEG, MPEG, and H.26x started using DCT as a core process in data compression, the design of the fast inverse discrete cosine transform (IDCT) has been an intensive research topic. Most research has focused on a reduction of the number of operations using the butterfly structure. However, the majority of DCT coefficients is zero after quantization and is therefore redundant for IDCT computation. Therefore, we exploited this DCT coefficients redundancy to propose a zero coefficient-aware IDCT algorithm for fast decoding. The proposed method significantly reduces the number of IDCT operations by adaptively including non-zero coefficients in the calculation and employing a table look-up to eliminate multiplication operations in the IDCT process. The proposed zero coefficient-ware algorithm outperformed other existing fast IDCT algorithms in terms of operational complexity. Moreover, the running time was faster than butterfly based IDCT algorithms implemented in MPEG-4 simple profile decoder by a speedup factor of 1.32 times for the SIF/CIF sequences and up to 2.18 times for the HD sequences.

Scaled zero coefficient-aware IDCT algorithm for fast video decoding

Proposed is a scaled zero coefficient-aware fast inverse discrete cosine transform (IDCT) algorithm that substantially outperforms the existing fixed-point 8×8 IDCT standard. The concept of the fixed-point approximation with accurate dyadic terms is applied to the zero coefficient-aware IDCT algorithm, improving the computational complexity of the authors' previous work. The experimental results show that the running time of the proposed scaled zero coefficient-ware algorithm is faster than that of the fixed-point 8×8 IDCT standard by a speed-up factor of 2.0 times on average and up to 2.6 times for the HD sequences.

Inverse discrete cosine transform architecture exploiting sparseness and symmetry properties

In this paper, a novel architecture for two-dimensional (2-D) inverse discrete cosine transform (IDCT) is implemented using 90-nm CMOS technology. By exploiting the sparseness property of a 2-D discrete cosine transform (DCT) coefficient matrix and the even and odd symmetry properties of the basis vectors of the one-dimensional (I-D) DCT, the proposed architecture reduces computational complexity and increases a throughput rate effectively. First, we derive a recursion equation from the definition of the 2-D IDCT algorithm and use it to design an efficient 2-D IDCT architecture. The proposed architecture consisting of processing elements is suitable for very-large-scale-integration implementation due to its highly regular and scalable structure for 2-D N /spl times/ N IDCT computations. Based on the derived recursion equation, we show how data How for the outer products scaled by only nonzero 2-D DCT coefficients performs 2-D IDCT naturally with low complexities of the controller and the interconnection. The proposed architecture based on the recursion equation provides optimum balance in both hardware complexity and throughput rate when compared with other 2-D IDCT architectures.

A new texture generation method based on pseudo-DCT coefficients

In this paper, a new method for generating different texture images is presented. This method involves a simple transform from a certain one-dimensional (1-D) signal to an expected two-dimensional (2-D) image. Unlike traditional methods, the input signal is generated by a simple 1-D function in our work instead of a sample texture. We first transform the 1-D input signal into frequency domain using fast Fourier transform. Based on the sufficient analysis in 2-D discrete cosine transform (DCT) domain, where each of the coefficients expresses a texture feature in a certain direction, the 2-D pseudo-DCT coefficients are then constructed by appropriately rearranging the Fourier coefficients in terms of their frequency components. Finally, the corresponding texture image can be produced by 2-D inverse DCT algorithm. We applied the proposed method to generate several stochastic textures (i.e., cloud, illumination, and sand), and several structural texture images. Experimental results indicate the good performance of the proposed method.

A fast and memory efficient algorithm for down-conversion of an HDTV bitstream to an SDTV signal

In the future of the digital television (DTV) broadcasting, a standard definition television (SDTV) decoder should have the function of receiving a high definition television (HDTV) signal and display it on its monitor. In order to do so, it is required to convert an HDTV bitstream down to an SDTV signal. In this paper, we propose a fast and memory efficient algorithm for the down-conversion. The proposed algorithm saves lots of computation of the down-conversion by combining inverse discrete cosine transform (IDCT) with the pixel-domain down-conversion. It also requires a smaller memory by performing motion compensation (MC) after the down-conversion, compared to the conventional scheme where MC is performed before the down-conversion. In the brute-force IDCT case, the computation savings of our proposed algorithm are 62%, 74% and 84% for down-sampling ratios of 2:1, 8:3, and 4:1, respectively, with the same picture quality compared to the conventional memory efficient pixel-domain approach. In the case of using a fast IDCT algorithm, the computational savings are respectively 25%, 31% and 37% for down-sampling ratios of 2:1, 8:3, and 4:1.

Computation of discrete cosine transform using Clenshaw's recurrence formula

Clenshaw's recurrence formula is used to derive recursive algorithms for the discrete cosine transform (DCT) and the inverse discrete cosine transform (IDCT). The recursive DCT algorithm presented requires one fewer delay element per coefficient and one fewer multiply operation per coefficient compared with two other proposed methods. Clenshaw's recurrence formula provides a unified development for the recursive DCT and IDCT algorithms. The recursive algorithms apply to arbitrary length algorithms and are appropriate for VLSI implementation. >

An efficient CORDIC array structure for the implementation of discrete cosine transform

We propose a novel implementation of the discrete cosine transform (DCT) and the inverse DCT (IDCT) algorithms using a CORDIC (coordinate rotation digital computer)-based systolic processor array structure. First, we reformulate an N-point DCT or IDCT algorithm into a rotation formulation which makes it suitable for CORDIC processor implementation. We then propose to use a pipelined CORDIC processor as the basic building block to construct l-D and 2-D systolic-type processor arrays to speed up the DCT and IDCT computation. Due to the proposed novel rotation formulation, we achieve 100% processor utilization in both 1-D and 2-D configurations. Furthermore, we show that for the 2-D configurations, the same data processing throughput rate ran be maintained as long as the processor array dimensions are increased linearly with N. Neither the algorithm formulation or the array configuration need to be modified. Hence, the proposed parallel architecture is scalable to the problem size. These desirable features make this novel implementation compare favorably to previously proposed DCT implementations.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>