Inter-partition Communication Research Articles

Algorithmics of Cost-Driven Computation Offloading in the Edge-Cloud Environment

Computation offloading between the edge and the cloud is an effective way for deployed service to fully utilize the resources at both sides for its QoS improvement and overall cost reduction. Although the offloading problem has been intensively studied in the context of mobile computing, existing algorithms in most cases cannot be effectively migrated to the edge-cloud environment because their inter-partition communication costs are always deemed as symmetric, and their intra-partition communication costs are often ignored, which, though reasonable to the traditional case, are not valid to our settings anymore. In this article, we propose a new algorithmic approach to the offloading problem in the edge-cloud environment, where a heterogeneous model is advocated to incorporate the communication cost between co-resident tasks while considering the asymmetry of communication costs between non-coresident tasks. We prove the offloading problem with respect to this model is NP-hard, and thereby designing an efficient algorithm to obtain a sub-optimal solution. Additionally, we also show that in a homogeneous case when the intra-partition and inter-partition communication costs between any pair of interactive tasks are symmetric, an optimal offloading algorithm can be devised by transforming the problem into a classical min-cut problem. We implemented and evaluated the algorithms by offloading a PageRank -based application in a controlled edge-cloud setting. Our empirical results show that the proposed algorithm for the heterogeneous case is always efficient to find a better offloading scheme, compared with the selected existing algorithms, while for the homogeneous case, the proposed solution can efficiently achieve the optimal strategy.

An efficient cell-centered finite-volume method with face-averaged nodal-gradients for triangular grids

In this paper, a face-averaged nodal-gradient approach is proposed as an efficient gradient method for a second-order cell-centered finite-volume discretization on triangular grids. The gradients needed in the linear reconstruction are computed in two steps: (1) compute gradients at nodes from solutions stored at cells, and (2) compute the gradient at each face by averaging the nodal gradients over the nodes forming the face. A unique feature of the proposed approach is that the same face-averaged gradient is used in linear reconstructions from both the left and right cells to the face centroid. This approach offers advantages over a conventional cell-gradient-based finite-volume method: reduced memory requirement for the gradients, smaller residual stencils, direct evaluations of viscous stresses and heat fluxes at solid boundaries, and less interpartition communication. The method is demonstrated for various inviscid and viscous problems from low to high Mach numbers on triangular grids.

Self Diagnostics and Isolation Mechanisms for Mixed Criticality Systems

Virtualization is a technology that is frequently employed in computers and servers to provide isolation for execution environments, and to support the execution of multiple Operating Systems (OS) on the same hardware platform. In the embedded systems´ world, virtualization has been a rising trend, essentially because it offers an isolation mechanism that provides hardware manufacturer´ independence and it avoids obsolescence issues. The isolation mechanism supports safety and security measures, and assists in the certification of safety-critical systems. Virtualization offers improved performances, better transparency, portability and interoperability by integrating hardware and software resources, and also networking services into one computing entity. It makes the integration process of Mixed Criticality Systems (MCS) easier. For industries, FieldProgrammable Gate Arrays (FPGAs) hardware solutions provide the needed level of flexibility and performance. In this paper, a Self-test application is integrated in the hardware and also in the software level. The importance of self-test applications for Instrumentation and Control (I&C) systems will be discussed in the context of virtualization. For this implementation a type 1 hypervisor called Xtratum is used. An analysis of inter-partition communication channels´ performance will be provided including the implications multicore approaches will have on communication. The novelty of this work is to study the isolation impact multicore approaches can have on inter-partitions communications in Xtratum. Another novel aspect is the implementation of a self-test application in the hypervisor and the board as well.

Refinement-Based Specification and Security Analysis of Separation Kernels

Assurance of information-flow security by formal methods is mandated in security certification of separation kernels. As an industrial standard for improving safety, ARINC 653 has been complied with by mainstream separation kernels. Due to the new trend of integrating safe and secure functionalities into one separation kernel, security analysis of ARINC 653 as well as a formal specification with security proofs are thus significant for the development and certification of ARINC 653 compliant S eparation K ernels (ARINC SKs). This paper presents a specification development and security analysis method for ARINC SKs based on refinement. We propose a generic security model and a stepwise refinement framework. Two levels of functional specification are developed by the refinement. A major part of separation kernel requirements in ARINC 653 are modeled, such as kernel initialization, two-level scheduling, partition and process management, and inter-partition communication. The formal specification and its security proofs are carried out in the Isabelle/HOL theorem prover. We have reviewed the source code of one industrial and two open-source ARINC SK implementations, i.e., VxWorks 653, XtratuM, and POK, in accordance with the formal specification. During the verification and code review, six security flaws, which can cause information leakage, are found in the ARINC 653 standard and the implementations.

GrapH: Traffic-Aware Graph Processing

Distributed graph processing systems such as Pregel, PowerGraph, or GraphX gained popularity due to their superior performance of data analytics on graph-structured data. These systems employ partitioning algorithms to parallelize graph analytics while minimizing inter-partition communication. Recent partitioning algorithms, however, unrealistically assume a uniform and constant amount of data exchanged between graph vertices (i.e., uniform vertex traffic ) and homogeneous network costs between workers hosting the graph partitions. This leads to suboptimal partitioning decisions and inefficient graph processing. To this end, we developed GrapH, the first graph processing system using vertex-cut graph partitioning that considers both, diverse vertex traffic and heterogeneous network costs. The main idea is to avoid frequent communication over expensive network links using an adaptive edge migration strategy. Our evaluations show an improvement of 10 percent in graph processing latency and 60 percent in communication costs compared to state-of-the-art partitioning approaches.

ARINC-653 Inter-partition Communications and the Ravenscar Profile

The ARINC-653 standard is offen used to build mixed-criticality systems, using a partitioned architecture. Inter-partition communication is carried out by meands of a message-passing mechanism based on ports. The standard includes an API for Ada, but the implementation semantics of operation ports is not fully defined. Furthermore, the API was defined for the Ada 95 standard, and therefore does not take into account the enhancements to the real-time features of the language that have been incorporated in the 2005 and 2013 standards, most notably the Ravenscar profile. This paper is aimed at clarifying the implementation of ARINC communication ports in Ada and the Ravenscar profile. ARINC communication ports are analysed, and their compatibility with the Ravenscar profile is assessed. A new API that can be used with the profile is defined, and a pilot implementation is introduced.

Research on Applied-Information Technology with Inter-Partition Integration Testing Strategy under IMA Architecture

IMA (Integrated Modular Avionics) system has been widely adopted by a new generation of aircraft. It with high complexity and integration will bring a new challenge in software testing. In this paper, it states what IMA is and how IMA system works. Because of isolation between partitions, the inter-partition communication is required to exchange information between the partitions. It also presents an integrated testing strategy based on UML sequence diagram according to the inter-partition integration of IMA. The method of test sequences generation is discussed emphatically. Finally, a case study is presented to testify the feasibility of our approach.

Generation of Heterogeneous Distributed Architectures for Memory-Intensive Applications Through High-Level Synthesis

Memory-intensive applications present unique challenges to an application-specific integrated circuit (ASIC) designer in terms of the choice of memory organization, memory size requirements, bandwidth and access latencies, etc. The high potential of single-chip distributed logic-memory architectures in addressing many of these issues has been recognized in general-purpose computing, and more recently, in ASIC design. The high-level synthesis (HLS) techniques presented in this paper are motivated by the fact that many memory-intensive applications exhibit irregular array data access patterns. Synthesis should, therefore, be capable of determining a partitioned architecture, wherein array data and computations may have to be heterogeneously distributed for achieving the best performance speed-up. We use a combination of clustering and min-cut style partitioning techniques to yield distributed architectures, based on simulation profiling while considering various factors including data access locality, balanced workloads, inter-partition communication, etc. Our experiments with several benchmark applications show that the proposed techniques yielded two-way partitioned architectures that can achieve upto 2.1 x (average of 1.9 x) performance speed-up over conventional HLS solutions, while achieving upto 1.5 x (average of 1.4 x) performance speed-up over the best homogeneous partitioning solution feasible. At the same time, the reduction in the energy-delay product over conventional single-memory designs is upto 2.7 x (average of 2.0 x). A larger amount of partitioning makes further system performance improvement achievable at the cost of chip area.

Parallel operation of CartaBlanca on shared and distributed memory computers

AbstractWe describe the parallel performance of the pure Java CartaBlanca code on heat transfer and multiphase fluid flow problems. CartaBlanca is designed for parallel computations on partitioned unstructured meshes. It uses Java's thread facility to manage computations on each of the mesh partitions. Inter‐partition communications are handled by two compact objects for node‐by‐node communication along partition boundaries and for global reduction calculations across the entire mesh. For distributed calculations, the JavaParty package from the University of Karlsruhe is demonstrated to work with CartaBlanca. Copyright © 2004 John Wiley & Sons, Ltd.

Exploiting idle floating-point resources for integer execution

In conventional superscalar microarchitectures with partitioned integer and floating-point resources, all floating-point resources are idle during execution of integer programs. Palacharla and Smith [26] addressed this drawback and proposed that the floating-point subsystem be augmented to support integer operations. The hardware changes required are expected to be fairly minimal.To exploit these idle floating resources, the compiler must identify integer code that can be profitably offloaded to the augmented floating-point subsystem. In this paper, we present two compiler algorithms to do this. The basic scheme offloads integer computation to the floating-point subsystem using existing program loads/stores for inter-partition communication. For the SPECINT95 benchmarks, we show that this scheme offloads from 5% to 29% of the total dynamic instructions to the floating-point subsystem. The advanced scheme inserts copy instructions and duplicates some instructions to further offload computation. We evaluate the effectiveness of the two schemes using timing simulation. We show that the advanced scheme can offload from 9% to 41% of the total dynamic instructions to the floating-point subsystem. In doing so, speedups from 3% to 23% are achieved over a conventional microarchitecture.

Experiences with the partitions model

Alsys has implemented a distributed Ada system known as AdaMap which is based on a program partitioning model almost identical to that being proposed for Ada9X, although the user interface for the inter-partition communications system is based on an input-output package rather than on remote procedure call. This paper examines the benefits of the partitions model including a simple demonstration program built using AdaMap, and is intended to give confidene in the viability of the partitions model for Ada9X.

Concurrency and Communication in Hardware Simulators

This paper describes models for concurrency and interpartition communication in a hardware logic simulator implemented using multiprocessors. Software simulation data from production VLSI chips were analyzed in the context of a multiprocessor environment to obtain experimental values for concurrency and communication. The VLSI chips were randomly partitioned in the above experiments. The concurrency observed is significantly lower than the maximum achievable theoretically. This effect was more pronounced for circuits with lower activity. The effect of different simulators (unit and multiple delay), on concurrency and communication, is explained. Finally, a partitioning heuristic whose objective is to enhance concurrency and minimize communication is proposed. It makes use of the circuit topology and the delay information in a simulation database.

PCOS: A Process Control Extension to Operating System/360

This paper discusses the design and implementation of an extension to IBM Operating System/360 that is called PCOS and is intended specifically for use in “real-time” control of IBM manufacturing processes and testing. The most important part of PCOS is a Real-Time Control Program (RTCP) which is initiated at system start-up time as a “never-ending” task. The RTCP controls the execution of application programs and permits system response to requests for their execution within a time on the order of 100 msec. Other contributions are an “express path” for handling input/output operations, an “interpartition communication” program that provides common core storage for use during the execution of application programs, and an appendage to the OS/360 supervisor program to serve a specially designed high-speed multiplexor called the “transmission control unit.”