Internal Block Diagram Research Articles

Dynamic Fault Tree Generation and Quantitative Analysis of System Reliability for Embedded Systems Based on SysML Models.

As embedded systems become increasingly complex, traditional reliability analysis methods based on text alone are no longer adequate for meeting the requirements of rapid and accurate quantitative analysis of system reliability. This article proposes a method for automatically generating and quantitatively analyzing dynamic fault trees based on an improved system model with consideration for temporal characteristics and redundancy. Firstly, an "anti-semantic" approach is employed to automatically explore the generation of fault modes and effects analysis (FMEA) from SysML models. The evaluation results are used to promptly modify the system design to meet requirements. Secondly, the Profile extension mechanism is used to expand the SysML block definition diagram, enabling it to describe fault semantics. This is combined with SysML activity diagrams to generate dynamic fault trees using traversal algorithms. Subsequently, parametric diagrams are employed to represent the operational rules of logic gates in the fault tree. The quantitative analysis of dynamic fault trees based on probabilistic models is conducted within the internal block diagram of SysML. Finally, through the design and simulation of the power battery management system, the failure probability of the top event was obtained to be 0.11981. This verifies that the design of the battery management system meets safety requirements and demonstrates the feasibility of the method.

AI Systems Modeling Enhancer (AI‐SME): Initial Investigations into a ChatGPT‐enabled MBSE Modeling Assistant

AbstractAs artificial intelligence (AI) becomes integral across industries, there is a growing opportunity to transform the generation of models for systems engineering. This research investigates the integration of OpenAI's GPT‐4 Turbo into CATIA Magic for Model‐Based Systems Engineering (MBSE), resulting in the creation of AI Systems Modeling Enhancer (AI‐SME). This study explores the comparison between models generated by AI, specifically OpenAI's GPT, and those crafted by human systems engineers. While recognizing challenges in AI‐generated models, this research underscores the potential of AI assistants to enhance the speed and accuracy of SysML model creation. Results demonstrate AI‐SME's successes in generating requirements, block definition diagrams, and internal block diagrams. Despite identified limitations such as redundancy and lack of cohesiveness in AI‐generated models, the study concludes that AI‐SME represents a notable advancement in AI‐assisted systems engineering.

Model-based safety assessment with SysML and component fault trees: application and lessons learned

Mastering the complexity of safety assurance for modern, software-intensive systems is challenging in several domains, such as automotive, robotics, and avionics. Model-based safety analysis techniques show promising results to handle this challenge by automating the generation of required artifacts for an assurance case. In this work, we adapt prominent approaches and propose to augment of SysML models with component fault trees (CFTs) to support the fault tree analysis and the failure mode and effects analysis. While most existing approaches based on CFTs are only targeting the system topology, e. g., UML class diagrams, we propose an integration of CFTs with SysML internal block diagrams as well as SysML activity diagrams. We realized our approach in a prototypical tool. We conclude with best practices and lessons learned that emerged from our case studies with an electronic power steering system and a boost recuperation system.

Dynamic Fault Tree Generation for Safety-Critical Systems Within a Systems Engineering Approach

Systems are getting increasingly complex and challenging to design. For safety-critical systems, the integration between model-based systems engineering and model-based safety assessment to improve the choice of the system architecture since the early design stage becomes a necessity. One of the integration solutions is to generate fault trees (FTs), either static or dynamic, directly from the system description. In this paper, we are particularly interested in the generation of the dynamic fault trees (DFTs) of the systems that contain redundancies, which is widely used in safety-critical systems to enhance their reliability. The goal of this paper is, first, to propose a redundancy profile and, second, to automatically generate the DFTs from system models. Since errors are propagated via input and output ports of the components, the generation process starts with a depth-first search graph traversal through the systems modeling language internal block diagram of the system. This diagram is considered as a multidirected graph in order to detect the external inputs, the nonredundant components, the switch components, and the redundant components of the system. Then, the redundancy information incorporated in the system model is used to generate the appropriate combinations of the FT. This FT is represented in a suitable format that can be studied using FT analysis tools, for both qualitative and quantitative safety analyses.

Improved Safety Analysis Integration in a Systems Engineering Approach

The goal of the paper is the integration of safety analysis in a model-based systems engineering approach to ensure consistency between system design and safety artifacts. This integration permits the continuous improvement of the structure and behavior of the system. It also reduces system development time and prevents late detection of errors. To reach this purpose, the SafeSysE methodology is extended. In SafeSysE, a preliminary Failure Mode and Effects Analysis (FMEA) is automatically generated from a SysML model, and this FMEA is then completed by the safety expert but no further development was proposed. The contribution of this paper is to suggest recommendations based on the FMEA analysis in order to enhance the system design and make it comply with safety requirements. First, an updated system structure that may contain redundancy is proposed. Then, a redundancy profile is used to enrich the system model with redundancy information, which will allow the generation of a dynamic fault tree considering the system behavior. Finally, the generated dynamic fault tree should be analyzed in order to create a state machine diagram that describes the behavior of the system. The created state machine with an internal block diagram will help the system designers to better understand the system dysfunctions by simulating the system. The proposed methodology is applied to an Electro-Mechanical Actuator system which is used in the aeronautics domain.

Using SysML to Automatically Generate of Failure Modes and Effects Analyses

AbstractThis paper describes a method for automated generation of Failure Modes and Effects Analyses from SysML models containing block definition diagrams, internal block diagrams, state transition machines, and activity diagrams. The SysML model can be created in any SysML modeling tool and then an analysis is performed using the AltaRica language and modeling tool. An example using a simple satellite and ground user shows the approach.

Research on SysML-Based Modeling for Production Management System

A comprehensive and systematic model for the production process of large-scale equipment manufacturing can reduce the cost and time of the development and enforcement of the management system. The characters of a modeling language for systems engineering, SysML(Systems Modeling Language), are introduced, and through analyzing the complexity of the production management system for complex product, the basic requirements of its modeling are given; With the practical example in our project, SysML based model is built for production management system of complex product manufacturing ,the application of requirements diagram, use case diagram, block definition diagram, internal block diagram and activity diagram is introduced emphatically.

Formalizing and verifying compatibility and consistency of SysML blocks

The objective of this paper is to define an approach to formalize and verify the SysML blocks in a refinement process. We propose to specify system architecture with SysML Block Definition Diagram, this diagram is then analyzed and decomposed into several sub-blocks in order to verify their compatibility. The structural architecture of an abstract block is given by the Internal Block Diagram (IBD) which defines the communication links between sub-blocks. The compatibility verification between sub-blocks is only made on linked sub-blocks. The behaviour of each sub-block is described by an interface automaton which species the invocations exchanged with its environment. The verification between blocks is translated into consistency verification between the blocks and compatibility verification between their interface automata. Incompatibilities can be inconsistent at architecture level and at communication level if there are deadlocks during the interaction between sub-blocks. Once the verification is established between the sub-blocks, the abstract block can be then substituted by the sub-blocks which compose it.