Intermittent Errors Research Articles

DDR4 Ball Grid Array Package Intermittent Fracture Effect on Signal Integrity

DDR4 die are commonly packaged in Ball Grid Array packages. The package solder balls develop fractures due to difference in the thermal co-efficient of expansion of the package and printed circuit board. The intermittent behavior of the fracture is due to the momentarily opening of the solder joint due to vibration or the warpage of the package and the printed circuit board. This intermittent behavior can result in no fault found phenomenon in memory systems. DDR4 response in the presence of an intermittent fracture depends on the location of defect. The defect can occur in clock, address or data channel. A test fixture is used to show the AC coupling nature of fracture in ball grid array package solder ball. The intermittent change in the height of fracture is analyzed using 3-D electromagnetic model of the solder ball using high frequency structure simulator (HFSS) software. HFSS model of the fractured solder ball is used along with DDR4 channel topology to compare the sensitivity of clock, address and data channel response to intermittent fracture. It is shown that the data channel is most sensitive to intermittent fracture. DDR4 data mask violation occurs for even a small fracture height of 0.1 μm. For clock channel, the eye degrades or becomes smaller as the fracture height increases from 0.1 μm to 3 μm. But even for 3 μm fracture height, clock eye diagram remains within DDR4 clock +/- 110 mV specification. For address channel the eye degrades or becomes smaller when the height of fracture increases from 0.1 μm to 3 μm. For fracture height of 3 μm, DDR4 address +/- 65 mV input specification violation occurs. Address channel is more sensitive to intermittent fracture as compared to clock channel. The analysis shows that there is always intermittent error in data channel due to intermittent fracture and there are more intermittent errors in address channel compared to clock channel.

DDR4 BER Degradation Due to Crack in FBGA Package Solder Ball

This paper measures bit error rate degradation in DDR4 due to crack in fine pitch ball grid array (FBGA) package solder ball. Thermal coefficient mismatch between the package and printed circuit board material causes cracks to occur in solder balls. These cracks change the electrical model of the solder ball and introduce parallel capacitance in the electrical model. The capacitance causes higher frequency attenuation and closes the data eye. As the data rate of the DDR4 increases there are more data eye closures. The data eye closure causes bit error rate (BER) degradation as the timing margin and voltage margin decreases. This degradation reduces the reliability of the system and causes more intermittent errors. DDR4 data line is loaded with a parallel capacitive element to mimic a crack in solder ball. The measured data eye shows a decrease in eye width. Bathtub plots are created for comparison of cracked solder ball and intact solder ball. The bathtub plots show the BER degradation due to crack in solder ball.

DDR4 Data Channel Failure Due to DC Offset Caused by Intermittent Solder Ball Fracture in FBGA Package

This paper shows that an intermittent AC coupling defect occurring in a DDR4 data channel will cause more intermittent errors in DDR4, compared to such defect in DDR3. The intermittent AC coupling defect occurs due to intermittent fracture in DDR4 package solder ball. The defect causes DC offset in DDR4, which shifts the data signal or data eye and results in DDR4 data channel failure. The DC offset occurs due to the asymmetric nature of pseudo open drain termination scheme. DDR4 data channel response is compared with DDR3 channel. It is shown that pseudo random binary sequence (PRBS) pattern will always cause failure for DDR4, but PRBS will only cause failure in DDR3 if the sequence of consecutive 0’s or 1’s in PRBS pattern is long enough to cause threshold violation. As a result there will be more intermittent errors in DDR4 compared to DDR3. The defect due to fracture in solder ball is modelled by an AC coupling capacitor. A 1nF AC coupling capacitor corresponding to a solder ball fracture of height about 1nm is used to show the difference between DDR4 and DDR3 response.

FBGA solder ball defect effect on DDR4 data signal rise time and ISI measured by loading the data line with a capacitor

This paper proposes a new method of investigating the effect of void or fracture in FBGA solder ball on the DDR4 data signal rise time and inter-symbol interference (ISI), by loading the data line with a capacitor. A void or fracture in solder ball increases its capacitance which effects the data signal rise time and increases ISI. For measuring ISI large consecutive patterns of 1's or 0's followed by a changing bit are used. However in in-field systems it is not possible to run large patterns of 1's or 0's. So the data line is loaded with a 0.2 pF capacitive load on a UDIMM test card to mimic the increased capacitance due to FBGA solder ball void defect of height 0.2 mm and cross sectional area of 0.0045 mm2. The loaded line shows increase in rise time of 16 ps. For loaded line the data eye opening is 0.077 UI lesser. This decrease in data eye means more ISI and will cause increase in intermittent errors.

Simulation model of dependability of redundant computer systems with recurrent information recovery

Today’s digital nanotechnology-based information management systems are especially sensitive to highly-energized particles during operation in irradiated areas. This sensitivity is most often manifested in the form of intermittent soft errors, i.e. distortion of information bits in the system’s memory elements with no hardware failure. The cause is in the afterpulses at the output of the logical elements that occur as the result of ionization of the gate area of the transistor’s semiconductor after it is exposed to a highly-energized particle. In order to counter soft errors the system is equipped with self-repair mechanisms that ensure regular replacement of distorted data with correct data. If this approach to design is employed, the significance of dependability analysis of the system under development increases significantly. Since regular occurrence of soft errors is essentially normal operating mode of a system in conditions of increased radiation, dependability analysis must be repeatedly conducted at the design stage, as that is the only way to duly evaluate the quality of the taken design decisions. The distinctive feature of fault-tolerant hardware and software systems that consists in the presence of nonprobabilistic recovery process limits the applicability of the known methods of dependability analysis. It is difficult to formalize the behaviour of such systems in the form of a dependability model in the context of the classic dependability theory that is geared towards the evaluation of hardware structure. As it has been found out, the application of conventional methods of dependability analysis (such as the Markovian model or probabilistic logic) requires making a number of assumptions that result in unacceptable errors in the evaluation results or its inapplicability.Aim. Development of the model and methods of dependability analysis that would allow evaluating the dependability of hardware and software systems with periodic recovery.Results. A simulation model was developed that is intended for dependability evaluation of complex recoverable information management systems. The model is a network of oriented state graphs that allows describing the behaviour of a recoverable system subject to the presence of computation processes and recovery processes that operate according to non-stochastic algorithms. Based on the simulation model, a software tool for dependability analysis was developed that enables probabilistic estimation of dependability characteristics of individual system units and its overall structure by means of computer simulation of failures and recoveries. This tool can be used for comprehensive dependability evaluation of hardware and software systems that involves the analysis of recoverable units with complex behaviour using the developed simulation model, and their operation along with simple hardware components, such as power supplies and fuses, using conventional analytical methods of dependability analysis. Such approach to dependability evaluation is implemented in the Digitek Reliability Analyzer dependability analysis software environment.Practical significance.The application of the developed simulation model and dependability analysis tool at the design stage enables due evaluation of the quality of the produced fault tolerant recoverable system in terms of dependability and choose the best architectural solution, which has a high practical significance.

Temporal and frequency characteristic analysis of margin-related failures caused by an intermittent nano-scale fracture of the solder ball in a BGA package device

This paper analyzes the solder ball fracture that could be a source of intermittent errors. The electrical characteristics of a momentary fracture (open), which may appear at the very beginning of a progressive solder ball failure, are extensively studied. The alternating current (AC)-coupling capacitor is defectively formed because of the fractured solder ball, and it can block low-frequency components of the bit data stream. The distorted signal reduces signal integrity under the fracture and results in increased jitter and reduced eye window. This fracture causes the dropping of the signal voltage level, and this dropping erroneously affects the system when multiple failing conditions are simultaneously satisfied. The major failing condition is the fracture height size, which determines the defective AC-coupling capacitor and changes the channel transmission characteristic. The other major condition is the bit pattern, which includes the frequencies affected by the defective channel. SPICE simulation is conducted to demonstrate the effects of a momentary fracture using the DDR3 memory tester system. In the case of a 10nm fractured solder ball with a pseudo-random binary sequence (PRBS) pattern, the eye height is reduced from 597mV to 349mV, and the jitter is increased from 38ps to 132ps. The bits that violate the eye-mask window begin to appear with a heavy bit stream and cause intermittent bit errors.

A software scheduling solution to avoid corrupted units on GPUs

Massively parallel processors provide high computing performance by increasing the number of concurrent execution units. Moreover, the transistor technology evolves to higher density, higher frequency and lower voltage. The combination of these factors increases significantly the probability of hardware failures. In this paper, we present a methodology to locate and mitigate hardware failures of Nvidia GPUs. Results show that intermittent errors can be precisely localized and have a limited impact to a well defined architecture tile. Therefore, we propose, and demonstrate on a software prototype, a rescheduling strategy to quarantine the defective hardware and ensure correct execution. Our approach significantly improves the GPU fault-tolerance capability and GPU’s lifespan, at a reasonable overhead.

An Efficient Application Mapping Approach for the Co-Optimization of Reliability, Energy, and Performance in Reconfigurable NoC Architectures

In this paper, an efficient application mapping approach is proposed for the co-optimization of reliability, communication energy, and performance (CoREP) in network-on-chip (NoC)-based reconfigurable architectures. A cost model for the CoREP is developed to evaluate the overall cost of a mapping. In this model, communication energy and latency (as a measure of performance) are first considered in energy latency product (ELP), and then ELP is co-optimized with reliability by a weight parameter that defines the optimization priority. Both transient and intermittent errors in NoC are modeled in CoREP. Based on CoREP, a mapping approach, referred to as priority and ratio oriented branch and bound (PRBB), is proposed to derive the best mapping by enumerating all the candidate mappings organized in a search tree. Two techniques, branch node priority recognition and partial cost ratio utilization, are adopted to improve the search efficiency. Experimental results show that the proposed approach achieves significant improvements in reliability, energy, and performance. Compared with the state-of-the-art methods in the same scope, the proposed approach has the following distinctive advantages: 1) CoREP is highly flexible to address various NoC topologies and routing algorithms while others are limited to some specific topologies and/or routing algorithms; 2) general quantitative evaluation for reliability, energy, and performance are made, respectively, before being integrated into unified cost model in general context while other similar models only touch upon two of them; and 3) CoREP-based PRBB attains a competitive processing speed, which is faster than other mapping approaches.

Integration testing of communicating systems with unknown components

The verification of a modular system composed of communicating components is a difficult problem, especially when the formal specifications, i.e. models of the components are not available. Conventional testing techniques are not efficient in detecting erroneous interactions of components because interleavings of internal events are difficult to reproduce in a modular asynchronous system. The problem of detecting intermittent errors and other compositional flaws in the absence of components’ models is addressed in this paper. A method for inferring a controllable approximation of communicating components through testing is elaborated. The inferred finite state models of components are used to detect compositional problems in the system through reachability analysis. To confirm a flaw in a particular component, a witness trace is used to construct a test applied to the component in isolation. The models are refined at each analysis step thus making the approach iterative. The proposed approach employs techniques for machine inference, testing and reachability analysis, and can reveal flaws due to the non-deterministic behaviour of a modular distributed system, such as unspecified receptions, livelocks, divergences, and races that would not be detected by testing alone. One key advantage of the approach is that by means of the inference parameter, it allows one to find a compromise between the co mplexity of testing the integrated system and the precision of the resulting models. The use of large tests is completely avoided in testing a component in isolation, since only single diagnostic test is executed in each iteration. Another advantage of the approach is that inferred models capture the functionalities of components used in the given system; unused behaviours of components are not modelled.

Guided Probabilistic Checksums for Error Control in Low-Power Digital Filters

In many DSP applications (image and voice processing), several dBs of SNR loss can be tolerated without noticeable impact on application level performance. For power optimization in such applications, voltage overscaling (VOS) can be used to operate the arithmetic circuitry at or marginally below the critical circuit path delay while incurring tolerable SNR loss due to the resulting periodic errors in computation. In this paper, low cost checksum codes are used for detection and compensation of intermittent errors due to voltage overscaling in linear digital filters. In traditional coding theory, diagnosis of errors is a key problem and incurs significant computation and latency cost. In the proposed approach, low-precision shadow latches are used to identify likely sources of errors due to voltage overscaling to avoid error diagnosis. This allows accurate error compensation with distance-2 checksum codes that are normally good only for error detection but not for correction. Very precise compensation is achieved by distributing the negative of the error value evenly across only the likely erroneous states. This is called guided probabilistic compensation, as compensation is not exact when errors occur simultaneously in more than one state. A feedback controller is used for dynamic voltage overscaling (DVOS) while keeping the error rate in the system within an acceptable range. It is shown that the low cost accurate error compensation allows significant power savings with minimal degradation in system performance (SNR).

Influence of controlled tool orientation on pattern formation and waviness in surface grinding

The surface of ground components can exhibit quality impairments which are attributed to grinding wheel irregularities. A remaining grinding wheel imbalance or a non-uniform grinding wheel topography results in a radial run-out which strongly affects the generated surface. By measuring and adjusting the phase-shift of the grinding wheel orientation during consecutive grinding passes, the resulting workpiece surfaces can significantly be improved. Experimental investigations show a strong effect of the phase-shift on the waviness profile and the pattern formation, as the pattern wave length coincides with the tangential feed. Setting the phase-shift directly affects the engagement conditions like the contact stiffness, remarkably influencing the dynamic process behaviour. The amplitudes of the normal force at rotational frequency have a strong effect on the workpiece surface, which can be influenced by a variation of the phase-shift. Constancy of table oscillating period will further increase due to faster machine control hardware, making longer periods of constant phase-shifts more likely to occur. As this parameter is mostly uncontrolled, it can cause intermittent grinding errors.

What is stochastic computation?

Stochastic computation [shan-1] is a communications-inspired [shan-2] model of computation for jointly achieving robustness and energy-efficiency in systems implemented in nanoscale processes. Emerging applications, driven by societal needs in security, health and energy [jan], tend to be media/sensory data-intensive with primary emphasis on the extraction of features/models in order to enable cognitive, detection and decision-making tasks. Stochastic computation exploits the somewhat relaxed definition of "correctness" afforded by such applications by incorporating application-awareness and statistical performance metrics (e.g., signal-to-noise ratio (SNR) and bit error-rate (BER) in communications, probability of anomaly detection in biomedical applications and others) into the design of computational platforms. Nanoscale circuit and device fabrics exhibit artifacts such as process, voltage and temperature (PVT) variations, leakage, soft errors, and noise leading to intermittent errors and hence a reliability problem. Stochastic computation matches the error statistics of the underlying circuit fabrics to the statistical performance metrics of emerging applications in order to enhance robustness by orders-of-magnitude and simultaneously achieve significant energy-efficiency. It may seem that stochastic computation may not be applicable to small class of critical applications such as those in finance/banking, flight control systems, and others whereas precise definition of correctness is mandatory. This is until one realizes that the inherent communication mechanisms in such systems are in fact stochastic in nature.

Propositionalizing the EM algorithm by BDDs

We propose an Expectation-Maximization (EM) algorithm which works on binary decision diagrams (BDDs). The proposed algorithm, BDD-EM algorithm, opens a way to apply BDDs to statistical learning. The BDD-EM algorithm makes it possible to learn probabilities in statistical models described by Boolean formulas, and the time complexity is proportional to the size of BDDs representing them. We apply the BDD-EM algorithm to prediction of intermittent errors in logic circuits and demonstrate that it can identify error gates in a 3bit adder circuit.

Error detection in three-dimensional surface anthropometric data

In recent years, the use of three-dimensional surface anthropometry has facilitated the collection of anthropometric data. Given the importance of reducing errors and securing data quality, data checking procedures are necessary. After an influential study done by Fellegi, I.P., Holt, C. [1976. A systematic approach to automatic edit and imputation. Journal of the American Statistical Association 71, 17–35], many survey organizations adopted data checking procedures to determine whether data are reliable or not. Detection of erroneous data is an essential part of data checking. An important feature of anthropometric data is that the data are continuous and multivariate and have strong correlations among variables. Because of the patterns of intermittent errors in multivariate data, data checking can be very complicated. The objective of this study is to propose an error detection procedure that uses a dynamic and interactive graphical method for anthropometric data. Furthermore, we present the results from applying this procedure to the data from the Korean National Anthropometric Survey, Size Korea 2004. Relevance to industry Anthropometric data provide a valuable source of information to ergonomists and designers. The results of this study can help to increase the reliability of anthropometric data collected by three-dimensional measurement approaches.

Online Reconfigurable Self-Timed Links for Fault Tolerant NoC

We propose link structures for NoC that have properties for tolerating efficiently transient, intermittent, and permanent errors. This is a necessary step to be taken in order to implement reliable systems in future nanoscale technologies. The protection against transient errors is realized using Hamming coding and interleaving for error detection and retransmission as the recovery method. We introduce two approaches for tackling the intermittent and permanent errors. In the first approach, spare wires are introduced together with reconfiguration circuitry. The other approach uses time redundancy, the transmission is split into two parts, where the data is doubled. In both structures the presence of permanent or intermittent errors is monitored by analyzing previous error syndromes. The links are based on self-timed signaling in which the handshake signals are protected using triple modular redundancy. We present the structures, operation, and designs for the different components of the links. The fault tolerance properties are analyzed using a fault model containing temporary, intermittent, and permanent faults that occur both as bursts and as single faults. The results show a considerable enhancement in the fault tolerance at the cost of performance and area, and with only a slight increase in power consumption.

A 1.3-GHz fifth-generation SPARC64 microprocessor

A fifth-generation SPARC64 processor is fabricated in 130-nm partially depleted silicon-on-insulator CMOS with eight layers of Cu metallization. At V/sub dd/ = 1.2 V and T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">a</sub> = 25°C, it runs at 1.3 GHz and dissipates 34.7 W. The chip contains 191 M transistors with 19 M logic circuits in an area of 18.14 mm × 15.99 mm and is covered with 5858 bumps, of which 269 are for I/O signals. It is mounted in a 1360-pin land-grid-array package. The 16-byte-wide system bus operates with a 260-MHz clock in single-data-rate or double-data-rate modes. This processor implements an error-detection mechanism for execution units and data path logic circuits in addition to on-chip arrays to detect data corruption. Intermittent errors detected in execution units and data paths are recovered via instruction retry. A soft barrier clocking scheme allows amortization of the clock skew and jitter over multiple cycles and helps to achieve high clock frequency. Tunability of the clock timing makes timing closure easier. A relatively small amount of custom circuit design and the use of mostly static circuits contributes to achieve short development time.

Improving Research Aircraft Navigation by Incorporating INS and GPS Information in a Variational Solution

Abstract With the new (potentially more accurate) Global Position System (GPS) measurements available, aircraft navigation systems are significantly improved. Since the GPS can drop out occasionally and exhibit other intermittent errors, it cannot be used exclusively for all navigational needs. The traditional Inertial Navigation System (INS) position and velocity measurements, on the other hand, suffer from large Schuler oscillation and drift errors over the duration of a flight. This work proposes and tests a variational method to determine improved aircraft positions and velocities when both INS and GPS data are available. This technique incorporates GPS position and velocity data and INS acceleration data. The data are weighted by the reciprocal of the variance of their errors. Error characteristics of the data are determined objectively by examining the internal consistency of the data themselves. The resulting improved position and velocity time series are fully internally consistent. The data used ...

Reliability levels for fault-tolerant linear processing using real number error correction

Fault-tolerant linear processing systems using real number codes, as in algorithm-based fault tolerance methodologies, can be extended to include error correction for correcting intermittent errors in the processed output data. The reliability function for a protected system containing correction is considered under simple but realistic assumptions on the arrival of failures in both the normal processing and corrector subassemblies. An error-correcting procedure employing a real, convolutional code is described briefly, and a system diagram of a corrector subsystem containing self-checking comparators for detecting its internal failures is presented. Failures are modelled as arriving according to Poisson processes in both parts of the fault-tolerant system. Formulas for the reliability of the protected system are given and an efficient lower bound is developed. This bound depends only on broad details such as relative areas used in a VLSI design of the processing and corrector parts. Computational methods employing computer algebra packages are discussed, and some typical reliability curves for two configurations demonstrate the dramatic improvement which error correction introduces.

Modification of: error log analysis: statistical modeling and heuristic trend analysis

The above-titled paper by T.-T.Y. Lin and D.P. Siewiorek (see ibid., vol.39, p.419-32, Oct. 1990) used traditional statistical analysis to demonstrate the superiority of the proposed dispersion frame technique. The purpose was to distinguish between transient and intermittent errors and predict the occurrence of intermittent errors. It is shown here that those traditional statistical methods were too traditional, since they involved fitting a distribution to data which were not identically distributed. Appropriate statistical techniques for fitting models to such nonstationary data are briefly discussed, and reasons are proffered for the persistence of too-traditional statistical methods in the reliability literature. >

4932028 Error log system for self-testing in very large scale integrated circuit (VLSI) units

A VSLI chip is implemented with registers which log permanent and intermittent errors occurring within the chip as sensed by concurrent error detection circuitry (CED). If a fatal error is detected (one which would destroy the reliability of chip operations), then the chip is immobilized into a hold mode (freeze). Interrupts are signalled to a cooperating maintenance controller which can pass the error information to an external computer for display and for locating a faulty area.