Interface State Density Research Articles

Sputter-Deposited copper iodide thin film transistors with low Operating voltage

This paper reports on a back-gated p-type thin film transistor (TFT) with copper iodide (CuI) as the channel material, a HfO2 gate dielectric layer, and Al2O3 passivation. The γ-CuI channel was deposited from a CuI target using DC magnetron sputtering at room temperature. Our TFT can be fully shut off by VG = 4 V, with a field-effect channel hole mobility μh ∼ 1.5–2 cm2 V−1 s−1. An anneal in forming gas was performed twice, once at 200 °C, then at 250 °C to improve gate control, yielding a final Ion/Ioff current ratio of ∼ 250. The anneal served two purposes: to reduce the oxygen acceptor density in the CuI channel and reduce the concentration of interface states between the CuI, Al2O3 passivation, and HfO2. A model of the device was built in an industrial TCAD simulator, which reproduces the measured characteristics and allows an estimation of interface state densities and channel doping.

Improved Subthreshold Characteristics of Epi-Silicon FinFET via Fin Surface Passivation Technologies

As demand for advanced integrated circuits (ICs) continues to grow, fin field-effect transistors (FinFETs) have remained highly influential in the IC market because of their mature fabrication process and powerful driving capabilities. However, the ion bombardment that occurs during the reactive ion etching (RIE) process used to form the fin structure increases the fin’s surface roughness and results in a high interfacial state density (D it ), which hinders further improvement in the subthreshold swing (SS) of FinFETs. To overcome this issue, this study proposes two oxidative trimming methods for use on the fin structures to improve their interface quality. It is found that conventional thermal oxidation and low-temperature oxidation processes reduced the channel D it by 73.31% vs 71.17%, respectively. Furthermore, the corresponding SS values of the device improved to 72.76 and 71.72 mV dec−1, respectively. The technical solutions proposed in this paper represent a promising approach for performance optimization of FinFETs and other advanced devices.

Impact of orbital hybridization on spin-polarized electronic transport through Ni-MAPbI3 interfaces

The solution-processed methylammonium lead tri-iodine (MAPbI3), with long spin lifetimes and large spin diffusion lengths, has merit for developing stable perovskite spin valves (PeSV) with low saturation fields. By far, it remains challenging to avoid ill-defined ferromagnet-MAPbI3 interfaces during device fabrications using solution methods and to quantify the hybridized interfacial electronic and magnetic structures. Herein, an annealing-free method was developed for the fabrication of MAPbI3 based PeSV. In comparison to a thermally annealed device, an improved room temperature magnetoresistance (MR) was achieved. We found remarkable interfacial contributions to anisotropic magnetoresistance and MR. The first-principles calculation was further adopted to quantify the interfacial spin and orbital moments. Our results suggest that the orbital hybridization and the spin transfer are remarkable for the formation of the spin-dependent interfacial density of states. It consequently affects magnetic switching behaviors. This study holds an exceptionally important role for a deep understanding of the spin-polarized electronic transport through the Ni-MAPbI3 hybridized interface.

Enhancing tetrafullerene based photosensors and photovoltaic cells by graphene oxide doping

This study explores the postulated potential of tetrafullerene as a charge transport material when combined with dispersed graphene oxide (GO), over concerns about fullerene’s limited performance in similar devices. Incorporating GO is expected to augment carrier concentration, increase surface area, and reduce operating voltages. Devices fabricated with p-Si/tetrafullerene with varying GO concentration exhibit notable enhancements in both dark and illuminated characteristics. The results demonstrate improved electron concentration and transport, leading to enhanced rectification ratios, ideality factors, and interface state densities across a broad bias and illumination range. Notably, devices doped with 0.2GO exhibit the most promising electrical and photoresponse characteristics, showcasing potential for applications in photosensing and photovoltaics.

Ultrahigh growth rate-induced thick 3C-SiC heteroepitaxial layers on 4H-SiC and its oxidation characteristics

The cubic 3C-SiC displays unique advantages in power electronics applications due to its high channel mobility and low SiO2/3C-SiC interface state density. Therefore, the epitaxial growth technology of 3C-SiC is one of the core technologies for preparing high-performance SiC power devices. In this work, we choose 4H-SiC as substrates to grow 3C-SiC with methyltrichlorosilane (MTS)-H2 complex precursor and acheieved an ultrahigh epitaxial growth rate up to 278 μm/h. Then the oxidation treatment has been conducted. The elemental composition, surface morphology, and crystalline phase of the prepared 3C-SiC/4H–SiC thick films were comprehensively characterized with SEM, Raman, XRD and TEM techniques. The growth mechanism and oxidation characteristics of the 3C-SiC/4H-SiC heteroepitaxial layers were analyzed based on experimental phenomena.

Emission of Trapped Electrons from the 4H-SiC/SiO<sub>2</sub>-Interface via Photon-Irradiance at Cryogenic Temperatures

For a reliable MOSFET performance it is crucial to identify and reduce device performance limiting 4H-SiC/SiO2 interface defects. Previous studies have focused on the quantification of the interface states density, however, the atomic defect structure is still to be investigated. Here, we introduce a new approach based on opto-electrical measurements, which allow to determine the energetic position of interface defects. The measurement routine is performed at cryogenic temperatures to suppress the thermal emission of electrons, which were trapped at interface states during the cooldown processed (from 300 K to 15 K) while a positive gate voltage of 50 V was applied. At 15 K the photon-assisted emission of trapped electrons is measured in dependence on the photon’s energy (1.8 eV-3 eV). The reduction of the threshold voltage is taken as an indicator for the amount of released charges after each photon irradiation. We found an enhanced emission efficiency at certain photon energies, especially at 2.8 eV. Near-interface-traps (NITs), reported by Afanasev et al. are located close to the measuredtrap level with ENIT = EC, SiO2−2.77(5) eV. Recently, El-Sayed et al. suggested wide-angle O-Si-Obonds as defect configuration, that act as electron traps and have a similar energy as the measure traplevel.

Characterization of interface states and investigation of possible current conduction mechanisms in the Pt, Au, Cu/n-InP Schottky diodes

Based on the capacitance/conductance–voltage (C/G–V) and current–voltage (I–V) methods, the interface characteristics and the current conduction mechanisms of Pt/n-InP Schottky contacts were studied in detail. The interface states strongly affected the values of capacitance in the depletion region. From Terman, G–V, and forward I–V methods, the interface state density (D it) was found to range from mid-1012 to mid-1013 eV−1cm−2. The forward current characteristics was not elucidated by the thermionic emission (TE) model assisted by tunneling via the interfacial layer. Rather, the spatially distributed inhomogeneous barrier could interpret the forward current characteristics. Trap-assisted tunneling involving phosphorous vacancy (VP)-related defects was observed to be dominant in the case of the reverse current characteristics. The comparison of Pt metal contact with Cu and Au contacts revealed that Pt contact has the highest D it among three contacts.

Voltage-frequency dependence of the complex dielectric and electric modulus and the determination of the interface-state density distribution from the capacitance-frequency measurements of Al/p-Si/Al and Al/V2O5/p-Si/Al structures

The energy distribution of the interface states (Nss) and relaxation time (τ) are calculated from the capacitance-frequency (C-f) characteristics for Al/p-type Si/Al metal-semiconductor and Al/V2O5/p-type Si/Al metal–interfacial layer–semiconductor diodes with and without anodic surface passivation. The experimental results show that the density of the interface states and the relaxation times increase almost exponentially with the bias from the top of the valence band to the center of the gap for each diode produced. At the same time, using the C-f characteristics, the dielectric properties such as the dielectric constant (ε′), dielectric loss (ε″), dielectric loss tangent (tanδ), real and imaginary portions of the electric modulus (M’ and M″) and ac electrical conductivity (σac) are investigated in this study. The analysis was performed at room temperature, in the frequency range from 1 kHz to 10 MHz, and the voltage range from 0 to 0.24 V. The experimental results show that the ε′, ε″ and tanδ values decrease with increasing frequency while σac, M′ and M″ values increase. This results will show that dielectric parameters are strongly frequency dependent.

A strategy to predict the current conduction mechanisms into Al/PVP:Gr-BaTiO3/p-Si Schottky structure using Artificial Neural Network

In this work, Artificial Neural Network (ANN) algorithm is used to predict the current conduction mechanisms into the metal-semiconductor (MS) and metal-nanocomposite-semiconductor (MPS) structures along with their primary electronic parameters, such as the leak current (I0), potential barrier height (ΦB0), ideality factor (n), series/shunt resistance (Rs/Rsh), rectifying ratio (RR), and interface states density (Nss) by analyzing the I–V characteristics. The polyvinylpyrrolidone (PVP), barium titanate (BaTiO3) and graphene (Gr) nanoparticles are mixed together to create the interfacial nanocomposite layer. Training data for ANN algorithm is gathered using the thermionic emission hypothesis. In order to study the efficacy of the ANN model, the predictive power of the ANN technique for predicting the current conduction mechanisms and electronic properties of SDs has been assessed by comparing the predicted and experimental results. The ANN predictions of the current conduction mechanisms at the forward/reverse bias and the fundamental electronic specifications of the MS and MPS structures are a high level of agreement with the experimental results. Furthermore, the results show that the RR and Rsh rise whereas the n, Rs, and Nss for MS structure decrease when the PVP:Gr-BaTiO3 nanocomposite interlayer is employed.

Deep-level transient spectroscopy of defect states at p-type oxide/β-Ga2O3 heterojunctions

Defects in p-type oxide/β-Ga2O3 heterojunction diodes were investigated using p-type Cu2O as a case study. Diodes with polycrystalline and epitaxial Cu2O films were analyzed using deep-level transient spectroscopy. For both diodes, two electron bulk defects were detected, including a minority defect at 0.23 eV below EC within Cu2O and a majority defect at 0.53 eV below EC within β-Ga2O3. Furthermore, a high-density interface state of 4.5 × 1012 cm−2/eV was observed in the polycrystalline Cu2O/β-Ga2O3 diode. The presence of a high density of interface states helped reduce the turn-on voltage owing to the interface recombination current. However, it also enabled electron carriers to tunnel through the interface to β-Ga2O3, followed by variable range hopping through the bulk defect in the β-Ga2O3 layer, ultimately causing undesirable premature breakdown. The results of this study underscore the critical role of optimizing the crystal structure during p-type oxide growth for desired defect characteristics, particularly concerning interface states, in β-Ga2O3 bipolar devices for different applications, offering insights for high-performance power rectifier development.

Measurement of Interface State Density on Pn-paterned Si Surface Using High- and Low-frequency Kelvin Probe Force Spectroscopy

Measurement of Interface State Density on Pn-paterned Si Surface Using High- and Low-frequency Kelvin Probe Force Spectroscopy

(Invited) Consideration on Gate Stack Formation Processes of Ultrawide Bandgap Ga2O3 with SiO2 Dielectric Layer

MOSFETs on β-Ga2O3 are expected to be a high-efficient and cost-effective alternative option of high-voltage power devices. Taking account of the reliability and the large conduction-band offset against β-Ga2O3, it would be reasonable to employ SiO2 as the gate dieletric. In this study we investigated the effects of post-deposition annealing (PDA) on SiO2/β-Ga2O3 MOS gate stacks, in terms of the MOS electrical characteristics and the band alignment.β-Ga2O3 (001) wafers with ~2×1016 cm-3 n-type doped epitaxial layers were cleaned in diluted HF solution, and SiO2 films were deposited by electron-beam (EB) evaporation of Si in O2 ambient of ~1×10-2 Pa, followed by PDA at various temperatures from 600 to 1000℃ in either O2 or N2 ambient. Au was evaporated as gate electrode to form MOS capacitors. X-ray photoelectron spectroscopy (XPS) was conducted on the stacks with ~3nm-thick SiO2 for the evaluation of band alignment. Ultraviolet photoelectron spectroscopy (UPS) was also employed to determine the band diagram of β-Ga2O3 (001).Nearly-ideal capacitance-voltage characteristics were obtained for the MOS capacitor fabricated with O2-PDA at 1000℃. The interface state density (Dit) determined by conductance method decreased down to ~1010 cm-3 at the energy level of EC−0.2 eV by PDA at higher temperature. The hysteresis width (ΔVhys) of C-V curves was smaller for the samples annealed at higher temperatures. The flatband voltage (VFB) shift after O2-PDA resulted in VFB close to the ideal value estimated from the physical properties of Au and Ga2O3, suggesting that fixed charge density at the interface would be minimized. However, PDA in N2 at 1000℃ resulted in a negative shift of VFB, which indicates the formation of positive fixed charges in the stack. The beneficial influences of O2-PDA on those characteristics suggest that an oxygen deficiency introduced near the interface is one of the origins of interface defect states. It is noteworthy that Ga3d XPS on the surface of Ga2O3 substrate always shows a tailing in lower binding energy side, which is indicating oxygen deficiency on the surface. The intensity of this lower-binding-energy component reduced significantly when a bare-Ga2O3 substate was annealed in O2, however, it did not decrease efficiently even after O2-PDA when the surface was covered with SiO2. This is probably due to the oxygen rearrangement at SiO2/Ga2O3 interface determined by the difference of material properties of those oxides. This fact suggests that the Ga2O3 surface easily forms oxygen vacancies when it is covered with SiO2. This would be the reason why the formation of interface defect states is not suppressed without O2-PDA.Next the band diagram of β-Ga2O3 (001) substrate was investigated by UPS analysis where the energy level of valence band edge referring to the vacuum level was evaluted from the energy difference between minimum (cut-off) and maximum edges of the obtained kinetic energy spectra of photoelectrons. As a result we found the valence band edge of of β-Ga2O3 (001) was ~8.2 eV below the vacuum level, where the influences of O2 annealing at 1000℃ on the valence band edge energy level was limited to the shift within ~0.1eV. This would tell us the valence band offset between SiO2 and Ga2O3 should be around ~1.1eV, and the conduction band offset between them is to be around 2.8-2.9eV, by taking account of the well-reported SiO2 band diagram and assuming the bandgap of β-Ga2O3 as 4.7eV. On the other hand, the valence band offset estimated from the deconvolution of the XPS valence band spectrum for a ~3nm-thick SiO2/β-Ga2O3 stack from the energy edge difference between the deconvoluted spectra corresponding to SiO2 and Ga2O3, was a few hundreds of mV smaller than the above expected value (~1.1eV). This discrepancy is indicating the formation of an interface dipole layer between SiO2 and Ga2O3 with a pair of nagative and positive charges aligned at the interface to cause a shift in the band alignment. The magnitude of such dipole was indicated to be more significant (~0.5eV) for the stack after PDA at 1000℃, whereas it was less (0.2~0.3eV) after PDA at 600℃.In conclusion, we demonstrated that SiO2/β-Ga2O3 (001) MOS capacitors showed nearly-ideal electrical characteristics with significantly reduced interface defect density and small fixed charge density by applying O2-PDA. The band alignment of SiO2/β-Ga2O3 (001) MOS stack was clarified by photoelectron spectroscopy to confirm a very large conduction band offset of the stack, but an influence of the formation of interface dipole layer between SiO2 and Ga2O3 on the band alighment was also indicated.

Single-crystalline metal-oxide dielectrics for top-gate 2D transistors.

Two-dimensional (2D) structures composed of atomically thin materials with high carrier mobility have been studied as candidates for future transistors1-4. However, owing to the unavailability of suitable high-quality dielectrics, 2D field-effect transistors (FETs) cannot attain the full theoretical potential and advantages despite their superior physical and electrical properties3,5,6. Here we demonstrate the fabrication of atomically thin single-crystalline Al2O3 (c-Al2O3) as a high-quality top-gate dielectric in 2D FETs. By using intercalative oxidation techniques, a stable, stoichiometric and atomically thin c-Al2O3 layer with a thickness of 1.25 nm is formed on the single-crystalline Al surface at room temperature. Owing to the favourable crystalline structure and well-defined interfaces, the gate leakage current, interface state density and dielectric strength of c-Al2O3 meet the International Roadmap for Devices and Systems requirements3,5,7. Through a one-step transfer process consisting of the source, drain, dielectric materials and gate, we achieve top-gate MoS2 FETs characterized by a steep subthreshold swing of 61 mV dec-1, high on/off current ratio of 108 and very small hysteresis of 10 mV. This technique and material demonstrate the possibility of producing high-quality single-crystalline oxides suitable for integration into fully scalable advanced 2D FETs, including negative capacitance transistors and spin transistors.

Comparison of Si and SiC MOSFETs responses to electrical stress and the observation of parameter recovery in SiC MOSFET by stress superposition

In this study we examined the effects of room temperature DC and AC electrical stress on Si and SiC n-channel metal-oxide-semiconductor field effect transistors (MOSFETs). Measurement of threshold voltage, transconductance, subthreshold swing, charge pumping, and gate oxide breakdown are used to compare the impact of stress on Si MOSFETs and SiC MOSFETS, as well as to understand the processes of carrier injection and trapping at oxide and interface defects. DC stress is observed to promote negative charge buildup in the gate oxide and interface in Si MOSFETs. However, in SiC MOSFETs the net charge buildup sign alternates between negative and positive as the DC stress polarity is changed from positive to negative, respectively. For the same stress level, relative degradation in parameters of SiC MOSFETs are significantly smaller than those in Si MOSFETs, where in the latter interface state density, conductance, and subthreshold swing have degraded by up to 400%.The change of charge buildup sign explains our observation that degradation in SiC MOSFETs subjected to AC bipolar stress is insignificantly small, whereas AC stressing of Si MOSFETs is observed to be much more severe. Also, the superposition of alternating DC stress polarity eliminates the stress induced degradation in SiC MOSFETs thus enabling a straightforward process for parameter reconfiguration and recovery.

Influence of fixed charges and trapped electrons on free electron mobility at 4H-SiC(0001)/SiO2 interfaces with gate oxides annealed in NO or POCl3

Free electron mobility (μ free) in 4H-SiC(0001) MOSFETs with gate oxides annealed in NO or POCl3 was calculated in a wide range of effective normal field (E eff) from 0.02 to 2 MV cm−1, taking account of scattering by fixed charges and trapped electrons. The present calculation indicates that the Hall mobility in the high-E eff region experimentally obtained for NO-annealed MOSFETs (14 cm2 V−1 s−1 at 1.1 MV cm−1) is much lower than that for POCl3-annealed MOSFETs (41 cm2 V−1 s−1) due to severe Coulomb scattering by electrons trapped at a very high density of interface states.

Interface state density in mist chemical vapor deposited Al2O3/AlGaN/GaN structure

Uniform thickness Al2O3 thin films have been deposited by eco-friendly mist CVD. The obtained Al2O3 film has an optical band gap value of more than 6.5 eV and a refractive index of 1.64 at 633 nm. The combination of capacitance–voltage (C–V) fitting method with non-linear least-squares algorithm, frequency dispersion, photo-assisted, and proposed reverse bias-assisted C–V methods revealed interface state densities ranging from 1 × 1012 to 3 × 1013 cm−2eV−1 along the mist-Al2O3/AlGaN interface. These values are comparable to those reported for atomic layer deposited Al2O3 thin films.

Simulation and Comparative Study of Propagation Delay in Multi-Channel Quantum SWS-CMOS-Based Inverters Using II–VI Gate Insulator

This paper investigates the effect of lattice-matched II–VI ZnS-ZnMgS stack as the gate insulator on the propagation delay of a 4-state quantum spatial wavefunction-switched (SWS)-CMOS-based inverters and SRAMs. The novelty is the smaller density of interface states which reduces the fluctuations in the various threshold voltages of the SWS-FETs and logic and memory devices using them. Two SWS-CMOS-based inverter models using SiO2 and lattice-matched II–VI ZnS-ZnMgS stack as the gate insulator, are presented. Cadence simulations are used for comparing the single stage propagation delay of each inverter and their four-state logic transitions.

Effect of hydrogen treatment on 4H-SiC Schottky barrier diodes

In this letter, 4H-SiC Schottky barrier diodes (SBDs) with Ti Schottky metal have been subjected to hydrogen treatment in a confined environment of 4% H2 and 96% N2 at 150 °C. The effect of hydrogen treatment on the SBDs electrical characteristics has been investigated by technical computer-aided design simulation (TCAD) and power device analyzer curve tracer. The change of electrical parameters of SBDs measured after hydrogen treatment is studied in detail, and the related degradation mechanism is discussed. It was found that hydrogen treatment affected both the interface region and bulk region of SiC SBDs. After hydrogen treatment, the Schottky barrier increases slightly, the ideal factor (n) decreases slightly, and the interfacial state density (D it) decreases. Hydrogen treatment resulted in a slight reduction in specific on-resistance (R on-sp), which was attributed to the diffusion of H in SBDs. Through TCAD simulation, it is determined that the diffusion of H in the body diode of SBDs is the main reason for the degradation of high forward current and high reverse voltage characteristics.

The study of interface quality in HfO2/Si films probed by second harmonic generation

Time-dependent second harmonic generation (TD-SHG) is an emergent sensitive and non-contact method to qualitatively/quantitively characterize the semiconductor materials, which is closely related to the interfacial electric field. Here, the TD-SHG technique is used to study the interface quality of atomic layer deposited 15 nm HfO2/Si (n-type/p-type) samples, which is compared to the conventional electrical characterization method. A relation between the interface state density and the time constant extracted from TD-SHG is revealed, indicating that TD-SHG is an effective method to evaluate the interface state density. In addition, the dopant type and dopant density can be disclosed by resolving the dynamic process of TD-SHG. The scenario of interfacial electric field between the initial electric field and the laser-induced electric field is proposed to explain the time-dependent evolution of SHG signal. In conclusion, the TD-SHG is a sensitive and non-contact method as well as simple and fast to characterize the semiconductor materials, which may facilitate the semiconductor in-line testing.

The Evaluation of Interface Quality in HfO2 Films Probed by Time-Dependent Second-Harmonic Generation.

Time-dependent second-harmonic generation (TD-SHG) is an emerging sensitive and fast method to qualitatively evaluate the interface quality of the oxide/Si heterostructures, which is closely related to the interfacial electric field. Here, the TD-SHG is used to explore the interface quality of atomic layer deposited HfO2 films on Si substrates. The critical SHG parameters, such as the initial SHG signal and characteristic time constant, are compared with the fixed charge density (Qox) and the interface state density (Dit) extracted from the conventional electrical characterization method. It reveals that the initial SHG signal linearly decreases with the increase in Qox, while Dit is linearly correlated to the characteristic time constant. It verifies that the TD-SHG is a sensitive and fast method, as well as simple and noncontact, for evaluating the interface quality of oxide/Si heterostructures, which may facilitate the in-line semiconductor test.