Thickness Of Interfacial Oxide Layer Research Articles

Enhanced ductility of B4C/Al composites by controlling thickness of interfacial oxide layer through high temperature oxidation of B4C particles

Pre-oxidizing of the B4C particles can regulate the thickness of the interfacial oxide layer between the B4C particles and the Al alloy matrix in the B4C/Al composites by adjusting the oxidation temperature and time. This paper studied the effect of oxidation temperature and time on the oxide layer of the B4C particles, which was oxidized at 500 °C ∼ 650 °C in air quantitatively. Taking the pre-oxidized B4C particles as raw reinforcements, the B4C/Al composites with a volume fraction of 15% were prepared by hot pressed sintering method, and the interfacial microstructure and tensile properties of the composites were discussed. The results show that the amorphous oxide layers with different average thickness are produced at the interface of the composites, which prepared by the B4C particles through different oxidation processes, and the average thickness of the oxide layer has a great influence on the fracture elongation of the B4C/Al composites. When the average thickness of the oxide layer is 9.6 nm, the composites show the highest value of the fracture elongation (4.2%), 50% and 147% higher than that in the composites with the average thickness of 0 and 37.6 nm. By designing the thickness of the interfacial oxide layer, it is expected to realize the regulation of the tensile properties of the B4C/Al composites.

Enhanced Ductility by Controlling Thickness of Interfacial Oxide Layer in B4c/Al Composites

Enhanced Ductility by Controlling Thickness of Interfacial Oxide Layer in B4c/Al Composites

Effects of interfacial oxide layer formed by annealing process on WORM characteristics of Ag/CuxO/SiOx/n+–Si devices

In this paper, we investigate the effects of a SiOx interfacial layer on ON/OFF current ratios, endurance characteristics and read-disturb immunities of Ag/CuxO/SiOx/n+-Si write-once-read-many-times (WORM) memories. The CuxO active layers were prepared using a sol-gel process. After coating CuxO films on n+-Si substrates, the CuxO/n+-Si samples were annealed in air at 400 ℃ and 600 ℃, respectively, to obtain a SiOx interfacial layer at the CuxO/n + -Si interfaces. The 400 ℃-annealed CuxO device shows an ON/OFF current ratio of 104. However, degradation of OFF state current (IOFF) with increasing read-pulse cycles and stress time is observed. For the 600 ℃-annealed CuxO device, stable ON and OFF state currents can be observed both in an endurance test for over 1.2 × 104 read cycles and in a read-disturb test for 2 × 104 s. Moreover, a higher ON/OFF current ratio of 107 is obtained. A rigorous retention test executed at an elevated temperature of 85 ℃ indicates that the data retention time is expected to last for 10 years. The performance improvement of the 600 ℃-annealed CuxO device is due to an increase in the thickness of the SiOx interfacial oxide layer. The mechanism for the influence of the interfacial layer on memory performance is investigated and illustrated. The OFF state current of the memory is limited by hopping and trap-assisted tunneling transport in the SiOx interfacial layer. In the ON state, conductive paths in the device cause that the carriers can easily migrate by Ohmic and space charge limited conduction.

Corrosion Mitigation by Photocatalytic Effect of TiO2 Coating on Low Carbon Steel

In this study, the photoelectrochemical behavior of the carbon steel with TiO2 coating by sol-gel method were investigated to preventing or minimizing the atmospheric corrosion. Various oxide structure of carbon steel and the TiO2 annealing process were also investigated in this study.The crystallinity of TiO2 was analyzed with grazing incident X-ray diffraction (GIXRD) and the interfacial oxide layer composition and thickness were analyzed via the Raman spectroscopy and SEM, respectively. Potential dynamic analyses and open circuit potential (OCP) measurement were carried out under a designated solution to evaluate the corrosion mitigation of the TiO2 coated carbon steel with or without UV illumination. These results indicated that the TiO2 treatment with UV illumination would effectively reduce the carbon steel corrosion rate in atmospheric environments.

Corrosion Mitigation By Photocatalytic Effect of TiO2 Coating on Low Carbon Steel

Titanium dioxide (TiO2) is one of the most commonly used photocatalyst at the field of environmental remediation and energy applications. TiO2 is an n-type semiconductor that can be excited by photon irradiation to generate electron-hole pairs in its space charge layer under UV illumination. The excited electrons in the conduction band are then transferred to the metal surface, leading to decrease in both the corrosion potential and the oxidation reaction rate of the metal.In this study, the photoelectrochemical behavior of the carbon steel with TiO2 coating by sol-gel method were investigated to preventing or minimizing the atmospheric corrosion. Various oxide structure of carbon steel and the TiO2 annealing process were also investigated in this study.The crystallinity of TiO2 was analyzed with grazing incident X-ray diffraction (GIXRD) and the interfacial oxide layer composition and thickness were analyzed via the Raman spectroscopy and SEM, respectively. Potential dynamic analyses and open circuit potential (OCP) measurement were carried out under a designated solution to evaluate the corrosion mitigation of the TiO2 coated carbon steel with or without UV illumination. These results indicated that the TiO2 treatment with UV illumination would effectively reduce the carbon steel corrosion rate in atmospheric environments.

Influence of Ta2O5 Interfacial Oxide Layer Thickness on Electronic Parameters of Al/Ta2O5/p-Si/Al Heterostructure

We describe the impact of Ta2O5 interfacial oxide layer thickness (ranging from 100-350 nm) on electrical and structural properties of Al/Ta2O5/p-Si/Al Metal-Insulator-Semiconductor (MIS) Schottky barrier diodes using RF magnetron sputtering. We studied the Schottky barrier device parameters such as ideality factor, barrier height and series resistance and are evaluated from current-voltage (I-V) measurements. The barrier height and ideality factor values are significantly varying with Ta2O5 oxide layer thickness and found to be 0.58 eV, 2.35, 0.71 eV, 2.10 and 0.78 eV, 1.87 for 20, 40 and 60 nm, respectively. It was noticed that the calculated barrier height and ideality values for this prepared Al/Ta2O5/p-Si/Al MIS Schottky barrier diode were greatly improved than those conventional metal-semiconductor (MS) Schottky diodes. The XRD studies revealed that the 100-nm thickness film exhibited poor crystallinity whereas 200 and 350 nm thickness films showed improved crystallinity with orthorhombic phase of β-Ta2O5. The presence of this orthorhombic phase of β-Ta2O5 is confirmed with FTIR studies. To explore the structural transformations in Ta2O5 films with varying thicknesses, Raman spectroscopy was utilized. In addition, the improvement in Schottky diode parameters was correlated with the enhanced crystallinity noticed in XRD studies.

Effect of atomic-arrangement matching on La2O3/Ge heterostructures for epitaxial high-k-gate-stacks

We demonstrate a high-quality La2O3 layer on germanium (Ge) as an epitaxial high-k-gate-insulator, where there is an atomic-arrangement matching condition between La2O3(001) and Ge(111). Structural analyses reveal that (001)-oriented La2O3 layers were grown epitaxially only when we used Ge(111) despite low growth temperatures less than 300 °C. The permittivity (k) of the La2O3 layer is roughly estimated to be ∼19 from capacitance-voltage (C-V) analyses in Au/La2O3/Ge structures after post-metallization-annealing treatments, although the C-V curve indicates the presence of carrier traps near the interface. By using X-ray photoelectron spectroscopy analyses, we find that only Ge–O–La bonds are formed at the interface, and the thickness of the equivalent interfacial Ge oxide layer is much smaller than that of GeO2 monolayer. We discuss a model of the interfacial structure between La2O3 and Ge(111) and comment on the C-V characteristics.

Ionizing radiation effects on electrical and reliability characteristics of sputtered Ta2O5/Si interface

This paper describes the effect of ionizing radiation on the interface properties of Al/Ta2O5/Si metal oxide semiconductor (MOS) capacitors using capacitance–voltage (C–V) and current–voltage (I–V) characteristics. The devices were irradiated with X-rays at different doses ranging from 100 rad to 1 Mrad. The leakage behavior, which is an important parameter for memory applications of Al/Ta2O5/Si MOS capacitors, along with interface properties such as effective oxide charges and interface trap density with and without irradiation has been investigated. Lower accumulation capacitance and shift in flat band voltage toward negative value were observed in annealed devices after exposure to radiation. The increase in interfacial oxide layer thickness after irradiation was confirmed by Rutherford Back Scattering measurement. The effect of post-deposition annealing on the electrical behavior of Ta2O5 MOS capacitors was also investigated. Improved electrical and interface properties were obtained for samples deposited in N2 ambient. The density of interface trap states (Dit) at Ta2O5/Si interface sputtered in pure argon ambient was higher compared to samples reactively sputtered in nitrogen-containing plasma. Our results show that reactive sputtering in nitrogen-containing plasma is a promising approach to improve the radiation hardness of Ta2O5/Si MOS devices.

Air-stable high-efficiency solar cells with dry-transferred single-walled carbon nanotube films

By using the excellent optical and electrical properties of pristine SWNTs with long bundle lengths, we present single-walled carbon nanotube–silicon (SWNT/Si) solar cells of 11% power conversion efficiency (PCE), prepared without doping. The PCEs of the fabricated solar cells even increased slightly after 10 months of exposure to ambient conditions, without any external protection. The open-circuit voltage of the SWNT/Si solar cells under low light intensities, down to 10 mW cm−2, demonstrated the characteristics of the ideal p–n junction model. The mechanism was discussed, taking into account the effect of varying the interfacial oxide layer thickness between the SWNTs and Si on the solar cell’s performance. The high efficiency and stability demonstrated in this study make SWNT/Si solar cells one of practical choices for next generation energy system.

Formation of Large-Grain Ge(111) Films on Insulator by Gold-Induced Layer-Exchange Crystallization at Low Temperature

A formation technique of orientation-controlled large-grain (< 10 μm) Ge crystals on insulator at low temperature ({less than or equal to} 350oC) has been investigated to realize advanced flexible electronics. Previously, we proposed a gold-induced crystallization technique, and demonstrated low temperature crystallization (250oC) of Ge on insulator. In the present study, we intentionally inserted thin Al2O3 layers between gold and a-Ge layer, to control crystal nucleation. Consequently, (111)-oriented large-grain (< 20 μm) Ge crystals are obtained at 350oC by optimizing interfacial oxide layer thickness. It is speculated that this phenomena is attributed to suppression of random bulk nucleation of Ge in Au films and resultant dominance of interfacial nucleation at Ge/SiO2 interfaces.

Insight Into N/PBTI Mechanisms in Sub-1-nm-EOT Devices

New insights into the negative/positive bias temperature instability (N/PBTI) degradation mechanisms in the sub-1-nm equivalent oxide thickness (EOT) regime are presented in this paper. The electric field requirements suggested by the International Roadmap for Semiconductors demand an even higher value in the sub-1-nm-EOT regime, which is practically difficult to meet with the increased hole trapping mechanism involved. Thus, a fixed electric field target of 5 MV/cm is considered as well here, which might be a reasonable target to achieve. The sub-1-nm-EOT devices in this paper are obtained by adopting a thinner TiN metal gate inducing Si in-diffusion and reducing the interfacial oxide layer thickness. NBTI degradation follows an isoelectric field model in over an EOT of 1 nm due to the degradation mechanism of Si/SiO_2 interface state generation combined with a hole trapping mechanism. However, in the sub-1-nm-EOT regime, the probability of hole trapping into the gate dielectric increases, and it is strongly dependent on the thickness of the interfacial oxide layer. Several experimental proofs of this increased bulk defect effect are shown in this paper. In addition, the bulk defect affecting NBTI is shown to be mostly a preexisting defect, although the permanently generated defects are relatively higher in sub-1-nm-EOT devices. Therefore, NBTI in the sub-1-nm-EOT regime faces the lifetime limit by both electric field dependence and increased degradation by increased hole trapping into bulk defects. Further, we found a minimum interfacial layer thickness of 0.4 nm that is required to prevent the accelerated NBTI degradation by increased direct tunneling. The main degradation mechanism of PBTI in sub-1-nm EOT is the electron trapping into bulk defects, which is the same as in over 1-nm-EOT devices. This enables us to modulate the bulk defect energetic locations in the oxide and to improve PBTI.

Impact of Precursor Chemistry and Process Conditions on the Scalability of ALD HfO2 Gate Dielectrics

The downscaling of high-/metal gate transistor devices requires thin-film deposition processes that deliver not only an outstanding high- oxide quality, but also a strict interfacial oxide thickness control in the sub-1 nm thickness range. To study the impact of atomic layer deposition (ALD) process conditions and chemistry on the quality and interfacial oxide thickness, we have used tetrakis[ethylmethylamino]hafnium (TEMAH) as a metal precursor and and as oxidants. The deposition temperature ranged from 285 up to , where TEMAH decomposition plays a role in the growth mechanism. Physical characterization and Pt dot capacitor devices have been used to study the impact of the oxidant and process conditions on the equivalent oxide thickness and gate leakage current of 2–4 nm thin films. By combining X-ray reflectometry and ellipsometry, we evaluated the Si/high- interfacial oxide layer thickness. Time-of-flight secondary-ion mass spectroscopy was used to determine the C impurity levels. Both the interfacial oxide layer thickness and the C impurity level in the stacks are strongly dependent on the oxidant. The temperature dependence of the C impurity level is opposite for and . Furthermore, regrowth was found for the process.

Simulation of Gate Tunneling Current in Metal–Insulator–Metal Capacitor with Multi layer High-κ Dielectric Stack Using the Non-equilibrium Green's Function Formalism

In this paper, we present a one-dimensional (1D) simulation study of gate leakage current in metal–insulator–metal (MIM) capacitors using the non-equilibrium Green's function (NEGF) formalism. The simulation code has been used to calculate tunneling transmission probability and tunneling current through multi layer gate stacks with various high-permittivity (high-κ) dielectric materials. Quantum–mechanical (NEGF) results are compared with the results of Wentzell–Kramers–Brillouin (WKB) classical approximation for different equivalent oxide thicknesses (EOTs) in numerous gate stacks such as single-SiO2-layer devices or double-layer (SiO2 + high-κ) structures. Quantum simulation shows that the conduction band offset between oxides induces wave-function reflections against barrier discontinuities, which significantly affect the transport of electrons and thus gate leakage current, particularly in double-layer high-κ gate dielectric stacks. The study of various high-κ dielectrics also shows that gate leakage current strongly depends not only on material properties such as dielectric constant, effective mass, and conduction band offset, but also on interfacial oxide (SiO2) layer thickness.

Low frequency noise analysis in HfO2∕SiO2 gate oxide fully depleted silicon on insulator transistors

In this article, low frequency noise in HfO2∕SiO2 metal-oxide-semiconductor devices with TiN metal gate on fully depleted silicon on insulator technology is analyzed. The drain current noise in linear regime is presented to determine the noise sources in such devices. The impact of different gate stack parameters such as interfacial oxide layer thickness, high-κ layer thickness, and the oxide deposit techniques on the noise level is studied.

A quantum mechanical mobility model for scaled NMOS transistors with ultra-thin high-K dielectrics and metal gate electrodes

A quantum mechanical model of electron mobility for scaled NMOS transistors with ultra-thin SiO2/HfO2 dielectrics (effective oxide thickness is less than 1nm) and metal gate electrode is presented in this paper. The inversion layer carrier density is calculated quantum mechanically due to the consideration of high transverse electric field created in the transistor channel. The mobility model includes: (1) Coulomb scattering effect arising from the scattering centers at the semiconductor–dielectric interface, fixed charges in the high-K film and bulk impurities, and (2) surface roughness effect associated with the semiconductor–dielectric interface. The model predicts the electron mobility in MOS transistors will increase with continuous dielectric layer scaling and a fixed volume trap density assumption in high-K film. The Coulomb scattering mobility dependence on the interface trap density, fixed charges in the high-K film, interfacial oxide layer thickness and high-K film thickness is demonstrated in the paper.

Influence of interfacial oxide layer thickness on conversion efficiency of SnO2/SiO2/Si(N) Solar Cells

Influence of interfacial oxide layer thickness on conversion efficiency of SnO2/SiO2/Si(N) Solar Cells

Effects of interfacial oxide layer thickness and interface states on conversion efficiency of SnO2/ SiO2/Si(N) solar cells

The interfacial layer in a Schottky barrier solar cell plays an important role in determining the short circuit current, open circuit voltage, fill factor and efficiency of the cell. In this paper, we studied the effects of interfacial oxide layer thickness, interface state density and Ф0 (the level above the valence band to which surface states are filled in isolated semiconductor) on the open circuit voltage and efficiency of the SnO2/SiO2/Si (N) solar cells. From our analysis, we have found that the efficiency of the cell increases at first with the interfacial oxide layer thickness δ, and after acquiring a maximum value falls with a further increase of δ. We have optimized the interfacial layer thickness for maximum efficiency. The solar cell current–voltage characteristics under illumination are also computed for different values of insulator thickness δ. The results obtained by numerical simulation using Matlab programs are presented and discussed. The SnO2/SiO2/Si (N) solar cells, in which the interfacial oxide layer thickness is optimized to 21 A°, have an average open circuit voltage of 0.62 V and a short circuit current of 36 mA/cm2. The calculated conversion efficiency of the cells can be as high as 17.5 %.

Temperature and frequency dependent electrical and dielectric properties of Al/SiO 2/p-Si (MOS) structure

The electrical and dielectric properties of Al/SiO 2/p-Si (MOS) structures were studied in the frequency range 10 kHz–10 MHz and in the temperature range 295–400 K. The interfacial oxide layer thickness of 320 Å between metal and semiconductor was calculated from the measurement of the oxide capacitance in the strong accumulation region. The frequency and temperature dependence of dielectric constant ( ε′), dielectric loss ( ε″), dielectric loss tangent (tan δ) and the ac electrical conductivity ( σ ac) are studied for Al/SiO 2/p-Si (MOS) structure. The electrical and dielectric properties of MOS structure were calculated from C– V and G– V measurements. Experimental results show that the ε′ and ε″ are found to decrease with increasing frequency while σ ac is increased, and ε′, ε″, tan δ and σ ac increase with increasing temperature. The values of ε′, ε″ and tan δ at 100 kHz were found to be 2.76, 0.17 and 0.06, respectively. The interfacial polarization can be more easily occurred at low frequencies, and the number of interface state density between Si/SiO 2 interface, consequently, contributes to the improvement of dielectric properties of Al/SiO 2/p-Si (MOS) structure. Also, the effects of interface state density ( N ss) and series resistance ( R s) of the sample on C– V characteristics are investigated. It was found that both capacitance C and conductance G were quite sensitive to temperature and frequency at relatively high temperatures and low frequencies, and the N ss and R s decreased with increasing temperature. This is behavior attributed to the thermal restructuring and reordering of the interface. The C– V and G/ ω– V characteristics confirmed that the N ss, R s and thickness of insulator layer ( δ) are important parameters that strongly influence both the electrical and dielectric parameters and conductivity in MOS structures.

Microstructure and electrical properties of Al 2O 3–ZrO 2 composite films for gate dielectric applications

Al 2O 3–ZrO 2 composite films were fabricated on Si by ultrahigh vacuum electron-beam coevaporation. The crystallization temperature, surface morphology, structural characteristics and electrical properties of the annealed films are investigated. Our results indicate that the amorphous and mixed structure is maintained up to an annealing temperature of 900 °C, which is much higher than that of pure ZrO 2 film, and the interfacial oxide layer thickness does not increase after annealing at 900 °C. However, a portion of the Al 2O 3–ZrO 2 film becomes polycrystalline after 1000 °C annealing and interfacial broadening is observed. Possible explanations are given to explain our observations. A dielectric constant of 20.1 is calculated from the 900 °C-annealed ZrO 2–Al 2O 3 film based on high-frequency capacitance–voltage measurements. This dielectric characteristic shows an equivalent oxide thickness (EOT) as low as 1.94 nm. An extremely low leakage current density of ∼2×10 −7 A/cm 2 at a gate voltage of 1 V and low interface state density are also observed in the dielectric film.

The Effect of Device Parameters on the Emitter Transit Time of a PET

Polysilicon Emitter Transistors (PETs) which are now being widely used in high speed bipolar circuits because of their extremely low emitter transit time τE, have broken-up interfacial oxide layer due to annealing process which they undergo. The effect of oxide layer break-up at the mono-poly interface of the emitter region of a PET on τE is studied here. The effect of doping profile, peak doping concentration, thickness of interfacial oxide layer on τE is studied also. Exponential doping distribution alongwith concentration dependent bandgap narrowing effect and concentration dependent diffusion constant in the monosilicon emitter region are considered.