Interfacial Native Oxide Layer Research Articles

Photoswitching effect of graphene photogated diodes with interfacial layers

Graphene/semiconductor heterojunction-based photodetectors are expected to achieve high performance in various wavelength regions. Graphene photogated diodes (GPDs) based on such heterojunctions are promising for the fabrication of high-performance photodetectors, which cannot be achieved using conventional technologies. However, their action mechanism has not yet been theoretically demonstrated. In this study, we investigated the mechanism of GPDs with and without an interfacial layer. We demonstrated that the thin interfacial native oxide layer is responsible for the reduction in the Fermi level induced by photogating, which is similar to “photoswitching.” This effect induces an extraordinarily large output current in GPDs with a barrier layer.

Determining the potential barrier presented by the interfacial layer from the temperature induced I–V characteristics in Al/p-Si Structure with native oxide layer

The temperature induced current-voltage (I–V-T) characteristics of the Al/SiO2/p-Si diodes with the interfacial native oxide layer were experimentally investigated in present our study. The values of 24.35 and 1.02 eV for the tunneling factor (aδχ) and the potential barrier presented by the interfacial layer (χ) were determined for the Al/SiO2/p-Si metal-insulator-semiconductor (MIS) diode. The χ value obtained from the forward bias I–V-T characteristics of the SiO2/p-Si diode is a crucial result according to those from only room temperature I–V curves in literature studies. Furthermore, the temperature dependence of the apparent barrier heights of the forward bias I–V-T characteristics displayed a Gaussian distribution (GD) of inhomogeneous barrier heights (BHs). Thus, the standard deviation values of σ1s0=147.65 mV for high temperature range and σ2s0=83.66 mV for low temperature range were obtained from the GD plot of the BHs (the apparent BH versus (2kT)−1 plot). Again, for the mean barrier height Φ‾b0 from the GD plot of the BHs, the values of 1.16 eV and 0.70 eV were obtained from the high temperature region and low temperature region, respectively. Furthermore, the Richardson constant values of 54.66 and 58.42 A/K2cm2 from these temperature regions are approximately 1.70 times higher than the theoretical value of 32 A/K2cm2 of the p-type Si semiconductor.

Investigation of Barrier Inhomogeneities and Electronic Transport on Al-Foil/p-Type-4H-SiC Schottky Barrier Diodes Using Diffusion Welding

The diffusion welding (DW) is a comprehensive mechanism that can be extensively used to develop silicon carbide (SiC) Schottky rectifiers as a cheaper alternative to existing mainstream contact forming technologies. In this work, the Schottky barrier diode (SBD) fabricated by depositing Al-Foil on the p-type 4H-SiC substrate with a novel technology; DW. The electrical properties of physically fabricated Al-Foil/4H-SiC SBD have been investigated. The current-voltage (I-V) and capacitance-voltage (C-V) characteristics based on the thermionic emission model in the temperature range (300 K–450 K) are investigated. It has been found that the ideality factor and barrier heights of identically manufactured Al-Foil/p-type-4H-SiC SBDs showing distinct deviation in their electrical characteristics. An improvement in the ideality factor of Al-Foil/p-type-4H-SiC SBD has been noticed with an increase in temperature. An increase in barrier height in fabricated SBD is also observed with an increase in temperature. We also found that these increases in barrier height, improve ideality factors and abnormalities in their electrical characteristics are due to structural defects initiation, discrete energy level formation, interfacial native oxide layer formation, inhomogenous doping profile distribution and tunneling current formation at the SiC sufaces.

The Effect of Measurement Frequency on Dielectric Characteristics in Al/P-Si Structures with Interfacial Native Oxide Layer

Deneysel olarak karakteristiklerini belirlemeye çalıştığımız arayüzey doğal oksit tabakalı Al/p-Si/Al metal/oksit tabaka/yarıiletken veya diğer bir adıyla metal/yalıtkan tabaka/yarıiletken (MIS) yapılar elde edilmiştir. Bu yapı için taban malzeme olarak 1-10 Ω-cm özdirençli p-Si yarıiletkeni kullanılmıştır. Arka yüzeyi omik kontaklı olan bu p-Si dilim, laboratuvar ortamında ön parlak yüzeyi üzerinde doğal oksit SiO2 tabakasının oluşması sağlanmıştır. Diyot parametrelerinin elde edilmesi için, yaygın olarak kullanılan, farklı frekanslarda kapasite-gerilim (C-V) kondüktans-gerilim (G-V) ölçümlerinden Al/p-Si MIS yapının deneysel frekans admittans karakteristikleri elde edilmiştir. Bu karakteristiklerinden, gerçek 𝜀′ ve sanal dielektrik 𝜀′′ sabiti, loss-tanjant (𝜀′′/𝜀′), gerçek 𝑀′ ve sanal elektriksel modulüs 𝑀′′ ve ac iletkenliği 𝜎𝑎𝑐 gibi parametreleri hesaplanmış ve gerekli grafikler çizimleri ve yorumları yapılmıştır.

Effect of measurement frequency on admittance characteristics in Al/p-Si structures with interfacial native oxide layer

Al/p-Si/Al diodes with interfacial native oxide layer were formed. Their frequency induced admittance-voltage measurements were made. The frequency-dependent density distribution of interface states has been determined from the corrected characteristics by considering the series resistance effect which masks the interface trap loss. The majority carrier density corresponding to the depletion and inversion parts of the C-2-V curve, was determined 1.82 x 1014 and 4.48 x 1014 cm-3 at 1000 kHz, respectively. The fact that the carrier density obtained from the inversion part of the plot is higher than that obtained from the depletion part can be related to the increase in the density of negative space charge in the depletion region.The value of was determined as 0.95 eV from the same plot. Interface state density decreased from 4.31 x 1012 eV-1cm-2 at 100 kHz to 7.30 x 1011 eV-1 cm-2 at 1000 kHz, because the interface charges do not follow the ac signal and do not contribute to capacitance values in high frequencies.

Enhanced load transfer by designing mechanical interfacial bonding in carbon nanotube reinforced aluminum composites

The interfacial native oxide layer always acts as barriers preventing effective interfacial bonding and load transfer in carbon nanotube reinforced aluminum (CNT/Al) composites. In this work, annealing-controlled reaction between the interfacial native oxide layer and Mg element was attempted to improve interfacial bonding in CNT/AlMg composite, and mechanical interfacial bonding featured with direct CNT-Al contact and well-reserved CNTs was achieved in the 1 h annealed composite. For the 2 h annealed composite, chemical interfacial bonding featured with interfacial aluminum carbide (Al4C3) was established due to progressive interfacial reaction. Further tensile tests and numerical analysis revealed that, owing to barrier-free load path and increased interfacial friction stress, the mechanical interfacial bonding significantly enhanced CNT load transfer effect from 30.9 MPa to 59.4 MPa, which was close to shear-lag model prediction of 59.9 MPa. While, the chemical interfacial bonding led to a combined strengthening effect of 58.8 MPa from CNT-Al4C3 hybrid as a comprised outcome of Al4C3 strengthening and CNT damage. Thus, the design of mechanical interfacial bonding should be a superior strategy for improving interfacial bonding and enhancing mechanical performance in CNT/Al composites, considering its effective protection of CNT structure integrity and suppressed formation of hydrolysable Al4C3 phase.

Forward-bias diode parameters, electronic noise, and photoresponse of graphene/silicon Schottky junctions with an interfacial native oxide layer

Metal-semiconductor Schottky junction devices composed of chemical vapor deposition grown monolayer graphene on p-type silicon substrates are fabricated and characterized. Important diode parameters, such as the Schottky barrier height, ideality factor, and series resistance, are extracted from forward bias current-voltage characteristics using a previously established method modified to take into account the interfacial native oxide layer present at the graphene/silicon junction. It is found that the ideality factor can be substantially increased by the presence of the interfacial oxide layer. Furthermore, low frequency noise of graphene/silicon Schottky junctions under both forward and reverse bias is characterized. The noise is found to be 1/f dominated and the shot noise contribution is found to be negligible. The dependence of the 1/f noise on the forward and reverse current is also investigated. Finally, the photoresponse of graphene/silicon Schottky junctions is studied. The devices exhibit a peak responsivity of around 0.13 A/W and an external quantum efficiency higher than 25%. From the photoresponse and noise measurements, the bandwidth is extracted to be ∼1 kHz and the normalized detectivity is calculated to be 1.2×109 cm Hz1/2 W−1. These results provide important insights for the future integration of graphene with silicon device technology.

Hydrostatic pressure dependence of interface state density of Cd/n-type GaAs Schottky barrier diodes

Abstract The interface state density obtained from current–voltage (I–V) characteristics of Cd/n-type GaAs Schottky barrier diodes (SBDs) at room temperature under hydrostatic pressure was investigated. SBD parameters such as ideality factor (n), series resistance (Rs), and barrier height (φb), were obtained from I–V measurements using Cheung's method. The diode parameters, such as ideality factor, series resistance, and barrier heights, were found in the range of 1.464–1.474, 0.995–4.359 kΩ and 0.739–0.777 eV, respectively, with sweeping pressure. The diode shows non-ideal I–V behaviors with an ideality factor greater than unity. Additionally, the energy distribution of interface state density was determined from the forward bias I–V characteristics by taking into account the bias dependence of the effective barrier height. The results have shown that the presence of the interfacial native oxide layer between the metal and the semiconductor seriously affects interface state density under hydrostatic pressure.

Linear correlation between barrier heights and ideality factors of Sn/n-Si schottky diodes with and without the interfacial native oxide layer

Abstract We have prepared the Sn/n-Si Schottky barrier diodes (SBDs) with and without the native oxide layer. The diodes with or without the native oxide layer have been identically fabricated on the same Si wafer. The effective Schottky barrier heights (SBHs) and ideality factors of the SBDs have been obtained from the current–voltage ( I–V ) characteristics. Our purpose is experimentally to show whether or not the effective SBHs and ideality factors of the identically fabricated diodes differ from diode to diode. The SBH Φ b for the Sn/n-Si SBDs without the interfacial oxide layer (the reference sample) has ranged from 0.670 to 0.599 eV, and ideality factor n from 1.349 to 2.558. Φ b value for the Sn/n-Si SBDs with the interfacial oxide layer (metal–interfacial layer–semiconductor (MIS) sample) has ranged from 0.647 to 0.560 eV, and ideality factor n value from 1.381 to 2.777. Among identically prepared diodes, higher ideality factors have been found to accompany lower SBHs. Furthermore, the extrapolations of the linear plot the experimental barrier heights (BHs) versus ideality factors to the ideality factor have given the laterally homogeneous BHs of approximately 0.683 and 0.656 eV for the reference and MIS Sn/n-Si SBDs.

Electrical and structural characteristics of yttrium oxide films deposited by rf-magnetron sputtering on n-Si

Yttrium oxide dielectric films were grown by rf-magnetron sputtering on n-Si(100) substrates and annealed in vacuum at temperatures ranging from 400 to 600 °C. The main aim of this work was the investigation of the interface between the dielectric film and silicon. Both structural (x-ray diffraction and transmission electron microscopy) and electrical characterization were used for this purpose. No structural change was observed on the interfacial native oxide layer after annealing at 600 °C for 1 h. Metal–oxide–semiconductor structures defined by the evaporation of Al electrodes show low leakage currents, moderate dielectric constant (around 14), and high densities of positive charges trapped in the oxide. Hysteresis effects in capacitance–voltage (C–V) curves reduce with the annealing temperature. Another interesting observation is the parallel shift of the C–V curves along the voltage axis with frequency. An insulator trap model is proposed to explain this behavior.

Time dependent ballistic electron emission microscopy studies of a Au/(100)GaAs interface with a native oxide diffusion barrier

Ballistic electron emission microscopy (BEEM) has been used to investigate the effects of a thin interfacial native oxide layer on the electronic properties and stability of a Au/(100) n-GaAs contact as a function of time. The oxide had no effect on the electronic band structure at the interface measured with BEEM, as compared to similar contacts without a diffusion barrier. In addition, the oxide greatly enhanced the electrical homogeneity of the interface and prolonged the ability of the diode to transmit ballistic electrons to more than 35 days.

Morphology of the silicon implanted interface of a polysilicon/single crystal silicon structure

Employing high resolution TEM, it was shown that the morphological change of polysilicon/single crystal silicon (poly-Si/Si) interface induced by silicon implantation and subsequent annealing at 900° C for 30 min greatly depended on implantation dose. After annealing, the interfacial native oxide layer implanted with 3 × 10 15 cm −2 Si was broken up into a discontinuous layer, which still remained at the interface. For the interface implanted with 1 × 10 16 cm −2 Si, however, “oxide balls” of 10–20 Å diameter were formed and the distribution of the oxide balls was broadened (about 100 Å width). SIMS analysis revealed that for an interface implanted with 1 × 10 16 cm −2 Si, the distribution of oxygen atoms near the interface broadened by the implantation and that it slightly narrowed after annealing. These morphological changes influenced the contact resistance of poly-Si/Si interface, especially in a sub-half-μm region.

Schottky and Ohmic Au contacts on GaAs: Microscopic and electrical investigation

We report here a systematic study which uses electrical device measurements and transmission electron microscopy (TEM) methods to investigate the electrical, morphological, and structural properties of Au/GaAs Schottky diodes. The electrical characteristics of Au diodes formed on atomically clean and air-exposed GaAs(110) surfaces are found to change from rectifying to Ohmic behavior after annealing above the Au–Ga eutectic temperature (360 °C). This change is shown to be due to an Ohmic-like contact at the periphery of the device. TEM studies of these structures indicate that the Ohmic peripheral current pathway can be correlated with the formation of near surface Ga-rich Au crystallites at the diode circumference upon annealing. Further evidence of the correlation of the Ohmic electrical characteristics with the morphology of the periphery comes from data which indicate that the removal of these Au crystallites by mesa etching is also accompanied with the elimination of the Ohmic current. The morphology of the overlayer was found to depend strongly on annealing and surface treatment. TEM indicates that the interface is flat and abrupt for all unannealed diodes, as well as for annealed diodes formed on atomically clean surfaces. For annealed diodes formed on the air-exposed surfaces, the metal–semiconductor interface contains large metallic protrusions extending up to several hundred angstroms into the semiconductor. For comparison to practical structures, the morphology of annealed diodes formed using typical commercial processing technology [i.e., formed on chemically prepared (100) surfaces annealed in forming gas] was also investigated using TEM. The interface for these structures is more complex than interfaces formed on the atomically clean and air-exposed cleaved (110) surfaces. Evidence that Au diffuses through the interfacial native oxide layer and forms islands in intimate contact with the semiconductor was found.

Evaluation of aluminum-GaAs Schottky barriers using Norde’s modified current-voltage analysis

Schottky barrier heights for aluminum-(100) GaAs diodes with and without an interfacial native oxide layer have been evaluated using Norde’s method of current-voltage analysis. Barrier heights determined by Norde’s method on sputter-annealed, oxide-free substrates are systematically lower (0.53–0.59 eV) than values determined by photoresponse measurements (0.78±0.03 eV). Anomalous structure in the form of a second minimum was observed in the Norde plots for unsputtered substrates on which a thin native oxide was present. The barrier heights obtained from the second minimum observed at high forward bias (∼0.75 V) were 0.90–0.95 eV, whereas photoresponse measurements indicated barriers of 1.00±0.01 eV.