Interconnects In 3D ICs Research Articles

New Computational Methods for Enhancing Reliability Testing of Interconnects in 3D ICs: Advanced Algorithms, Optimization Techniques, and Real-World Applications

New Computational Methods for Enhancing Reliability Testing of Interconnects in 3D ICs: Advanced Algorithms, Optimization Techniques, and Real-World Applications

Novel BIST Solution to Test the TSV Interconnects in 3D Stacked IC’s

This paper proposes a novel technique of TSV BIST repair that targets the design yield and various test challenges of three-dimensional integrated circuits (3D stacked ICs). The proposed methodology is efficient to cover the various faults during the fabrication, the interconnect breakages, shorts, bridges, void formation, thermal and physical stress, etc., during the TSV fabrication and stacking of 3D ICs. The repair mechanism provides a redundancy feature to replace the failing TSVs with spare TSVs in the design. It provides a significant impact on yield compared to the standard TSV testing approach. Further analysis was performed on different stacked levels of 3D ICs, and the results were compared with the existing industrial methods in terms of the yield and test time parameters. The proposed mechanism showed a significant improvement of 12.5% in the yield and 17.5% in the test time and also recovered all defective chips efficiently.

(Invited) Towards the Physical Reliability of 3D-Integrated Systems: Broadband Dielectric Spectroscopic (BDS) Studies of Material Evolution and Reliability in Integrated Systems

In this paper, we present an overview of our current research focus in developing non-destructive metrology for monitoring reliability issues in 3D- integrated electronic systems. We introduce a suite of non-destructive metrologies that can serve as early warning monitors for reliability issues. These Broadband Dielectric Spectroscopic (BDS) techniques are based on the application of high frequency microwaves (up to 40 GHz) to devices under various external stress, to probe impedance changes due to material and structural changes in integrated circuits. We illustrate the capabilities of the techniques with four case studies of potential reliability issues in 3D-IC interconnects.

Application of Broadband Microwave Metrology to Emerging Integrated Circuit Device Reliability Analyses

Metrology is needed to characterize structure and composition in emerging integrated circuits at the nano-scale. Interconnect technology has been identified as the largest single factor limiting both performance, power, and reliability of emerging devices. The artifacts of interest may be exposed or embedded and may occur at any stage of device fabrication. We are particularly interested in metrology for the accurate understanding and quantification of the reliability issues associated with interconnect metallization in emerging nanoelectronic devices. In this regard, we have developed a suite of broadband microwave (RF)-based metrology techniques to non-destructively identify, measure, and characterize performance-limiting defects in emerging nanoelectronic devices. These RF based metrology tools offer several advantages over the traditional techniques and are uniquely suitable for studying the kinds of problems we are interested in. For example, the traditional low-frequency resistance (RDC) measurements, commonly used for electromigration, are based on changes in the resistance of conductive pathways. So long as there are contiguous electrical paths, the devices under test will not fail the RDC test. In contrast, changes in RF insertion losses offer early prognostics. In this talk, we describe the application of a suite of broadband microwave-based techniques to the interconnect reliability assessment of integrated circuits. We discuss how microwave propagation characteristics have been used to study the impact of thermal aging on phenomena such as stress-induced failures, electromigration, and corrosion of the interconnects in 3D-ICs. We will also compare the mechanistic insights obtained from the traditional resistance increases in low-frequency direct current to those from high-frequency measurements.

A Design for Testability of Open Defects at Interconnects in 3D Stacked ICs

A Design for Testability of Open Defects at Interconnects in 3D Stacked ICs

Yield Enhancement of Face-to-Face Cu–Cu Bonding With Dual-Mode Transceivers in 3DICs

When more than one dies are stacked vertically in 3-D integrated circuits (3DICs), the overall system yield degrades significantly. While each die can be tested before stacking, failures in 3DIC interconnects could jeopardize the entire system. In this paper, a dual-mode transceiver is proposed as a built-in-self-test/repair solution to improve the yield of direct face-to-face copper thermocompression bonding (Cu–Cu bonding). The proposed transceiver could improve the Cu–Cu bonding-based interconnect reliability with the introduction of two operation modes: the ohmic mode when Cu–Cu bonding presents low resistance and the capacitive coupling mode when Cu–Cu bonding is showing any sign of failure with high resistance at the bonding interface. Such mode sensing is self-contained in the transceiver itself with the help of the proposed resistance sensor. In this paper, we discuss the modeling of Cu–Cu bonding and the proposed transceiver design with power, latency, jitter, and crosstalk simulations followed by the design guideline for the practical implementation with yield analysis.

FT-Z-OE: A Fault Tolerant and Low Overhead Routing Algorithm on TSV-based 3D Network on Chip Links

dimensional Network-On-Chips (3D NOC) are the most efficient communication structures for complex multi-processor System-On-Chips (SOC). Such structures utilize short vertical interconnects in 3D ICs together with scalability of NOC to improve performance of communications in SOCs. By scaling trends in 3D integration, probability of fault occurrence increases that leads to low yield of links, especially TSV-based vertical links in 3D NOCs. In this paper, FT-Z-OE (Fault Tolerant Z Odd-Even) routing, a distributed routing to tolerate permanent faults on vertical links of 3D NOCs is proposed. FT-Z-OE is designed to have low overhead because of no need to any routing table or global information of faults in the network. The proposed routing is evaluated using a cycle-accurate network simulator and compared to planar-adaptive routing for a 3D mesh-based network. It is shown that FT-Z-OE significantly outperforms planar-adaptive in the terms of latency and throughput under synthetic traffic patterns.

Integration of CNTs in 3D-IC interconnects: a non-destructive approach for the precise characterization and elucidation of interfacial properties

Growth of CNT bundles on Cu-metal lines through oxide vias and the precise estimation of Cu–CNT contact resistance.

(Invited) Microwave-Based Metrology Platform Development: Application of Broad-Band RF Metrology to Integrated Circuit Reliability Analyses

In this paper we describe the development of a suite of techniques, based on the application of high frequency electromagnetic waves (RF), to probe material and structural changes in integrated circuits under various external perturbations. We discuss how RF insertion loss (S21) based-techniques have been used to study the impact of thermal cycling on the thermo-mechanical reliability of Cu TSV-based interconnects in 3D-ICs. In addition, we demonstrate, with preliminary data, how Scanning Microwave Spectroscopy (based around RF reflectance (S11)) can be used to detect buried artifacts and characterize metallic contacts.

Modeling and Analysis of Vertical Interconnects in 3D ICs

Modeling and Analysis of Vertical Interconnects in 3D ICs

Fabrication and Characterization of Grain Growth in Electroplated Cu for 3D IC Interconnect Applications

not Available.

Performance of random-walk capacitance extractors for IC interconnects: A numerical study

With ever-shrinking feature geometries, multilevel IC interconnects will greatly influence overall circuit behavior. In particular, efficient numerical evaluation of 3D IC-interconnect capacitance is essential to achieving targeted design goals. Previously, we have reported a new random-walk (RW) algorithm for extracting capacitance of complex multilevel IC interconnects [see, Y.L. Le Coz and R.B. Iverson, Solid-St. Electron. 35, 1005 (1991)]. Here, for the first time, we present a numerical study concerning the influence of interconnect complexity on RW-extractor performance. Of primary interest, are the empirical relationships among geometric complexity, run time, and memory usage. We also include, for reference, comparisons with conventional finite-element (FE) and boundary-element (BI) capacitance extractors. Despite the general computational limitations of these conventional extractors, we have attempted to normalize numerical errors to a single common value. The problem geometry selected for our study consists of a long “bus” wire situated beneath a series of shorter cross wires. Problem complexity is controlled by increasing the bus-wire length and adding cross wires. We have found that at 1% normalized error in bus-wire self-capacitance, the RW extractor has the shortest execution time, which is uniquely independent of problem complexity. In addition, because the RW extractor requires no numerical meshing, an RW:BI:FE memory-usage ratio of 1:10 3:10 7 was observed. We conclude that the RW method may possibly excel in the high-complexity regime characteristic of multilevel IC interconnects.