Interconnect Delay Model Research Articles

Analytical Delay Model and Stability Analysis for MLGNR Interconnects

This paper analyzes the signal delay and relative stability of multilayer graphene nanoribbon (MLGNR) interconnects dependent on temperature at global lengths. A thermally aware driver interconnect load (DIL) system, constituted by equivalent single conductor (ESC) model along with mathematical equations, is proposed to convert multi-conductor transmission circuit into single transmission line of MLGNR. The temperature-dependent analytical delay model of MLGNR is evaluated and the obtained outcomes are compared with the simulated results. The analytical and simulated results are obtained at global interconnect length (2000-[Formula: see text]m) for 32[Formula: see text]nm, 22[Formula: see text]nm and 16[Formula: see text]nm nodes of technology under 200–500[Formula: see text]K temperature range of MLGNR. The simulation and analytical results reveal that the outcomes of the two models correspond well. The trend of the models shows the increase in delay with the rising temperature levels (200–500[Formula: see text]K) for three different nodes of technology. Further, relative stability analysis of MLGNR as interconnect line at three different technological nodes from 500–2000-[Formula: see text]m lengths is examined.

High speed RLC equivalent RC delay model using normalized asymptotic function for global VLSI interconnects

This work proposes a mathematical delay models for global VLSI interconnects using normalized asymptotic value of characteristic impedance of RLC interconnected line. In the proposed Model (R0C0) the delay of RLC interconnects line is formulated by incorporating the line inductance in terms of effective impedance. The earlier simple RC interconnect models results in a significant error in delay estimation in long interconnects. Due to this analogy the non-ideal effect of inductive behaviour at high frequencies and scaled technologies such as ringing, spikes overshoot and undershoot can be suppressed. The dominance of inductance effect is optimized by Simulative Sweep Analysis Techniques (SSAT). Accuracy is verified by analytical and SPICE simulation results. Step response analysis of the proposed model is validated with the existing literature and found to be superior. Using this approach the results for both the signaling technique i.e. voltage and current mode signaling are found in close agreement between analytical and simulation for long interconnect lines.

High speed RLC equivalent RC delay model for global VLSI interconnects

Current-mode signaling significantly is known for increasing the bandwidth of on-chip interconnects and reduces the overall propagation delay. In this paper feature of current mode interconnects is exploited for investigating the performance of RLC equivalent ReffCT mathematical delay model of interconnects. This is due to a simple RC interconnects model which results a significant error in delay estimation. Due to this equivalency the non ideal effect of inductive behavior at high frequencies and scaled technologies can be suppressed. The dominance of inductance effect is optimized by Simulative Sweep Analysis Techniques (SSAT). Accuracy is verified by analytical and SPICE simulation results. The performance of delay model is further estimated for voltage and current mode interconnects. When test results are estimated with voltage and current mode systems, it is observed that the equivalent model is superior to the traditional Elmore and Sakurai delay model.

Interconnect Delay Model for Wide Supply Voltage Range Repeater Insertion in Sub-22 nm FinFET Technologies

Interconnect Delay Model for Wide Supply Voltage Range Repeater Insertion in Sub-22 nm FinFET Technologies

A Unified Delay, Power and Crosstalk Model for Current Mode Signaling Multiwall Carbon Nanotube Interconnects

Multiwall carbon nanotube (MWCNT) has been investigated as a potential interconnect material for future advanced technology nodes. The present paper analyzes performance of MWCNT interconnects using current mode signaling (CMS) scheme. The novelty of the present work can be stated as: Firstly, a unified model is proposed for both copper and MWCNT interconnects using finite-difference time-domain (FDTD) technique. Secondly, this model is applicable for both the conventional voltage mode signaling and more versatile CMS schemes. Furthermore, the presented FDTD-based model is valid for single as well as M-line coupled interconnects in integrated circuits. The model also incorporates CMOS gate as driver for MWCNT interconnect. Thirdly, power model using FDTD technique is investigated for the first time. Accurate formulation and computation of power dissipation in CMS MWCNT interconnects are presented in the paper. Propagation delay, power dissipation and power_delay_product (PDP) are the performance metrics considered for single-line CMS MWCNT interconnect. Crosstalk is analyzed for 2-Line and 5-Line coupled interconnects. It is investigated that CMS scheme leads to about 4 times lesser propagation delay and 2.5 times reduced PDP in MWCNT interconnect than the conventional copper interconnect for interconnect length of 4500 $$\upmu $$ m. The technology node considered is 32 nm. The response of the system is accurately computed using the proposed FDTD-based model. The maximum percentage error between results obtained by the proposed analytical model and SPICE simulation model is <3% for the various test cases.

Signal Propagation Delay Model in Vertically Stacked Chips

To design high quality three-dimensional integrated circuits (3-D ICs), the effect of process and design parameters on delay must be adequately understood. This paper presents an electrical circuit model of an entire structure in through silicon via (TSV) based 3-D ICs with a new equation for on-chip interconnect capacitance and then proposes an effective model for evaluating signal propagation delay in vertically stacked chips. All electrical parameter values can be calculated by the closed-form equations without a field solver. The delay model is constructed with the first- or second-order function of each parameter to the delay obtained from a typical structure. The results obtained by on-chip interconnect capacitance equations and delay model are in excellent agreement with those by a field solver and circuit simulator, respectively. We also show that the model is very useful for evaluating effects of the process and design parameters on vertical signal propagation delay such as the sensitivity and variability analysis.

Improved Analytical Delay Models for RC-Coupled Interconnects

As process technologies scale into deep submicrometer region, crosstalk delay is becoming increasingly severe, especially for global on-chip buses. To cope with this problem, accurate delay models of coupled interconnects are needed. In particular, delay models based on analytical approaches are desirable, because they are not only largely transparent to technology, but also explicitly establish the connections between delays of coupled interconnects and transition patterns, thereby enabling crosstalk alleviating techniques such as crosstalk avoidance codes. Unfortunately, existing analytical delay models, such as the widely cited model in [1], have limited accuracy and do not account for loading capacitance. In this brief, we propose analytical delay models for coupled interconnects that address these disadvantages.

Closed form Delay Model for on-Chip VLSIRLCG Interconnects for Ramp Input for Different Damping Conditions

Fast delay estimation methods, as opposed to simulation techniques, are needed for incremental performance driven layout synthesis. On-chip inductive effects are becoming predominant in deep submicron interconnects due to increasing clock speed and circuit complexity. Inductance causes noise in signal waveforms, which can adversely affect the performance of the circuit and signal integrity. Several approaches have been put forward which consider the inductance for on-chip interconnect modelling. But for even much higher frequency, of the order of few GHz, the shunt dielectric lossy component has become comparable to that of other electrical parameters for high speed VLSI design. In order to cope up with this effect, on-chip interconnect has to be modelled as distributed RLCG line. Elmore delay based methods, although efficient, cannot accurately estimate the delay for RLCG interconnect line. In this paper, an accurate analytical delay model has been derived, based on first and second moments of RLCG interconnection lines. The proposed model considers both the effect of inductance and conductance matrices. We have performed the simulation in 0.18μm technology node and an error of as low as less as 5% has been achieved with the proposed model when compared to SPICE. The importance of the conductance matrices in interconnect modelling has also been discussed and it is shown that if G is neglected for interconnect line modelling, then it will result an delay error of as high as 6% when compared to SPICE.

A statistical RCL interconnect delay model taking account of process variations

As the feature size of the CMOS integrated circuit continues to shrink, process variations have become a key factor affecting the interconnect performance. Based on the equivalent Elmore model and the use of the polynomial chaos theory and the Galerkin method, we propose a linear statistical RCL interconnect delay model, taking into account process variations by successive application of the linear approximation method. Based on a variety of nano-CMOS process parameters, HSPICE simulation results show that the maximum error of the proposed model is less than 3.5%. The proposed model is simple, of high precision, and can be used in the analysis and design of nanometer integrated circuit interconnect systems.

A novel low-swing interconnect optimization model with delay and bandwidth constraints

Interconnect power and repeater area are important in the interconnect optimization of nanometer scale integrated circuits. Based on the RLC interconnect delay model, by wire sizing, wire spacing and adopting low-swing interconnect technology, this paper proposed a power-area optimization model considering delay and bandwidth constraints simultaneously. The optimized model is verified based on 65-nm and 90-nm complementary metal-oxide semiconductor (CMOS) interconnect parameters. The verified results show that averages of 36% of interconnect power and 26% of repeater area can be saved under 65-nm CMOS process. The proposed model is especially suitable for the computer-aided design of nanometer scale systems-on-chip.

A multilevel nano-scale interconnection RLC delay model

Based on the multilevel interconnections temperature distribution model and the RLC interconnection delay model of the integrate circuit, this paper proposes a multilevel nano-scale interconnection RLC delay model with the method of numerical analysis, the proposed analytical model has summed up the influence of the configuration of multilevel interconnections, the via heat transfer and self-heating effect on the interconnection delay, which is closer to the actual situation. Delay simulation results show that the proposed model has high precision within 5% errors for global interconnections based on the 65 nm CMOS interconnection and material parameter, which can be applied in nanometer CMOS system chip computer-aided design.

An improved Elmore delay model for VLSI interconnects

Elmore delay metric is a widely used model to compute signal delays for both analog and digital circuit interconnects. Although it provides a limited accuracy and its applicability is limited to the step function type input signals, this model is extremely popular with simple analytical functions that can be easily incorporated into design and automation software. In this work, a new boundary limiting the Elmore delay is introduced. A general form of traditional Elmore delay is defined and solved by utilizing this boundary. The new solution of the propagation delay problem called the improved Elmore delay model is derived according to the compound interest problem of Jacob Bernoulli. The improved Elmore delay formulation and the traditional Elmore delay model are compared according to SPICE simulation environment performances which verifies the superior accuracy of the novel delay formulation. The test results proved that better accuracy is achieved with the improved Elmore delay model than the traditional Elmore delay model with the same computation speed.

Predicting Interconnect Delay for Physical Synthesis in a FPGA CAD Flow

This paper studies the prediction of interconnect delay in an industrial setting. Industrial circuits and two industrial field-programmable gate-array (FPGA) architectures were used in this paper. We show that there is a large amount of inherent randomness in a state-of-the-art FPGA placement algorithm. Thus, it is impossible to predict interconnect delay with a high degree of accuracy. Furthermore, we show that a simple timing model can be used to predict some aspects of interconnect timing with just as much accuracy as predictions obtained by running the placement tool itself. Using this simple timing model in a two-phase timing driven physical synthesis flow can both improve quality of results and decrease runtime. Next, we present a metric for predicting the accuracy of our interconnect delay model and show how this metric can be used to reduce the runtime of a timing driven physical synthesis flow. Finally, we examine the benefits of using the simple timing model in a timing driven physical synthesis flow, and attempt to establish an upper bound on these possible gains, given the difficulty of interconnect delay prediction.

Analytical delay models for RLC interconnects under ramp input

Analytical delay models for Resistance Inductance Capacitance (RLC) interconnects with ramp input are presented for different situations, which include overdamped, underdamped and critical response cases. The errors of delay estimation using the analytical models proposed in this paper are less by 3% in comparison to the SPICE-computed delay. These models are meaningful for the delay analysis of actual circuits in which the input signal is ramp but not ideal step input.

Modeling and analysis of nonuniform substrate temperature effects on global ULSI interconnects

Nonuniform thermal profiles on the substrate in high-performance ICs can significantly impact the performance of global on-chip interconnects. This paper presents a detailed modeling and analysis of the interconnect performance degradation due to the nonuniform temperature profiles that are encountered along long metal interconnects as a result of existing thermal gradients in the underlying Silicon substrate. A nonuniform temperature-dependent distributed RC interconnect delay model is proposed. The model is applied to a wide variety of interconnect layouts and substrate temperature distributions to quantify the impact of such thermal nonuniformities on signal integrity issues including speed degradation in global interconnect lines and skew fluctuations in clock signal distribution networks. Subsequently, a new thermally dependent zero-skew clock-routing methodology is presented. This study suggests that thermally aware analysis should become an integrated part of the various optimization steps in physical-synthesis flow to improve the performance and integrity of signals in global ultra large scale integration interconnects.

Fitted Elmore delay: a simple and accurate interconnect delay model

In this brief, we present a new interconnect delay model called fitted Elmore delay (FED). FED is generated by approximating HSPICE delay data using a curve fitting technique. The functional form used in curve fitting is derived based on the Elmore delay (ED) model. Thus, our model has all the advantages of the ED model. It has a closed-form expression as simple as the ED model and is extremely efficient to compute. Interconnect optimization with respect to design parameters can also be done as easily as in the ED model. In fact, most previous algorithms and programs based on ED model can use our model without much change. Most importantly, FED is significantly more accurate than the ED model. The maximum error in delay estimation is at most 2% for our model, compared to 8.5% for the scaled ED model. The average error is less than 0.8%. We also show that FED can be more than 10 times more accurate than the ED model when applied to wire sizing.

A timing-driven floorplanning algorithm with the Elmore delay model for building block layout

This paper presents a timing-driven floorplanning algorithm for building block layout. As the interconnection delay model, the proposed algorithm adopts the Elmore delay model. The algorithm consists of two phases. In the first phase, a timing-driven topological arrangement of blocks is generated with the resolution of overlap among blocks using nonlinear programming under the timing constraints. In the second one, the algorithm performs floorplan sizing which determines the sizes and the shapes of blocks based on the topological arrangement obtained in the first phase so as to minimize the chip area, and obtains a legal floorplan. This phase is based on the topological constraint manipulation. Through the experimental results, the proposed algorithm can produce results without any timing violations within a practical computation time.

Automated Synthesis of Skew-Based Clock Distribution Networks

In this paper a top-down methodology is presented for synthesizing clock distribution networks based on application-dependent localized clock skew. The methodology is divided into four phases: 1) determination of an optimal clock skew schedule for improving circuit performance and reliability; 2) design of the topology of the clock tree based on the circuit hierarchy and minimum clock path delays; 3) design of circuit structures to implement the delay values associated with the branches of the clock tree; and 4) design of the geometric layout of the clock distribution network. Algorithms to determine an optimal clock skew schedule, the optimal clock delay to each register, the network topology, and the buffer circuit dimensions are presented.The clock distribution network is implemented at the circuit level in CMOS technology and a design strategy based on this technology is presented to implement the individual branch delays. The minimum number of inverters required to implement the branch delays is determined, while preserving the polarity of the clock signal. The clock lines are transformed from distributed resistive-capacitive interconnect lines into purely capacitive interconnect lines by partitioning the RC interconnect lines with inverting repeaters. The inverters are specified by the geometric size of the transistors, the slope of the ramp shaped input/output waveform, and the output load capacitance. The branch delay model integrates an inverter delay model with an interconnect delay model. Maximum errors of less than 2.5% for the delay of the clock paths and 4% for the clock skew between any two registers belonging to the same global data path are obtained as compared with SPICE Level-3.

A timing-driven placement algorithm with the Elmore delay model for row-based VLSIs

In this paper, we present a timing-driven placement algorithm for standard cell layout, and propose a path-based timing-driven placement algorithm. To estimate the accurate interconnection delay, the proposed algorithm adopts the Elmore delay model [8] so that we can apply the proposed algorithm to wider technologies than the conventional algorithms. The proposed algorithm is based on hierarchical partitioning and nonlinear programming, and consists of three phases. In the first phase, the algorithm produces an initial placement by a timing-driven min-cut partitioning algorithm. Next, an iterative improvement phase improves the initial placement by nonlinear programming. The improvement problem is formulated as the problem of minimizing the total wire length subject to timing constraints. Finally, a row assignment phase considering timing constraint arranges cells in rows. From the experimental results comparing with RITUAL [29], the proposed algorithm is much better than RITUAL in regard to the maximum violation ratio, the total wire length, and the cut size, and is more effective in point of the interconnection delay model and its extendability.

An analytical delay model for RLC interconnects

Elmore delay has been widely used to estimate interconnect delays in the performance-driven synthesis and layout of very-large-scale-integration (VLSI) routing topologies. For typical RLC interconnections, however, Elmore delay can deviate significantly from SPICE-computed delay, since it is independent of inductance of the interconnect and rise time of the input signal. Here, we develop an analytical delay model based on first and second moments to incorporate inductance effects into the delay estimate for interconnection lines under step input. Delay estimates using our analytical model are within 15% of SPICE-computed delay across a wide range of interconnect parameter values. We also extend our delay model for estimation of source-sink delays in arbitrary interconnect trees. We observe significant improvement in the accuracy of delay estimates for interconnect trees when compared to the Elmore model, yet our estimates are as easy to compute as Elmore delay. Evaluation of our analytical models is several orders of magnitude faster than simulation using SPICE. We also illustrate the application of our model in controlling response undershoot/overshoot and reducing interconnect delay through constraints on the moments.