Interconnect Process Variations Research Articles

Characterization of Interconnect Process Variation in CMOS Using Electrical Measurements and Field Solver

An electrical methodology to extract the complete set of interconnect process parameters is developed. A new structure comprising a combination of integrated meander resistor and a comb-capacitor sandwiched between bottom and top plates is proposed. Its electrical characterization provides all the necessary measurement data required for reliable and robust extraction of interconnect parameters, namely, interconnect thickness, width, as well as dielectric thickness and dielectric constant. A nonlinear optimizer based on the simulated annealing method coupled with an accurate random walk field solver is used for this purpose. The measurements are performed on a 130-nm Cu CMOS process and the extracted parameters are shown to be within 6% of the values obtained from cross-sectional scanning electron microscope (XSEM) data. Further, the applicability of the methodology to characterize the interconnects in more advanced technology nodes is also discussed.

A Method for Minimizing Clock Skew Fluctuations Caused by Interconnect Process Variations

A Method for Minimizing Clock Skew Fluctuations Caused by Interconnect Process Variations

Inclusion of Chemical-Mechanical Polishing Variation in Statistical Static Timing Analysis

Technology trends show the importance of modeling process variation in static timing analysis. With the advent of statistical static timing analysis (SSTA), multiple independent sources of variation can be modeled. This paper proposes a methodology for modeling metal interconnect process variation in SSTA. The developed methodology is applied in this study to investigate metal variation in SSTA resulting from chemical-mechanical polishing (CMP). Using our statistical methodology, we show that CMP variation has a smaller impact on chip performance as compared to other factors impacting metal process variation.

Effects of process variation in VLSI interconnects – a technical review

PurposeProcess variation has become a major concern in the design of many nanometer circuits, including interconnect pipelines. The purpose of this paper is to provide a comprehensive overview of types and sources of all aspects of interconnect process variations.Design/methodology/approachThe impacts of these interconnect process variations on circuit delay and cross‐talk noises along with the two major sources of delays – parametric delay variations and global interconnect delays – have been discussed.FindingsParametric delay evaluation under process variation method avoids multiple parasitic extractions and multiple delay evaluations as is done in the traditional response surface method. This results in significant speedup. Furthermore, both systematic and random process variations have been contemplated. The systematic variations need to be experimentally modeled and calibrated while the random variations are inherent fluctuations in process parameters due to any reason in manufacturing and hence are non‐deterministic.Originality/valueThis paper usefully reviews process variation effects on very large‐scale integration (VLSI) interconnect.

Stochastic Physical Synthesis Considering Prerouting Interconnect Uncertainty and Process Variation for FPGAs

Process variation and prerouting interconnect delay uncertainty affect timing and power for modern VLSI designs in nanometer technologies. This paper presents the first in-depth study on stochastic physical synthesis algorithms leveraging statistical static timing analysis (SSTA) with process variation and prerouting interconnect delay uncertainty for field-programmable gate arrays (FPGAs). Evaluated by SSTA using the placed and routed circuits, the stochastic clustering, placement, and routing reduce the mean delay by 5.0%, 4.0%, and 1.4%, respectively, and reduce the standard deviation of delay by 6.4%, 6.1%, and 1.4%, respectively for MCNC designs. The majority of improvements come from modeling interconnect delay uncertainty for clustering and from considering process variation for placement, while routing has less improvement on delay. In addition, we study the interaction between each individual design stage. When applying all stochastic algorithms concurrently, the mean delay and standard deviation are reduced by 6.2% and 7.5%, respectively. On the other hand, stochastic clustering with deterministic placement and routing is a good flow with little change to the entire flow, but the mean delay is reduced by 5.0%, the standard deviation is reduced by 6.4%, and the runtime is slightly reduced compared to the deterministic flow. Finally, while its improvement over timing is small, stochastic routing is able to reduce the total wire length by 4.5% and to reduce the overall runtime by 4.2% compared to deterministic routing.

Simulation of interconnect inductive impact in the presence of process variations in 90 nm and beyond

The on-chip inductive impact on signal integrity has been a problem for designs in deep-submicrometer technologies. The inductive impact increases the clock skew, max timing, and noise of bus signals. In this letter, circuit simulations using silicon-validated macromodels show that there is a significant inductive impact on the signal max timing (~ 10% pushout versus RC delay) and noise (~2timesRC noise). In nanometer technologies, process variations have become a concern. Results show that device and interconnect process variations add ~ 3% to the RLC max-timing impact. However, their impact on the RLC signal noise is not appreciable. Finally, inductive impact in 65- and 45-nm technologies is investigated, which indicates that the inductance impact will not diminish as technology scales

Rapid Method to Account for Process Variation in Full-Chip Capacitance Extraction

Full-chip capacitance extraction programs based on lookup techniques, such as HILEX/CUP , can be enhanced to rigorously account for process variations in the dimensions of very large scale integration interconnect wires with only modest additional computational effort. HILEX/CUP extracts interconnect capacitance from layout using analytical models with reasonable accuracy. These extracted capacitances are strictly valid only for the nominal interconnect dimensions; the networked nature of capacitive relationships in dense, complex interconnect structures precludes simple extrapolations of capacitance with dimensional changes. However, the derivatives, with respect to linewidth variation of the analytical models, can be accumulated along with the capacitance itself for each interacting pair of nodes. A numerically computed derivative with respect to metal and dielectric layer thickness variation can also be accumulated. Each node pair's extracted capacitance and its gradient with respect to linewidth and thickness variation on each metal and dielectric layer can be stored in a file. Thus, instead of storing a scalar value for each extracted capacitance, a vector of 3I+1 values will be stored for capacitance and its gradient, where I is the number of metal layers. Subsequently, this gradient information can be used during circuit simulation in conjunction with any arbitrary vector of interconnect process variations to perform sensitivity analysis of circuit performance.