Inter-task Interference Research Articles

Expanding SafeSU capabilities by leveraging security frameworks for contention monitoring in complex SoCs

The increased performance requirements of applications running on safety-critical systems have led to the use of complex platforms with several CPUs, GPUs, and AI accelerators. However, higher platform and system complexity challenge performance verification and validation since timing interference across tasks occurs in unobvious ways, hence defeating attempts to optimize application consolidation informedly during design phases and validating that mutual interference across tasks is within bounds during test phases.In that respect, the SafeSU has been proposed to extend inter-task interference monitoring capabilities in simple systems. However, modern mixed-criticality systems are complex, with multilayered interconnects, shared caches, and hardware accelerators. To that end, this paper proposes a non-intrusive add-on approach for monitoring interference across tasks in multilayer heterogeneous systems implemented by leveraging existing security frameworks and the SafeSU infrastructure.The feasibility of the proposed approach has been validated in an RTL RISC-V-based multicore SoC with support for AI hardware acceleration. Our results show that our approach can safely track contention and properly break down contention cycles across the different sources of interference, hence guiding optimization and validation processes.

Over-the-Air Federated Multi-Task Learning via Model Sparsification, Random Compression, and Turbo Compressed Sensing

To achieve communication-efficient federated multi-task learning (FMTL), we propose an over-the-air FMTL (OA-FMTL) framework, where multiple learning tasks deployed on edge devices share a non-orthogonal fading channel under the coordination of an edge server (ES). To overcome the inter-task interference inherent in the non-orthogonal transmission among tasks, we design a novel transmission method called model sparsification and random compression (MSRC) as well as a reception method called modified turbo compressed sensing (M-Turbo-CS). More specifically, at each edge device, the local model updates of all tasks are first sparsified and <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">randomly</i> compressed with different random compression matrices for different tasks, before being superimposed and sent over the uplink channel. Then the ES constructes the model aggregations of all the tasks from the channel observation data through a modified version of the turbo compressed sensing (Turbo-CS) algorithm called M-Turbo-CS. We analyze the performance of the proposed OA-FMTL framework with MSRC and M-Turbo-CS. Based on the analysis, we formulate a communication-learning optimization problem to improve the system performance by adjusting the power allocation among the tasks at the edge devices. Numerical simulations show that our proposed OA-FMTL efficiently suppresses the inter-task interference to achieve a learning performance comparable to the inter-task interference free bound at a significantly reduced communication overhead. It is also shown that the proposed inter-task power allocation optimization algorithm further reduces the overall communication overhead by appropriately adjusting the power allocation among the tasks.

Over-the-Air Federated Multi-Task Learning Over MIMO Multiple Access Channels

With the explosive growth of data and wireless devices, federated learning (FL) over wireless medium has emerged as a promising technology for large-scale distributed intelligent systems. Yet, the urgent demand for ubiquitous intelligence will generate a large number of concurrent FL tasks, which may seriously aggravate the scarcity of communication resources. By exploiting the analog superposition of electromagnetic waves, over-the-air computation (AirComp) is an appealing solution to alleviate the burden of communication required by FL. However, sharing frequency-time resources in over-the-air computation inevitably brings about the problem of inter-task interference, which poses a new challenge that needs to be appropriately addressed. In this paper, we study over-the-air federated multi-task learning (OA-FMTL) over the multiple-input multiple-output (MIMO) multiple access (MAC) channel. We propose a novel model aggregation method for the alignment of local gradients of different devices, which alleviates the straggler problem in over-the-air computation due to the channel heterogeneity. We establish a communication-learning analysis framework for the proposed OA-FMTL scheme by considering the spatial correlation between devices, and formulate an optimization problem for the design of transceiver beamforming and device selection. To solve this problem, we develop an algorithm by using alternating optimization (AO) and fractional programming (FP), which effectively mitigates the impact of inter-task interference on the FL learning performance. We show that due to the use of the new model aggregation method, device selection is no longer essential, thereby avoiding the heavy computational burden involved in selecting active devices. Numerical results demonstrate the validity of the analysis and the superb performance of the proposed scheme.

Fine-grained recognition: Multi-granularity labels and category similarity matrix

The core of fine-grained recognition is to distinguish different subcategories within a same broad category through subtle differences in images. Yet two important factors are less explored: Firstly, the degree of similarity between categories, with the more similar categories being more likely to be confused. Secondly, different fine-grained definitions under divergent levels of expertise, with one coarse label corresponding to multiple similar fine categories (e.g., a brand of car has multiple models). In this paper, we discover that multi-granularity label can function as an intermediary for turning inter-category similarity relations into fine-grained recognition performance. Specifically, we first explore the association between label hierarchies in multi-granularity prediction: both coarse and fine label predictions require coarse information, but fine label prediction additionally requires subtle information. Then, a multi-granularity classification framework is proposed, where the extracted feature is decoupled and re-coupled into groups for predicting labels at different granularities, respectively. The key is to involve coarse-grained features in the prediction of finer-level labels. The realization way is to train these features with a joint probability-based loss that we design to reduce inter-task interference through inter-granularity probability relations. Lastly, for tasks without coarse labels, a category similarity matrix is suggested for measuring inter-class similarity and a further non-parametric aggregation method is devised for clustering fine labels into coarse labels. The evaluation is carried out on several fine-grained classification benchmark datasets. Results show that the proposed approach achieves state-of-the-art in multi-granularity classification and exhibits the potential to enhance existing fine-grained recognition models.

Genetic dissection of mutual interference between two consecutive learning tasks in Drosophila.

Animals can continuously learn different tasks to adapt to changing environments and, therefore, have strategies to effectively cope with inter-task interference, including both proactive interference (Pro-I) and retroactive interference (Retro-I). Many biological mechanisms are known to contribute to learning, memory, and forgetting for a single task, however, mechanisms involved only when learning sequential different tasks are relatively poorly understood. Here, we dissect the respective molecular mechanisms of Pro-I and Retro-I between two consecutive associative learning tasks in Drosophila. Pro-I is more sensitive to an inter-task interval (ITI) than Retro-I. They occur together at short ITI (<20 min), while only Retro-I remains significant at ITI beyond 20 min. Acutely overexpressing Corkscrew (CSW), an evolutionarily conserved protein tyrosine phosphatase SHP2, in mushroom body (MB) neurons reduces Pro-I, whereas acute knockdown of CSW exacerbates Pro-I. Such function of CSW is further found to rely on the γ subset of MB neurons and the downstream Raf/MAPK pathway. In contrast, manipulating CSW does not affect Retro-I as well as a single learning task. Interestingly, manipulation of Rac1, a molecule that regulates Retro-I, does not affect Pro-I. Thus, our findings suggest that learning different tasks consecutively triggers distinct molecular mechanisms to tune proactive and retroactive interference.

DAG Scheduling and Analysis on Multi-Core Systems by Modelling Parallelism and Dependency

With ever more complex functionalities being implemented in emerging real-time applications, multi-core systems are demanded for high performance, with directed acyclic graphs (DAG) being used to model functional dependencies. For a single DAG task, our previous work presented a concurrent provider and consumer (CPC) model that captures the node-level dependency and parallelism, which are the two key factors of a DAG. Based on the CPC, scheduling and analysis methods were constructed to reduce makespan and tighten the analytical bound of the task. However, the CPC-based methods cannot support multi-DAGs as the interference between DAGs (i.e., inter-task interference) is not taken into account. To address this limitation, this article proposes a novel multi-DAG scheduling approach which specifies the number of cores a DAG can utilise so that it does not incur the inter-task interference. This is achieved by modelling and understanding the workload distribution of the DAG and the system. By avoiding the inter-task interference, the constructed schedule provides full compatibility for the CPC-based methods to be applied on each DAG and reduces the pessimism of the existing analysis. Experimental results show that the proposed multi-DAG method achieves an improvement up to 80% in schedulability against the original work that it extends, and outperforms the existing multi-DAG methods by up to 60% for tightening the interference.

Global Fixed-Priority Scheduling for Parallel Real-Time Tasks with Constrained Parallelism

With the rapid development of parallel programming techniques and the widespread use of multiprocessors, scheduling and analysis techniques supporting parallel real-time tasks become a critical topic for multiprocessor real-time systems. Global scheduling that allows the vertices of a parallel task to execute on any processor is a promising scheduling approach with guaranteed theoretical bounds and wide use in practice. However, the complex internal structure of parallel tasks leads to extensive inner- and inter-task interference, which leads to significant pessimism in the worst-case timing analysis. In this paper, a global fixed-priority (G-FP) scheduling with constrained parallelism for parallel real-time tasks based on the sporadic directed acyclic graph (DAG) model is proposed. Each DAG task is assigned a parallel threshold, such that the number of processors occupied by the task is limited to the parallel threshold of the task at a time. We propose a heuristic algorithm to set the parallel threshold and present a response-time analysis (RTA) to exploit the feature of the constrained parallel scheduling. Experiments with randomly generated tasks show that the proposed approach improves the schedulability upon G-FP and federated scheduling in terms of acceptance ratio.

DeepNOMA: A Unified Framework for NOMA Using Deep Multi-Task Learning

Non-orthogonal multiple access (NOMA) will provide massive connectivity for future Internet of Things. However, the intrinsic non-orthogonality in NOMA makes it non-trivial to approach the performance limit with only conventional communication-theoretic tools. In this paper, we resort to deep multi-task learning for end-to-end optimization of NOMA, by regarding the overlapped transmissions as multiple distinctive but correlated learning tasks. First of all, we establish a unified multi-task deep neural network (DNN) framework for NOMA, namely DeepNOMA, which consists of a channel module, a multiple access signature mapping module, namely DeepMAS, and a multi-user detection module, namely DeepMUD. DeepMAS and DeepMUD are automatically trained in a data-driven fashion, and a multi-task balancing technique is then proposed to guarantee fairness among tasks as well as to avoid local optima. To further exploit the benefits of communication-domain expertise, we introduce constellation shape prior and inter-task interference cancellation structure into DeepMAS and DeepMUD, respectively. These sophisticated designs help to reduce the implementation complexity without sacrificing DNN’s universal function approximation property, which makes DeepNOMA a universal transceiver optimization approach. Detailed experiments and link-level simulations show that higher transmission accuracy and lower computational complexity can be simultaneously achieved by DeepNOMA under various channel models, compared with state-of-the-art.

Schedulability analysis of DAG tasks with arbitrary deadlines under global fixed-priority scheduling

One of the major sources of pessimism in the response time analysis (RTA) of globally scheduled real-time tasks is the computation of an upper-bound on the inter-task interference. This problem is further exacerbated when intra-task parallelism is permitted because of the complex internal structure of parallel tasks. This paper considers the global fixed-priority (G-FP) scheduling of sporadic real-time tasks when each task is modeled by a directed acyclic graph (DAG) of concurrent subtasks. We present a RTA based on the concept of problem window, a technique that has been extensively used to study the schedulability of sequential task in multiprocessor systems. The problem window approach of RTA usually categorizes interfering jobs in three different groups: carry-in, carry-out and body jobs. In this paper, we propose two novel techniques to derive less pessimistic upper-bounds on the workload produced by the carry-in and carry-out jobs of the interfering tasks. Those new bounds take into account the precedence constraints between subtasks pertaining to the same DAG. We show that with this new characterization of the carry-in and carry-out workload, the proposed schedulability test offers significant improvements on the schedulability of DAG tasks for randomly generated task sets in comparison to state-of-the-art techniques. In fact, we show that, while the state-of-art analysis does not scale with an increasing number of processors when tasks have constrained deadlines, the results of our analysis are barely impacted by the processor count in both the constrained and the arbitrary deadline case.

Elastic Places

The diversity and complexity of modern computing platforms makes the development of high-performance software challenging. Designing scalable software requires tuning for a large set of resources, including cores (parallelism), memory bandwidths, and various levels of private and shared caches, as well as developing strategies for optimizing locality. But highly optimized implementations are often inefficient when executed on a different platform. This is the performance portability problem. One approach to scalability and portability is to tune the amount of work per task based on runtime overheads and concurrency. This results in a better balance between parallelism and scheduling overheads, but it can neither tune data reuse nor avoid inter-task interference. We propose a complementary approach that consists in tuning the amount of resources allocated to tasks and combine it with software-defined task topologies to provide portable locality. These ideas are combined into a low-overhead resource management scheme called Elastic Places . Elastic Places is implemented in the XiTAO software framework but the core ideas are equally applicable to other languages and runtimes. Experimental results on an AMD-based NUMA machine and an Intel Knights Landing system show that elastic places provides both high scalability and performance portability, with speed-ups of up to 2.3× on both platforms compared to state-of-the-art runtimes.

Implementation of Partitioned Mixed-Criticality Scheduling on a Multi-Core Platform

Recent industrial trends favor the adoption of multi-core architectures for mixed-criticality applications. Although several mixed-criticality multi-core scheduling approaches have been proposed, currently there are few implementations on hardware that demonstrate efficient resource utilization and the ability to bound interference on shared resources. To address this necessity, we develop a mixed-criticality runtime environment on the Kalray MPPA-256 Andey many-core platform. The runtime environment implements a scheduling policy based on adaptive temporal partitioning. We develop models, methods and implementation principles to implement the necessary scheduling primitives, to achieve high platform utilization and to perform a compositional worst-case execution time analysis. The bounds account for scheduling overheads and for the inter-task interference on the platform’s shared memory. Using realistic benchmarks from avionics and signal processing, we validate the correctness and tightness of the bounds and demonstrate a high platform utilization.

Reducing the Upper Bound Delay by Optimizing Bank-to-Core Mapping

Nowadays, inter-task interferences are the main difficulty in analyzing the timing behavior of multicores. The timing predictable embedded multicore architecture MERASA, which allows safe worst-case execution time (WCET) estimations, has emerged as an attractive solution. In the architecture, WCET can be estimated by the upper bound delay (UBD) which can be bounded by the interference-aware bus arbiter (IABA) and the dynamic cache partitioning such as columnization or bankization. However, this architecture faces a dilemma between decreasing UBD and efficient shared cache utilization. To obtain tighter WCET estimation, we propose a novel approach that reduces UBD by optimizing bank-to-core mapping on the multicore system with IABA and the two-level partitioned cache. For this, we first present a new UBD computation model based on the analysis of inter-task interference delay, and then put forward the core-sequence optimization method of bank-to-core mapping and the optimizing algorithms with the minimum UBD. Experimental results demonstrate that our approach can reduce WCET from 4% to 37%.

User-Centric Power Management for Embedded CPUs Using CPU Bandwidth Control

Dynamic power management for mobile processors has become very important due to the increased clock speed and number of cores. There have been various power management governors using dynamic voltage and frequency scaling (DVFS). Among them, a user-centric power management has received a lot of attention as a method to save power while maintaining the quality of user experience (UX) referring to the perceived quality of system services to end users. Most user-centric governors have employed DVFS as a method to reduce the power consumption. However, DVFS may not be adequate enough to guarantee UX qualities for all task because the CPU clock speed changed by DVFS can affect all tasks running at the same processor. In order to minimize such inter-task interferences by DVFS, it is necessary to employ task-specific power management methods. This paper shows that CPU bandwidth control developed for CPU resource management within Linux kernel can be employed as a task-specific power management method, and a novel CPU power management scheme employing both DVFS and CPU bandwidth control is proposed. Experimental results show that the proposed governor can reduce the power consumption more than the Ondemand governor can achieve while maintaining the quality of UX.

A hard real-time capable multi-core SMT processor

Hard real-time applications in safety critical domains require high performance and time analyzability. Multi-core processors are an answer to these demands, however task interferences make multi-cores more difficult to analyze from a worst-case execution time point of view than single-core processors. We propose a multi-core SMT processor that ensures a bounded maximum delay a task can suffer due to inter-task interferences. Multiple hard real-time tasks can be executed on different cores together with additional non real-time tasks. Our evaluation shows that the proposed MERASA multi-core provides predictability for hard real-time tasks and also high performance for non hard real-time tasks.

Timing effects of DDR memory systems in hard real-time multicore architectures

Multicore processors are an effective solution to cope with the performance requirements of real-time embedded systems due to their good performance-per-watt ratio and high performance capabilities. Unfortunately, their use in integrated architectures such as IMA or AUTOSAR is limited by the fact that multicores do not guarantee a time composable behavior for the applications: the WCET of a task depends on inter-task interferences introduced by other tasks running simultaneously. This article focuses on the off-chip memory system: the hardware shared resource with the highest impact on the WCET and hence the main impediment for the use of multicores in integrated architectures. We present an analytical model that computes the worst-case delay, also known as Upper Bound Delay (UBD), that a memory request can suffer due to memory interferences generated by other co-running tasks. By considering the UBD in the WCET analysis, the resulting WCET estimation is independent from the other tasks, hence ensuring the time composability property and enabling the use of multicores in integrated architectures. We propose a memory controller for hard real-time multicores compliant with the analytical model that implements extra hardware features to deal with refresh operations and interferences generated by co-running non hard real-time tasks.

On the evaluation of the impact of shared resources in multithreaded COTS processors in time-critical environments

Commercial Off-The-Shelf (COTS) processors are now commonly used in real-time embedded systems. The characteristics of these processors fulfill system requirements in terms of time-to-market, low cost, and high performance-per-watt ratio. However, multithreaded (MT) processors are still not widely used in real-time systems because the timing analysis is too complex. In MT processors, simultaneously-running tasks share and compete for processor resources, so the timing analysis has to estimate the possible impact that the inter-task interferences have on the execution time of the applications. In this paper, we propose a method that quantifies the slowdown that simultaneously-running tasks may experience due to collision in shared processor resources. To that end, we designed benchmarks that stress specific processor resources and we used them to (1) estimate the upper limit of a slowdown that simultaneously-running tasks may experience because of collision in different shared processor resources, and (2) quantify the sensitivity of time-critical applications to collision in these resources. We used the presented method to determine if a given MT processor is a good candidate for systems with timing requirements. We also present a case study in which the method is used to analyze three multithreaded architectures exhibiting different configurations of resource sharing. Finally, we show that measuring the slowdown that real applications experience when simultaneously-running with resource-stressing benchmarks is an important step in measurement-based timing analysis. This information is a base for incremental verification of MT COTS architectures.

Motor abundance supports multitasking while standing

Many activities require simultaneous performance of multiple tasks. Motor redundancy may provide a key mechanism for multitasking, ensuring minimal inter-task interference. This study investigated the effect of performing two supra-postural tasks on postural stability. The component of joint configuration variance (JCV) reflecting flexible joint combinations (VUCM) that stabilize the center of mass (CoM) position and the component of JCV leading to variability (VORT) of the CoM were determined using the Uncontrolled Manifold (UCM) approach. Subjects executed a targeting task alone or in combination with a ball-balancing task. UCM analysis revealed that the joints were coordinated such that their combined variance reflected primarily VUCM, without a substantial effect on CoM position stability. Evidence for this flexible control strategy increased when the ball-balancing task was added to targeting, or when the index of difficulty of targeting increased, both without leading to substantial increases in VORT or CoM position variance. The increase in joint variance when performing additional tasks without affecting adversely CoM position stability supports the hypothesis that the nervous system takes advantage of available motor redundancy for the successful performance of multiple tasks concurrently. Future work is needed to investigate the limits of this control scheme.

Improving the WCET computation in the presence of a lockable instruction cache in multitasking real-time systems

In multitasking real-time systems it is required to compute the WCET of each task and also the effects of interferences between tasks in the worst case. This is very complex with variable latency hardware, such as instruction cache memories, or, to a lesser extent, the line buffers usually found in the fetch path of commercial processors. Some methods disable cache replacement so that it is easier to model the cache behavior. The difficulty in these cache-locking methods lies in obtaining a good selection of the memory lines to be locked into cache. In this paper, we propose an ILP-based method to select the best lines to be loaded and locked into the instruction cache at each context switch (dynamic locking), taking into account both intra-task and inter-task interferences, and we compare it with static locking. Our results show that, without cache, the spatial locality captured by a line buffer doubles the performance of the processor. When adding a lockable instruction cache, dynamic locking systems are schedulable with a cache size between 12.5% and 50% of the cache size required by static locking. Additionally, the computation time of our analysis method is not dependent on the number of possible paths in the task. This allows us to analyze large codes in a relatively short time (100KB with 10^6^5 paths in less than 3min).

Cache partitioning for energy-efficient and interference-free embedded multitasking

We propose a technique that leverages configurable data caches to address the problem of energy inefficiency and intertask interference in multitasking embedded systems. Data caches are often necessary to provide the required memory bandwidth. However, caches introduce two important problems for embedded systems. Caches contribute to a significant amount of power as they typically occupy a large part of the chip and are accessed frequently. In nanometer technologies, such large structures contribute significantly to the total leakage power as well. Additionally, cache outcomes in multitasking environments are notoriously difficult to predict, if not impossible, thus resulting in poor real-time guarantees. We study the effect of multiprogramming workloads on the data cache in a preemptive multitasking environment, and propose a technique which leverages configurable cache architectures to not only eliminate intertask cache interference, but also to significantly reduce both dynamic and leakage power. By mapping tasks to different cache partitions, interference is completely eliminated. Dynamic and leakage power are significantly reduced as only a subset of the cache is active at any moment. We introduce a profile-based, off-line algorithm, which identifies a beneficial cache partitioning. The OS configures the data cache during context-switch by activating the corresponding partition. Our experiments on a large set of multitasking benchmarks demonstrate that our technique not only efficiently eliminates intertask interference, but also significantly reduces both dynamic and leakage power.

Compositional, Dynamic Cache Management for Embedded Chip Multiprocessors

This paper proposes a dynamic cache repartitioning technique that enhances compositionality on platforms executing media applications with multiple utilization scenarios. Because the repartitioning between scenarios requires a cache flush, two undesired effects may occur: (1) in particular, the execution of critical tasks may be disturbed and (2) in general, a performance penalty is involved. To cope with these effects we propose a method which: (1) determines, at design time, the cache footprint of each tasks, such that it creates the premises for critical tasks safety, and minimum flush in general, and (2) enforces, at run-time, the design time determined cache footprints and further decreases the flush penalty. We implement our dynamic cache management strategy on a CAKE multiprocessor with 4 Trimedia cores. The experimental workload consists of 6 multimedia applications, each of which formed by multiple tasks belonging to an extended MediaBench suite. We found on average that: (1) the relative variations of critical tasks execution time are less than 0.1%, regardless of the scenario switching frequency, (2) for realistic scenario switching frequencies the inter-task cache interference is at most 4% for the repartitioned cache, whereas for the shared cache it reaches 68%, and (3) the off-chip memory traffic reduces with 60%, and the performance (in cycles per instruction) enhances with 10%, when compared with the shared cache.