Inter-task Communications Research Articles

An SMDP-based approach to thermal-aware task scheduling in NoC-based MPSoC platforms

In this paper, we consider the operation of a thermal-aware task scheduler, dispatching tasks from an arrival queue as well as setting the voltage and frequency of the processing cores to optimize the mean temperature margin of the entire chip (i.e., cores as well as the NoC routers). We model the decision process of the task scheduler as a semi-Markov decision problem (SMDP) to account for the most common uncertainties prevalent in MPSoC systems (including: the stochastic nature of the workload inter-arrival times, time-varying workload characteristics, the uncertain chip thermal profile as well as random inter-task communications). SMDP is among the fairly general variants of continuous-time optimization frameworks from the stochastic control theory and is a much more efficient choice compared to discrete-time formalisms (which would lead to an increase in task waiting times and degraded system performance). To solve the formulated SMDP, we propose two reinforcement learning (RL) algorithms that are capable of computing the optimal task assignment policy without requiring the statistical knowledge of the stochastic dynamics underlying the system states. The proposed algorithms also rely on function approximation techniques to handle the infinite length of the task queue as well as the continuous nature of temperature readings. Compared to previous work, the simulations demonstrate nearly 6 Kelvin reduction in system average peak temperature and 66 milliseconds decrease in mean task service time.

JAMPI: Efficient Matrix Multiplication in Spark Using Barrier Execution Mode

The new barrier mode in Apache Spark allows for embedding distributed deep learning training as a Spark stage to simplify the distributed training workflow. In Spark, a task in a stage does not depend on any other tasks in the same stage, and hence it can be scheduled independently. However, several algorithms require more sophisticated inter-task communications, similar to the MPI paradigm. By combining distributed message passing (using asynchronous network IO), OpenJDK’s new auto-vectorization and Spark’s barrier execution mode, we can add non-map/reduce-based algorithms, such as Cannon’s distributed matrix multiplication to Spark. We document an efficient distributed matrix multiplication using Cannon’s algorithm, which significantly improves on the performance of the existing MLlib implementation. Used within a barrier task, the algorithm described herein results in an up to 24% performance increase on a 10,000 × 10,000 square matrix with a significantly lower memory footprint. Applications of efficient matrix multiplication include, among others, accelerating the training and implementation of deep convolutional neural network-based workloads, and thus such efficient algorithms can play a ground-breaking role in the faster and more efficient execution of even the most complicated machine learning tasks.

Custom NoC topology generation using Discrete Antlion Trapping Mechanism

This paper outlines an innovative and creative algorithm known as Discrete Antlion Trapping Mechanism (DATM). It imitates the hunting mechanism of antlions in nature. The proposed DATM is incorporated in Network on Chip (NoC) which is a replacement to standard transmission technique along with the Reliable Reconfigurable Real-Time Operating System (R3TOS) for intertask communications. Though there are many designing issues, mapping the applications to NoC is an unmanageable and challenging problem. The DATM algorithm optimizes the above problem to reduce the energy consumption and transmission charge. The DATM method follows a systematic approach to analyze the scenario similar to other topology generating algorithms. Experimental results implemented in different applications showed that the proposed mechanism saved energy consumption on an average of 16.14% and 25.15% reduction in the transmission charge compared to other topologies.

TT-BIP: using correct-by-design BIP approach for modelling real-time system with time-triggered paradigm

In order to combine advantages of real-time operating systems implementing the time-triggered (TT) execution model and model-based design frameworks, we aim at proposing a correct-by-design methodology that derives correct TT implementations from high-level models. This methodology consists of two main steps: (1) transforming the high-level model into an intermediate model which respects the TT communication principles and where all communications between components are simple send/receive interactions, and (2) transforming the obtained intermediate model into the programming language of the target platform. In this paper, we focus on the presentation of the transformational methodology of the first step of this design flow. This methodology produces a correct-by-construction TT model by starting from a high-level model of the application software in behaviour, interaction, priority (BIP). BIP is a component-based framework with formal semantics that rely on multiparty interactions for synchronizing components. Commonly in TT implementations, tasks interact with each other through a communication medium. Our methodology transforms, depending on a user-defined task mapping, high-level BIP models where communication between components is strongly synchronized, into TT model that integrates a communication medium. Thus, only inter-task communications and components participating in such interactions are concerned by the transformation process. We also provide correctness proofs of the transformation and apply it on an industrial case study.

A regression test selection technique for embedded software

The current approaches for regression test selection of embedded programs are usually based on data- and control-dependency analyses, often augmented with human reasoning. Existing techniques do not take into account additional execution dependencies which may exist among code elements in such programs due to features such as tasks, task deadlines, task precedences, and intertask communications. In this context, we propose a model-based regression test selection technique for such programs. Our technique first constructs a graph model of the program; the proposed graph model has been designed to capture several characteristics of embedded programs, such as task precedence order, priority, intertask communication, timers, exceptions and interrupt handlers, which we consider important for regression-test selection. Our regression test selection technique selects test cases based on an analysis of the constructed graph model. We have implemented our technique to realize a prototype tool. The experimental results obtained using this tool show that, on average, our approach selects about 28.33% more regression test cases than those selected by a traditional approach. We observed that, on average, 36.36% of the fault-revealing test cases were overlooked by the existing regression test selection technique.

Explicit Allocation Strategy with Deadline and Budget Constraint Algorithm in Bag of Tasks Grid

Problem statement: This study is for effective scheduling of grid job s based on economy for space shared resources in Bag of tasks grid. Gr id Computing aims in combining the power of heterogeneous, geographically distributed, multi-do main computational resources to provide high performance or high throughput. Approach: Space shared resources are parallel supercomputers and clusters of workstations that provides a great amou nt of computational power. These resources require jobs to be specified formally in terms of the amoun t of time (tr) and number of processors (p) needed for execution. Bag-of-Tasks (BoT) is an application consists of several uniprocessor and independent tasks that have no inter-task communications or tas k-dependencies. BoT is highly suitable for executio n in grids. It is capable of tolerating network delay s or faults and does not require formal job submiss ion. The Explicit allocation strategy assigns the formal job parameters (p, tr) to the job requests, minimi zing the overhead on the grid users to provide a formal job specification. This strategy uses adaptive heur istics to determine the parameters based on certain heuris tics, in order to improve throughput. In the propos ed system, explicit allocation strategy combined with Deadline and Budget Constraint (DBC) Cost Time optimization algorithm performs effective schedulin g of the jobs based on the user's quality of servic e (QoS) requirements such as deadline, budget and optimization strategy. Results: The cost-time optimization scheduling allocates the cheapest reso urces to ensure that the deadline can be met and computation is minimized. In case if there are two resources with the same cost, scheduling is done in any affordable resource so that the job gets execut ed as early as possible. Conclusion: The performance of this scheme against the existing system is evalu ated using cost factor (C factor ) and speed up ratio (T speedup ) and this scheme is more effective than the existi ng system.

Embedded control software design with aspect patterns

This article presents an aspect-oriented design method for embedded control software. Model-based control design has become popular in embedded control systems such as automotive control systems. In the control logic design phase, a control model is built with a CAD/CAE tool such as MATLAB/Simulink, in which ‘zero-time execution’ is assumed. Then, in the software design phase, we design the software to meet timing constraints and to execute control logic correctly in the preemptive multi-task environment. We design task structures and then add mechanisms for data integrity. To make the timing design more efficient, we represent the mechanisms for the timing design as reusable aspect patterns. We define aspect patterns of triggering methods, synchronizations, and inter-task communications. We also provide a model weaver to weave the aspect patterns into the base model incrementally. In the timing design, we only have to select the aspect patterns and weave them into the functional model with the model weaver.

Integrating real-time inter-task communication channels into hardware–software codesign

Codesign in system on chip (SoC) systems is a joint development of hardware and software tasks to obtain a complete system design. Especially, a key problem in the hardware–software codesign for real-time embedded systems is related to the time-bounded communication channel that guarantees the deadlines of tasks, as well as the timely delivery of messages exchanged between tasks. This paper presents a technique to integrate a real-time inter-task communication channel into hardware–software codesign. The real-time inter-task communication channel presented in this paper is addressed from two perspectives: a unified inter-task communication interface and a combined task and message scheduling scheme. From the perspective of an inter-task communication interface, we consider three possible inter-task communication associations, software-to-software, software-to-hardware, and hardware-to-hardware task communication associations. Tasks and messages exploited in real-time inter-task communications are allowed to have periodic and aperiodic properties. In the unified inter-task communication interface, coarse-grained real-time processing is allowed at a level of task unit and fine-grained real-time processing is allowed at a piece of message frame unit. Consequently, periodic tasks and messages need to be timely processed and delivered to meet their deadlines, and aperiodic tasks and messages need to be quickly processed for fast response without missing periodic task and message deadlines. We present a novel scheduling policy from the perspective of the combined task and message scheduling scheme. In the scheduling policy, the first objective is to meet the timing constraints of periodic tasks as well as periodic messages simultaneously for given application-specific real-time requirements. The second objective is to improve the response time of aperiodic messages. We evaluated the performance of the proposed technique after implementing it on a commercial SoC platform. The experimental evaluation showed it yielded efficient performance in terms of the minimal deadline miss ratio of periodic tasks and messages, and a fast average response time for aperiodic messages.

SCHEDULING PARALLEL PROGRAM TASKS WITH NON-NEGLIGIBLE INTERTASK COMMUNICATIONS ON TO NUMA MULTIPROCESSOR SYSTEMS

The purpose of this paper is to examine the impact of scheduling parallel tasks onto non-uniform memory access (NUMA) shared-memory multiprocessor systems by considering non-negligible intertask communications and communication contentions. Communication contentions arise from the communication medium having insufficient capacity to serve all transmissions, thereby causing significant contention delays. Therefore, a new scheduling algorithm, herein referred to as the Extended Critical Path (ECP) algorithm is proposed. The proposed algorithm schedules parallel tasks by considering non-negligible intertask communications and the contentions among shared communication resources. Moreover, it ensures performance within a factor of two of the optimum for general directed acyclic task graphs (DATGs). Experimental results demonstrate the superiority of the ECP algorithm over the scheduling algorithms presented in previous literature.

Optimal scheduling of cooperative tasks in a distributed system using an enumerative method

Preemptive (resume) scheduling of cooperative tasks that have been preassigned to a set of processing nodes in a distributed system, when each task is assumed to consist of several modules is discussed. During the course of their execution, the tasks communicate with each other to collectively accomplish a common goal. Such intertask communications lead to precedence constraints between the modules of different tasks. The objective of this scheduling is to minimize the maximum normalized task response time, called the system hazard. Real-time tasks and the precedence constraints among them are expressed in a PERT/CPM form with activity on arc (AOA), called the task graph (TG), in which the dominance relationship between simultaneously schedulable modules is derived and used to reduce the size of the set of active schedules to be searched for an optimal schedule. Lower-bound costs are estimated, and are used to bound the search. An example of the task scheduling problem and some computational experiences are presented. >

Traffic-Specific Interconnection Networks for Multicomputers

Special-purpose networks of processors and intelligent switching devices can be programmed to solve problems with inherent parallelism. The target algorithm is coded into a number of asynchronously executing parallel tasks, and assigned to specific processors. For well-known algorithms, information about the data communicated between these tasks (traffic) can be characterized and used by a heuristic algorithm to produce a specialized interconnection network of switching devices at a lower cost and increased performance over the use of a general purpose structure. A program was developed which uses intertask communications to automatically generate interconnection structures of switch chips (SC's). Simulation results were used to compare cost/performance measures for the program-generated networks with some well-known structures, using both statistically generated traffic patterns and the simulation of real applications.

A Characterization and Analysis of Parallel Processor Interconnection Networks

The permuting properties of various interconnection networks have been extensively studied. However, not too much attention has been focused on how the permuting properties interact with the mapping of tasks to processors in realizing the communication requirements between tasks. In this paper we focus on characterizing the abilities of some interconnection networks in realizing intertask communication that can be specified as permutations of the task names. From the point of view of the intertask communications requirements, the perceived permuting capabilities may depend upon the specific assignment of tasks to processors. Distinct network permutations may actually result in equivalent intertask communication patterns depending upon the mapping of tasks to processors. Characterizations of networks are developed based upon the theory of permutation groups. A number of properties as well as limitations of these networks become evident from this characterization. Finally, a class of switching networks is identified, that possess many useful properties that make them preferable to multistage interconnection networks in specific applications.

Intertask communications in an integrated multirobot system

An integrated multirobot system (IMRS) consists of two or more robots, machinery, and sensors and is capable of executing almost all industrial processes with efficiency, flexibility, and reliability. Although the IMRS is motivated by an interesting application, it is essentially a distributed real-time processing system with various heterogeneous processes. To support a distributed modular architecture of the IMRS, low-level communication primitives are proposed along with their supporting language syntax which are typical of real-time concurrent programming languages. This is done by 1) carefully examining the generic structure and interactions of IMRS processes, 2) comparing and analyzing the primitives and syntax developed/proposed for general concurrent programming, and 3) using port-directed communications.

A Microprocessor Multi-Task Monitor

This paper describes a multi-task monitor program for microprocessors. Although written for the Intel 8085, it incorporates features that would be beneficial for implementation in other microprocessors used in controlling and monitoring experiments and accelerators. The monitor places permanent programs (tasks) arbitrarily located throughout ROM in a priority ordered queue. The programmer is provided with the flexibility to add new tasks or modified versions of existing tasks, without having to comply with previously defined task boundaries or having to reprogram all of ROM. Scheduling of tasks is triggered by timers, outside stimuli (interrupts), or inter-task communications. Context switching time is of the order of tenths of a millisecond.