Interprocessor Communication Research Articles

Разработка и внедрение многопоточного сервиса распознавания речи с помощью связки C#, C++ и Python

<p>This article discusses specificity of multithread industrial systems implementation using Python and its computation libraries. Article contains description of theory, including working principle of the Python’s Global Interpreter Locker (GIL), dependency management, multiprocessing library. The practical part of the article devoted to speech recognition service implementation. The implementation uses interprocess communication through shared memory based on "boost.interprocess" library. The result of integration architecture described by the article is reducing of CPU loading, in that case.</p>

Mitigating critical nodes in brain simulations via edge removal

Brain simulation holds promise for advancing our comprehension of brain mechanisms, brain-inspired intelligence, and addressing brain-related disorders. However, during brain simulations on high-performance computing platforms, the sparse and irregular communication patterns within the brain can lead to the emergence of critical nodes in the simulated network, which in turn become bottlenecks for inter-process communication. Therefore, effective moderation of critical nodes is crucial for the smooth conducting of brain simulation. In this paper, we formulate the routing communication problem commonly encountered in brain simulation networks running on supercomputers. To address this issue, we firstly propose the Node-Edge Centrality Addressing Algorithm (NCA) for identifying critical nodes and edges, based on an enhanced closeness centrality metric. Furthermore, drawing on the homology of spikes observed in biological brains, we develop the Edge Removal Transit Algorithm (ERT) to reorganize sparse and unbalanced inter-process communication in brain simulation, thereby diminishing the information centrality of critical nodes. Through extensive simulation experiments, we evaluate the performance of the proposed communication scheme and find that the algorithm accurately identifies critical nodes with a high accuracy. Our simulation experiments on 1600 GPU cards demonstrate that our approach can reduce communication latency by up to 25.4%, significantly shortening simulation time in large-scale brain simulations.

Quality Management in Software Development

Introduction. The scientific literature examines various approaches to quality management in information technology (IT). The issues of identifying and correcting defects are worked out, and the possibilities for minimizing them are shown. There are materials on quality management in complex engineering processes. At the same time, there is no detailed description of quality management at each stage of the IT product life cycle, including testing. It should be noted that the coordination of software releases is closely related to quality management, but this process is rarely or fragmentarily considered in the literature. Additionally, the interprocess communication is not taken into account; therefore, there is no comprehensive understanding of quality management in the creation, testing and refinement of software. This study is designed to fill these gaps. The research is aimed at presenting a comprehensive approach that links the theory, practice and methods of software quality management.Materials and Methods. Theoretical and applied literature on the subject were studied, analyzed, and reviewed. The author's professional background in managing the quality of IT products was used. The practices of global suppliers of digital goods and services were taken into account. The author has used these materials and methods to study in detail the issues of software testing and code deployment.Results. A comprehensive model of quality management in software development is elaborated, described and presented in the form of a diagram. Its interconnections with the project management model and the product life cycle, namely: analysis, design, development, testing, deployment, and support, are identified. Principles of quality management at each of these stages are specified. The processes and checks during code deployment are systematized and presented in the form of a diagram. Their features are shown in three environments: during development, testing, and production.Discussion and Conclusion. The algorithm allows quality experts to build the sequence of actions to eliminate detected defects in the future, understand the situation when it is possible (or impossible) to deploy code, and determine the moment when the software should be transferred to the user. In addition, the proposed scheme can be the basis for automating code deployment. The solution will reduce development time. As a result, the product will enter the market faster, which will speed up the payback of costs. The implementation of the model created within the framework of this scientific work into the production practice of IT companies presupposes strategic changes. Their implementation requires significant time and other resources; therefore, the overall transformation process should be divided into parts. The proposed approach is adaptable to the needs of various organizations and products. You can work with individual components to create an optimal plan for achieving quality management goals.

An interprocess communication-based two-way coupling approach for implicit–explicit multiphysics lattice discrete particle model simulations

In this study, the researchers have developed a Multiphysics-Lattice Discrete Particle Model (M-LDPM) framework that deals with coupled-fracture-poroflow problems. The M-LDPM framework uses two lattice systems, the LDPM tessellation and the Flow Lattice Element (FLE) network, to represent the heterogeneous internal structure of typical quasi-brittle materials like concrete and rocks, and to simulate the material’s mechanical and transport behavior at the aggregate scale. The researchers revisited the LDPM governing equations and added the influence of fluid pore pressure. They also derived the Flow Lattice Model (FLM) governing equations for pore pressure flow through mass conservation balances for uncracked and cracked volumes. The M-LDPM framework was implemented using Abaqus user element subroutine VUEL for the explicit dynamic procedure of LDPM and user subroutine UEL for the implicit transient procedure of FLM. The coupling of the two models was achieved using Interprocess Communication (IPC) between Abaqus solvers. The M-LDPM framework can simulate the variation of permeability induced by fracturing processes by relating the transport properties of flow elements with local cracking behaviors. The researchers validated the M-LDPM framework by comparing the numerical simulation outcomes with analytical solutions of classical benchmarks in poromechanics.

Overview of Embedded Rust Operating Systems and Frameworks.

Embedded Operating Systems (OSs) are often developed in the C programming language. Developers justify this choice by the performance that can be achieved, the low memory footprint, and the ease of mapping hardware to software, as well as the strong adoption by industry of this programming language. The downside is that C is prone to security vulnerabilities unknowingly introduced by the software developer. Examples of such vulnerabilities are use-after-free, and buffer overflows. Like C, Rust is a compiled programming language that guarantees memory safety at compile time by adhering to a set of rules. There already exist a few OSs and frameworks that are entirely written in Rust, targeting sensor nodes. In this work, we give an overview of these OSs and frameworks and compare them on the basis of the features they provide, such as application isolation, scheduling, inter-process communication, and networking. Furthermore, we compare the OSs on the basis of the performance they provide, such as cycles and memory usage.

I-PI 3.0: A flexible and efficient framework for advanced atomistic simulations.

Atomic-scale simulations have progressed tremendously over the past decade, largely thanks to the availability of machine-learning interatomic potentials. These potentials combine the accuracy of electronic structure calculations with the ability to reach extensive length and time scales. The i-PI package facilitates integrating the latest developments in this field with advanced modeling techniques thanks to a modular software architecture based on inter-process communication through a socket interface. The choice of Python for implementation facilitates rapid prototyping but can add computational overhead. In this new release, we carefully benchmarked and optimized i-PI for several common simulation scenarios, making such overhead negligible when i-PI is used to model systems up to tens of thousands of atoms using widely adopted machine learning interatomic potentials, such as Behler-Parinello, DeePMD, and MACE neural networks. We also present the implementation of several new features, including an efficient algorithm to model bosonic and fermionic exchange, a framework for uncertainty quantification to be used in conjunction with machine-learning potentials, a communication infrastructure that allows for deeper integration with electronic-driven simulations, and an approach to simulate coupled photon-nuclear dynamics in optical or plasmonic cavities.

Competing with autonomous model vehicles: a software stack for driving in smart city environments

This article introduces an open-source software stack designed for autonomous 1:10 scale model vehicles. Initially developed for the Bosch Future Mobility Challenge (BFMC) student competition, this versatile software stack is applicable to a variety of autonomous driving competitions. The stack comprises perception, planning, and control modules, each essential for precise and reliable scene understanding in complex environments such as a miniature smart city in the context of BFMC. Given the limited computing power of model vehicles and the necessity for low-latency real-time applications, the stack is implemented in C++, employs YOLO Version 5 s for environmental perception, and leverages the state-of-the-art Robot Operating System (ROS) for inter-process communication. We believe that this article and the accompanying open-source software will be a valuable resource for future teams participating in autonomous driving student competitions. Our work can serve as a foundational tool for novice teams and a reference for more experienced participants. The code and data are publicly available on GitHub.

Is Bare-metal I/O Performance with User-defined Storage Drives Inside VMs Possible? Benchmarking libvfio-user vs. Common Storage Virtualization Configurations

It is a critical concern for cloud computing providers to identify and adopt optimal virtual machine (VM) I/O storage paths. In Linux, these involve NVMe hardware, PCIe passthrough with vfio, and userspace drivers (e.g. SPDK). One project tying together these host-side improvements with the guests is vfio-user, a library and protocol for inter-process communication of I/O operations over sockets. QEMU/KVM VMs using vfio-user and SPDK are theoretically expected to attain low latencies due to mostly userspace processing, but this VM datapath configuration is still experimental and performance data is lacking in the literature.

Analysis of Double-Ended Guillotine Break Accident of Surge Line in ACP100 Based on Coupling Method: Development and Validation of the Coupling Method

The ACP100 is a small modular reactor (SMR) designed and built in China, featuring an integrated primary loop and passive safety systems. In SMRs, the interaction between the reactor coolant system, containment vessel, and other systems is highly interdependent. Therefore, it is necessary to use high-precision analysis codes, which can be achieved by coupling multiple codes. This paper is the first part of a study which investigates the LOCA in the ACP100 using a coupled platform. In this paper, a coupling platform was developed for transient analysis of SMR accidents, based on the system code NUSOL-SYS and the Integrated Severe Accident Analysis (ISAA) code. An inter-process communication module was developed adopting shared memory and event objects to exchange data between the two codes. A coupling interface defining the data to be exchanged was proposed. Both NUSOL-SYS and ISAA were modified to perform synchronous time step control. The coupling platform were validated through a hypothetical scenario and Edwards’ pipe blowdown experiment, demonstrating exact consistency and high accuracy. This coupling platform offers a new method for SMR accident analysis, providing a foundation for future work.

Software Model Checking Distributed Applications: A Hybrid Approach

Developing reliable distributed systems poses many challenges such as concurrency, failure handling, and scalability. It is due to the non-deterministic execution of threads within processes, and communication means. Formal verification methods, such as model checking, have been used to ensure the reliability of safety-critical systems. This technique systematically explores the complete behavior of the system under test (SUT), investigating each reachable state with different thread schedules. Recent software model-checking tools, employing cache and centralization, have been applied to distributed systems. The caching technique can only check one process at a time, while the centralization technique verifies all processes simultaneously. In the centralization technique, two "ArrayByteQueue" buffers are utilized to store communication and process data byte-by-byte. However, during the backtracking process, the read and write operations, involving data insertion and removal from the queue, become resource-intensive. As a consequence, existing interprocess communication (IPC) models encounter computational limitations and experience a rapid state space explosion. To address these challenges, our work proposes the remodeling of IPC models by introducing a request and response tree structure to store communication data. Additionally, we employ pointers to navigate through the data during the backtracking process. Through experimental evaluations, the proposed implementation choices have demonstrated significantly improved performance across various metrics. By incorporating the request and response tree, we enhance the efficiency of storing communication data, while the use of pointers optimizes navigation during backtracking. This remodeling of IPC models shows promise in mitigating computational limitations and state space explosion, thereby enhancing the model-checking process in distributed systems. Our research contributes to advancing the field of model checking in distributed systems and offers potential solutions to the challenges associated with resource-intensive read and write operations during the model-checking process.

Accelerating page loads via streamlining JavaScript engine for distributed learning

Distributed learning based on JavaScript-based frontends is typically implemented at the endpoint to maximize performance. Yet, JavaScript-based frontends often experience suboptimal performance. To reconcile these disparities in performance between EDGE and endpoint deployments, strategic optimization is essential, particularly for preserving privacy in distributed learning. Real-time streaming optimizations are imperative to align the performance of disparate components for smooth integration. The reliance on JavaScript for various web functionalities can lead to increased resource consumption and slower page loads. Thus, we introduce a streamlined JavaScript engine designed to optimize structural patterns in JavaScript code, with three key enhancements. Firstly, we reduce the computational burden of the JavaScript engine necessary for setting up the browser's runtime environment. Secondly, we refine the parsing process for specific code patterns, boosting the efficiency of our lightweight engine. Thirdly, we streamline the Inter-Process Communication (IPC) to maintain high performance, even with limited memory resources. Our evaluations demonstrate that our approach reduces the median Total Computation Time (TCT) by 45.2%, and surpasses existing leading solutions, Siploader and Prepack, with improvements ranging from 1.13× to 1.39×.

BRAND: a platform for closed-loop experiments with deep network models.

Objective.Artificial neural networks (ANNs) are state-of-the-art tools for modeling and decoding neural activity, but deploying them in closed-loop experiments with tight timing constraints is challenging due to their limited support in existing real-time frameworks. Researchers need a platform that fully supports high-level languages for running ANNs (e.g. Python and Julia) while maintaining support for languages that are critical for low-latency data acquisition and processing (e.g. C and C++).Approach.To address these needs, we introduce the Backend for Realtime Asynchronous Neural Decoding (BRAND). BRAND comprises Linux processes, termednodes, which communicate with each other in agraphvia streams of data. Its asynchronous design allows for acquisition, control, and analysis to be executed in parallel on streams of data that may operate at different timescales. BRAND uses Redis, an in-memory database, to send data between nodes, which enables fast inter-process communication and supports 54 different programming languages. Thus, developers can easily deploy existing ANN models in BRAND with minimal implementation changes.Main results.In our tests, BRAND achieved <600 microsecond latency between processes when sending large quantities of data (1024 channels of 30 kHz neural data in 1 ms chunks). BRAND runs a brain-computer interface with a recurrent neural network (RNN) decoder with less than 8 ms of latency from neural data input to decoder prediction. In a real-world demonstration of the system, participant T11 in the BrainGate2 clinical trial (ClinicalTrials.gov Identifier: NCT00912041) performed a standard cursor control task, in which 30 kHz signal processing, RNN decoding, task control, and graphics were all executed in BRAND. This system also supports real-time inference with complex latent variable models like Latent Factor Analysis via Dynamical Systems.Significance.By providing a framework that is fast, modular, and language-agnostic, BRAND lowers the barriers to integrating the latest tools in neuroscience and machine learning into closed-loop experiments.

A Parallel 3-D HIE-FDTD Method using the MPI Library

This paper presents the implementation of the parallel hybrid implicit-explicit finite-difference time-domain (HIE-FDTD) method using the Message Passing Interface (MPI) library. The method proves to be very effective in simulating large-scale three-dimensional electromagnetic problems with fine structures in one direction. For the decomposition of the computational volume in the HIE-FDTD method, an MPI Cartesian 2D topology is implemented, allowing arbitrary division of the volume in two directions. Derived data types provided in the MPI library are employed to optimize inter-process communication. High accuracy and efficiency are subsequently demonstrated through a numerical example of a frequency-selected surface (FSS). It shows that the proposed method is very suitable for parallel computing, and the parallel efficiency maintains above 80% for different numbers of processes.

Distributed Implementation of Full Configuration Interaction for One Trillion Determinants.

Full configuration interaction (FCI) can provide an exact molecular ground-state energy within a given basis set and serve as a benchmark for approximate methods in quantum chemical calculations, including the emerging variational quantum eigensolver. However, its exponential computational and memory requirements easily exceed the capability of a single server and limit its applicability to large molecules. In this paper, we present a distributed FCI implementation employing a hybrid parallelization scheme with multithreading and multiprocessing to expand FCI's applicability. We optimize this scheme to minimize the bottlenecks arising from interprocess communications and interthread data management. Our implementation achieves higher scalability than the naive combination of prior works and successfully calculates the exact energy of C3H8/STO-3G with 1.31 trillion determinants, which is the largest FCI calculation to the best of our knowledge. Furthermore, we provide a comprehensive list of FCI results with 136 combinations of molecules and basis sets for future evaluation and development of approximate methods.

Commissioning of the ALICE readout software for LHC Run 3

ALICE (A Large Ion Collider Experiment) is a heavy-ion detector studying the physics of strongly interacting matter and the quarkgluon plasma at the CERN LHC (Large Hadron Collider). During the second long shut-down of the LHC, the ALICE detector was upgraded to cope with an interaction rate of 50 kHz in Pb-Pb collisions, producing in the online computing system (O2) a sustained input throughput of 3.5 TB/s. In the past years, the O2/FLP project built the new data-acquisition system capable of handling this load. It consists of 200 readout nodes, collecting the data transferred from over 8000 detector links to PCs memory by dedicated PCI boards. The readout software manages the hardware and software memory buffers used for DMA and inter-process communication. It initiates the data flow, performs on-the-fly consistency checks, formats the data, reports performance, and finally pushes the data to the local processing pipeline. The output is then sent by the data distribution software over 100Gb/s links to a dedicated event processing farm. The readout software modular design allowed to address the manifold needs faced during the prototyping, installation and commissioning phases, which proved essential from the lab tests to physics production, like file replay and recording, or online multi-threaded LZ4 compression. We will describe the hardware and software implementation of the O2 readout system, and review the challenges met during the commissioning and first months of operation with LHC collisions in 2022.

An overview of the Legio fault resilience framework for MPI applications

While the computational power of HPC clusters breached through the exascale milestone, it highlighted the need for some critical features like fault management. The current de facto standard for inter-process communication at scale, MPI, lacks proper fault management functionalities, precluding result production in the presence of faults. Many efforts have already addressed the problem, with the ULFM extension and Reinit proposal being the two works receiving the most attention. While powerful and effective, they require expertise from the user and significantly impact the application code. For this reason, we presented the Legio fault resilience framework, which can introduce graceful degradation properties in MPI applications with minimal changes. This work summarises the development and evolution of Legio, highlighting successful use cases and providing some tips for users who want to leverage it for their executions.

ChamelIoT: a tightly- and loosely-coupled hardware-assisted OS framework for low-end IoT devices

The evergrowing Internet of Things (IoT) ecosystem continues to impose new requirements and constraints on every device. At the edge, low-end devices are getting pressured by increasing workloads and stricter timing deadlines while simultaneously are desired to minimize their power consumption, form factor, and memory footprint. Field-Programmable Gate Arrays (FPGAs) emerge as a possible solution for the increasing demands of the IoT. Reconfigurable IoT platforms enable the offloading of software tasks to hardware, enhancing their performance and determinism. This paper presents ChamelIoT, an agnostic hardware operating systems (OSes) framework for reconfigurable IoT devices. The framework provides hardware acceleration for kernel services of different IoT OSes by leveraging the RISC-V open-source instruction set architecture (ISA). The ChamelIoT hardware accelerator can be deployed in a tightly- or loosely-coupled approach and implements the following kernel services: thread management, scheduling, synchronization mechanisms, and inter-process communication (IPC). ChamelIoT allows developers to run unmodified applications of three well-established OSes, RIOT, Zephyr, and FreeRTOS. The experiments conducted on both coupling approaches consisted of microbenchmarks to measure the API latency, the Thread Metric benchmark suite to evaluated the system performance, and tests to the FPGA resource consumption. The results show that the latency can be reduced up to 92.65% and 89.14% for the tightly- and loosely-coupled approaches, respectively, the jitter removed, and the execution performance increased by 199.49% and 184.85% for both approaches.

A Design Flow for Scheduling Spiking Deep Convolutional Neural Networks on Heterogeneous Neuromorphic System-on-Chip

Neuromorphic systems-on-chip (NSoCs) integrate CPU cores and neuromorphic hardware accelerators on the same chip. These platforms can execute spiking deep convolutional neural networks (SDCNNs) with a low energy footprint. Modern NSoCs are heterogeneous in terms of their computing, communication, and storage resources. This makes scheduling SDCNN operations a combinatorial problem of exploring an exponentially-large state space in determining mapping, ordering, and timing of operations to achieve a target hardware performance, e.g., throughput. We propose a systematic design flow to schedule SDCNNs on an NSoC. Our scheduler, called SMART ( S DCNN MA pping, Orde R ing, and T iming), branches the combinatorial optimization problem into computationally-relaxed sub-problems that generate fast solutions without significantly compromising the solution quality. SMART improves performance by efficiently incorporating the heterogeneity in computing, communication, and storage resources. SMART operates in four steps. First, it creates a self-timed execution schedule to map operations to compute resources, maximizing throughput. Second, it uses an optimization strategy to distribute activation and synaptic weights to storage resources, minimizing data communication-related overhead. Third, it constructs an inter-processor communication (IPC) graph with a transaction order for its communication actors. This transaction order is created using a transaction partial order algorithm, which minimizes contention on the shared communication resources. Finally, it schedules this IPC graph to hardware by overlapping communication with the computation, and leveraging operation, pipeline, and batch parallelism. We evaluate SMART using 10 representative image, object, and language-based SDCNNs. Results show that SMART increases throughput by an average 23%, compared to a state-of-the-art scheduler. SMART is implemented entirely in software as a compiler extension. It doesn’t require any change in a neuromorphic hardware or its interface to CPUs. It improves throughput with only a marginal increase in the compilation time. SMART is released under the open-source MIT licensing at https://github.com/drexel-DISCO/SMART to foster future research.

Stochastic Gradient Descent for matrix completion: Hybrid parallelization on shared- and distributed-memory systems

The purpose of this study is to investigate the hybrid parallelization of the Stochastic Gradient Descent (SGD) algorithm for solving the matrix completion problem on a high-performance computing platform. We propose a hybrid parallel decentralized SGD framework with asynchronous inter-process communication and a novel flexible partitioning scheme to attain scalability up to hundreds of processors. We utilize Message Passing Interface (MPI) for inter-node communication and POSIX threads for intra-node parallelism. We tested our method by using different real-world benchmark datasets. Experimental results on a hybrid parallel architecture showed that, compared to the state-of-the-art, the proposed algorithm achieves 6× higher throughput on sparse datasets, while it achieves comparable throughput on relatively dense datasets.

Real-Time Guarantees in Routerless Networks-on-Chip

This article considers the use of routerless networks-on-chip as an alternative on-chip interconnect for multi-processor systems requiring hard real-time guarantees for inter-processor communication. It presents a novel analytical framework that can provide latency upper bounds to real-time packet flows sent over routerless networks-on-chip, and it uses that framework to evaluate the ability of such networks to provide real-time guarantees. Extensive comparative analysis is provided, considering different architectures for routerless networks and a state-of-the-art wormhole network based on priority-preemptive routers as a baseline.