Inter-processor Communication Overhead Research Articles

Energy and memory-aware software pipelining streaming applications on NoC-based MPSoCs

In this article, we explore the problem of energy-aware scheduling of real-time applications modelled by conditional task graphs on NoC based MPSoC such that the total energy consumption is minimized. We propose a novel energy and memory-aware retiming conditional task graph (EMRCTG) approach that integrates task-level coarse-grained software pipelining with Dynamic Voltage and Frequency Scaling (DVFS). Our approach not only optimizes energy consumption but ensures that memory capacity constraints are satisfied. EMRCTG has two phases. In the first phase, we map tasks to processors, transform intra-period data dependencies into inter-period and generate a schedule by a Non-Linear Programming (NLP)-based algorithm assuming infinite memory capacity. The NLP-based algorithm assigns a continuous frequency and voltage to each task and each communication and uses a polynomial-time heuristic to transform the continuous frequencies and voltages to discrete frequencies and voltages. We analyse the memory consumption of the generated schedule and initiate schedule repair phase 2 if the memory capacity constraints violate. The schedule repair phase finds a set of nodes such that by reducing their retiming values the memory capacity constraints satisfy.We compare our approach against two existing approaches GeneS and JCCTS. GeneS is a genetic algorithm that first transforms the dependent task set into an independent task set and then collectively performs task mapping, ordering and voltage scaling. JCCTS is a mixed integer linear programming based approach that optimally removes inter-processor communication overhead. Our experimental result show that compared to the approach GeneS our approach can obtain an improvement in range of 1.6 to 18 percent and an average improvement of 11 percent. Compared to the approach JCCTS our approach can achieve an improvement in range of 9 to 42 percent and an average improvement of 26 percent.

Generation of Frequent sensor epochs using efficient Parallel Distributed mining algorithm in large IOT

Numerous data mining algorithms are implemented using huge volume of sensor data to generate the frequent item sets that are useful in many aspects such as to predict the behavioural sensor patterns of future events and to detect the survival of sensors in large IOT . Traditional data mining algorithms transactional databases to produce the frequent patterns. Since the rate of input data arrival in large IOT varies, it becomes difficult to mine the dynamic sensor database. This work proposes an efficient algorithm known as Vertical Partitioning Parallel Distributed Algorithm(VPPDA) that uses MapReduce framework to mine sensor epochs to detect the survival of sensors using association rules formed by generated frequent patterns. The proposed VPPDA eliminates overhead of interprocess communication, by introducing overlapped window concept implemented in MapReduce framework combined with Vertical partitioning approach to get better progress in execution time and accurate results. Additionally pipelining processing has been implemented in MapReduce framework that still increases the performance and generates the frequent sensor epochs patterns. The concept of pipeline processing was introduced to minimize the execution time and also make the situation adaptable to any input rate of incoming sensor epochs.

Energy-Aware and Reliability-Aware Mapping for NoC-Based Architectures

Extensive research has been conducted on task scheduling and mapping on a multi-processor system on chip. The mapping strategy on a network on chip (NoC) has a huge effect on the communication energy and performance. This paper proposes an efficient core mapping for NoC-based architectures. Which focus on energy- aware and reliability-aware mapping issues for NoC-based architectures and considers new applications with insignificant inter-processor communication overhead to be added to the system. This methodology was assessed by applying it to various benchmark applications. Simulation results reveal that the proposed mapping algorithm greatly improves the reliability of the system and reduce the communication energy.

Reducing Inter-Process Communication Overhead in Parallel Sparse Matrix-Matrix Multiplication

Parallel sparse matrix-matrix multiplication algorithms (PSpGEMM) spend most of their running time on inter-process communication. In the case of distributed matrix-matrix multiplications, much of this time is spent on interchanging the partial results that are needed to calculate the final product matrix. This overhead can be reduced with a one-dimensional distributed algorithm for parallel sparse matrix-matrix multiplication that uses a novel accumulation pattern based on the logarithmic complexity of the number of processors (i.e., where is the number of processors). This algorithm's MPI communication overhead and execution time were evaluated on an HPC cluster, using randomly generated sparse matrices with dimensions up to one million by one million. The results showed a reduction of inter-process communication overhead for matrices with larger dimensions compared to another one dimensional parallel algorithm that takes run-time complexity for accumulating the results.

PSIN: A scalable, Parallel algorithm for Seismic INterferometry of large-N ambient-noise data

Seismic interferometry is a technique for extracting deterministic signals (i.e., ambient-noise Green's functions) from recordings of ambient-noise wavefields through cross-correlation and other related signal processing techniques. The extracted ambient-noise Green's functions can be used in ambient-noise tomography for constructing seismic structure models of the Earth's interior. The amount of calculations involved in the seismic interferometry procedure can be significant, especially for ambient-noise datasets collected by large seismic sensor arrays (i.e., “large-N” data). We present an efficient parallel algorithm, named pSIN (Parallel Seismic INterferometry), for solving seismic interferometry problems on conventional distributed-memory computer clusters. The design of the algorithm is based on a two-dimensional partition of the ambient-noise data recorded by a seismic sensor array. We pay special attention to the balance of the computational load, inter-process communication overhead and memory usage across all MPI processes and we minimize the total number of I/O operations. We have tested the algorithm using a real ambient-noise dataset and obtained a significant amount of savings in processing time. Scaling tests have shown excellent strong scalability from 80 cores to over 2000 cores.

WeNA: Deterministic Run-time Task Mapping for Performance Improvement in Many-core Embedded Systems

Many-core embedded systems will feature an extremely dynamic workload distribution where massive applications arranged as an unpredictable sequence enter and leave the system at run-time. Efficient mapping strategy is required to allocate system resources to the incoming application. Noncontiguous mapping improves system throughput by utilizing disjoint nodes, however, the increasing communication distance and external congestion lead to high power consumption and network delay. This paper thus presents an enhanced noncontiguous dynamic mapping algorithm, aiming at decreasing interprocessor communication overhead and improving both network and application performance. Communication volumes are utilized to arrange the mapping order of tasks belong to the same application. Moreover, expanding parameter of each task is developed which directs the optimized mapping decision comparing to the current neighborhood and occupancy information. Experimental results show that our modified mapping algorithm Weighted-based Neighborhood Allocation (WeNA) makes considerable improvements on Average Weighted Manhattan Distance (8.06%) and network latency (9.8%) in comparison with the state-of-the-art algorithm.

Data Partition and Communication On Parallel Heuristik Model Based on Clonal Selection Algorithm

Researchers conducted experiments on parallel algorithms, which are inspired by the clonal selection, called Clonal Selection Algorithm (CSA). This algorithm is a population-based heuristic solution. Course-grained parallelism model applied to improve the execution time. Inter-process communication overhead is addressed by adjusting the communication frequencies and size of data communicated. In this research, conducted experiments on six parallel computing models represent all possible partitions and communications. Experiments conducted using data of NP-Problem, Traveling Salesman Problem (TSP). The algorithm is implemented using the model of message passing libraries using MPJExpress. Experiments conducted in a cluster computation environment. Result shows the best parallelism model is achieved by partitioning the initial population data at the beginning of communication and the end of generation. Communication frequency can be up to per 1% of the population size generated. Using four dataset from TSPLib, this reseache shows effect of the communication frequency that increased the best cost, from 44.16% to 87.01% for berlin52.tsp; from 9.61% to 53.43% for kroA100.tsp, and from 12.22% to 17.18% for tsp225.tsp. With eight processors, using communication frequency will be reduced the execution time e.g 93.07%, 91.60%, 89.60%, 74.74% for burma14.tsp, berlin52.tsp, kroA100.tsp, and tsp225.tsp respectively. We conclude that frequency of communication greatly affects the execution time, and also the best cost. It improved execution time and best cost.

Fast Control Method of Software-Managed TLB for Reducing Zero-Copy Communication Overhead

SUMMARY Microkernel operating systems (OSes) use zero-copy communication to reduce the overhead of copying transfer data, because the communication between OS servers occurs frequently in the case of microkernel OSes. However, when a memory management unit manages the translation lookaside buffer (TLB) using software, TLB misses tend to increase the overhead of interprocess communication (IPC) between OS servers running on a microkernel OS. Thus, improving the control method of a software-managed TLB is important for microkernel OSes. This paper proposes a fast control method of software-managed TLB that manages page attachment in the area used for IPC by using TLB entries, instead of page tables. Consequently, TLB misses can be avoided in the area, and the performance of IPC improves. Thus, taking the SH-4 processor as an example of a processor having a software-managed TLB, this paper describes the design and the implementation of the proposed method for AnT oper

Hypergraph partitioning for multiple communication cost metrics: Model and methods

We investigate hypergraph partitioning-based methods for efficient parallelization of communicating tasks. A good partitioning method should divide the load among the processors as evenly as possible and minimize the inter-processor communication overhead. The total communication volume is the most popular communication overhead metric which is reduced by the existing state-of-the-art hypergraph partitioners. However, other metrics such as the total number of messages, the maximum amount of data transferred by a processor, or a combination of them are equally, if not more, important. Existing hypergraph-based solutions use a two phase approach to minimize such metrics where in each phase, they minimize a different metric, sometimes at the expense of others. We propose a one-phase approach where all the communication cost metrics can be effectively minimized in a multi-objective setting and reductions can be achieved for all metrics together. For an accurate modeling of the maximum volume and the number of messages sent and received by a processor, we propose the use of directed hypergraphs. The directions on hyperedges necessitate revisiting the standard partitioning heuristics. We do so and propose a multi-objective, multi-level hypergraph partitioner called UMPa. The partitioner takes various prioritized communication metrics into account, and optimizes all of them together in the same phase. Compared to the state-of-the-art methods which only minimize the total communication volume, we show on a large number of problem instances that UMPa produces better partitions in terms of several communication metrics.

Dynamic task partition for video decoding on heterogeneous dual-core platforms

This article presents the design of a video decoder using dynamic task partition approach on a heterogeneous dual-core embedded platform. For such systems, static task partition between the two cores at design time is a typical approach for application development. In this article, we propose a runtime dynamic task partition model and implement an MPEG-4 Simple Profile video decoder using this approach on a TI OMAP 5912 platform. Comparing with a traditional mobile video decoder optimized for the same DSP core, the performance gain from dynamic task partition is 38.4% on average. More importantly, the gain is achieved with the design constraint that the implementation effort for the dynamic task partition decoder is about the same as the effort using design-time task partition model. Unlike common belief that the inter-processor communication overhead would be too high to justify intense cooperation between two heterogeneous cores, this paper shows that it is indeed beneficial to adopt dynamic task partition model on commercially available heterogeneous multi-core platforms.

HICAMP

Programming language and operating system support for efficient concurrency-safe access to shared data is a key concern for the effective use of multi-core processors. Most research has focused on the software model of multiple threads accessing this data within a single shared address space. However, many real applications are actually structured as multiple separate processes for fault isolation and simplified synchronization. In this paper, we describe the HICAMP architecture and its innovative memory system, which supports efficient concurrency safe access to structured shared data without incurring the overhead of inter-process communication. The HICAMP architecture also provides support for programming language and OS structures such as threads, iterators, read-only access and atomic update. In addition to demonstrating that HICAMP is beneficial for multi-process structured applications, our evaluation shows that the same mechanisms provide substantial benefits for other areas, including sparse matrix computations and virtualization.

HICAMP

Programming language and operating system support for efficient concurrency-safe access to shared data is a key concern for the effective use of multi-core processors. Most research has focused on the software model of multiple threads accessing this data within a single shared address space. However, many real applications are actually structured as multiple separate processes for fault isolation and simplified synchronization. In this paper, we describe the HICAMP architecture and its innovative memory system, which supports efficient concurrency safe access to structured shared data without incurring the overhead of inter-process communication. The HICAMP architecture also provides support for programming language and OS structures such as threads, iterators, read-only access and atomic update. In addition to demonstrating that HICAMP is beneficial for multi-process structured applications, our evaluation shows that the same mechanisms provide substantial benefits for other areas, including sparse matrix computations and virtualization.

Redundancy Mining for Soft Error Detection in Multicore Processors

The trends in technology scaling and the reduction in supply voltages have significantly improved the performance and energy consumption in modern microprocessors. Microprocessors are being built with higher degrees of spatial parallelism and deeper pipelines to improve performance, which, however, makes them more susceptible to transient faults. Radiation causes "transient faults” or "single-event transients” in logic, which, once propagated and latched, become full cycle errors or soft errors. If radiation hits memory elements, this is usually called an "single-event upset” or "soft error” as it can further propagate as a full cycle error. The problem of soft errors is further exacerbated in large multiprocessors employed in servers in which reliability is a key concern. In the past, the technique of lockstep execution of the original and the duplicate instructions has been used for error detection in multiprocessors. However, the execution of redundant threads in the on-chip multiprocessor (CMP) provides error detection at lower overheads, since the branch outcomes of the leading thread can be exploited during the execution of the trailing thread, and also because the interprocessor communication latency is a key concern for lockstepping. In this paper, we show that by mining various redundancies inherent within a single core, the interprocessor communication can be brought down to a minimum. Toward this, we propose techniques based on 1) temporal redundancy, 2) data value redundancy, and 3) information redundancy for error detection in multicore designs. We exploit temporal redundancy by using the "latency slack cycles” (LSC) of an instruction, which we define as the number of cycles before the computed result from the instruction becomes the source operand of a subsequent instruction. The value-based detection technique is explored by exploiting the width of the operands with small data values and information redundancy is exploited by the generation of residue code check bits for the source operands. We show that with a clustered core multiprocessor, the interprocessor communication overhead can be significantly reduced. In our proposed multicore design, when a soft error is detected, error correction is achieved by rolling back the execution to a previous checkpoint state and re-executing the instructions. The proposed techniques have been implemented on the RSIM simulation framework and validated using the SPLASH benchmarks. Experimental results indicate that the soft error detection schemes proposed in this work, can be implemented, on the average, with less than 10 percent increase in CPI on modern multicore designs.

Multi-core platform for an efficient H.264 and VC-1 video decoding based on macroblock row-level parallelism

In order for the video decoding processing such as H.264 and VC-1 to be effective in multi-core environments, several kinds of parallelisms must be utilised. Here, a novel parallelisation methodology, macroblock row-level parallelism (MBRLP), of video decoding is presented. The ETRI multimedia processing core (EMC) and the ETRI multi-core platform (EMP) are proposed for adopting MBRLP. In terms of the scalability and utilisation of processing cores, MBRLP has advantages over other parallelisation strategies such as frame, slice and macroblock (MB)-level parallelism. The scalability can be easily achieved by just increasing the number of processing cores and applying homogeneous software design/optimisation techniques to each EMC. Instead of employing a dynamic MB-level scheduler, a hybrid approach is used, which is a two-stage functional pipelining combined with MBRLP. The hybrid approach of combining MBRLP and de-blocking pipelining can relieve the synchronisation and inter-processor communication overheads incurred by multicore decoding systems as well as run-time scheduler's overheads. As a result, the proposed parallelisation method and architectures can boost the performance with the efficiency of 83%. The proposed architecture consisting of six EMC clusters has the capability to process Dl (720 × 480) 30 fps real-time decoding at around 200 MHz. The same concept can be applied to full-HD (1920 × 1088) video decoding in this work. It can be found that as the number of processing cores increase, the performance improvement is enhanced almost linearly. The EMP consisting of four EMC clusters (eight cores), memories and other peripherals are prototyped on Xilinx Virtex4 XC4VL200 FPGA which is operating at 60 MHz.

Parallel and Distributed Algorithms for Frequent Pattern Mining in Large Databases

Mining frequent patterns (FP) from large-scale databases has emerged as an important problem in the data mining and knowledge discovery research community. A significant number of parallel and distributed FP mining algorithms have been proposed, when the database is large and/or distributed. Among them, parallelization of the FP-growth algorithm using the FP-tree has been proved to be more efficient, when compared to the Apriori -based approaches. However, the FP-tree based techniques suffer from two major limitations - multiple database scans requirement (i.e., high I/O cost) and huge communication overhead. Therefore, in this paper, we propose a novel tree structure, called PP-tree (Parallel Pattern tree) that significantly reduces the I/O cost by capturing the database contents with a single scan and facilitates efficient FP-growth mining on it. Our parallel algorithm works independently at each local site and merges the locally generated global frequent patterns at the final stage, thereby reducing inter-processor communication overhead and getting a high degree of parallelism. Extensive experimental study on datasets of different types reflects that parallel and distributed FP mining with our PP-tree is highly efficient on large databases.

Fine-grained parallelization of the Car-Parrinello ab initio molecular dynamics method on the IBM Blue Gene/L supercomputer

Important scientific problems can be treated via ab initio-based molecular modeling approaches, wherein atomic forces are derived from an energy function that explicitly considers the electrons. The Car–Parrinello ab initio molecular dynamics (CPAIMD) method is widely used to study small systems containing on the order of 10 to 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> atoms. However, the impact of CPAIMD has been limited until recently because of difficulties inherent to scaling the technique beyond processor numbers about equal to the number of electronic states. CPAIMD computations involve a large number of interdependent phases with high interprocessor communication overhead. These phases require the evaluation of various transforms and non-square matrix multiplications that require large interprocessor data movement when efficiently parallelized. Using the Charm++ parallel programming language and runtime system, the phases are discretized into a large number of virtual processors, which are, in turn, mapped flexibly onto physical processors, thereby allowing interleaving of work. Algorithmic and IBM Blue Gene/L™ system-specific optimizations are employed to scale the CPAIMD method to at least 30 times the number of electronic states in small systems consisting of 24 to 768 atoms (32 to 1,024 electronic states) in order to demonstrate fine-grained parallelism. The largest systems studied scaled well across the entire machine (20,480 nodes).

A high performance algorithm for static task scheduling in heterogeneous distributed computing systems

Effective task scheduling is essential for obtaining high performance in heterogeneous distributed computing systems (HeDCSs). However, finding an effective task schedule in HeDCSs requires the consideration of both the heterogeneity of processors and high interprocessor communication overhead, which results from non-trivial data movement between tasks scheduled on different processors. In this paper, we present a new high-performance scheduling algorithm, called the longest dynamic critical path (LDCP) algorithm, for HeDCSs with a bounded number of processors. The LDCP algorithm is a list-based scheduling algorithm that uses a new attribute to efficiently select tasks for scheduling in HeDCSs. The efficient selection of tasks enables the LDCP algorithm to generate high-quality task schedules in a heterogeneous computing environment. The performance of the LDCP algorithm is compared to two of the best existing scheduling algorithms for HeDCSs: the HEFT and DLS algorithms. The comparison study shows that the LDCP algorithm outperforms the HEFT and DLS algorithms in terms of schedule length and speedup. Moreover, the improvement in performance obtained by the LDCP algorithm over the HEFT and DLS algorithms increases as the inter-task communication cost increases. Therefore, the LDCP algorithm provides a practical solution for scheduling parallel applications with high communication costs in HeDCSs.

A note on scaling the Linpack benchmark

Dimensional analysis yields a new scaling formula for the Linpack benchmark. The computational power r ( p 0 , q 0 ) on a set of processors decomposed into a ( p 0 , q 0 ) grid determines the computational power r ( p , q ) on a set of processors decomposed into a ( p , q ) grid by the formula r ( p , q ) = ( p / p 0 ) α ( q / q 0 ) β r ( p 0 , q 0 ) . The two scaling parameters α and β measure interprocessor communication overhead required by the algorithm. A machine that scales perfectly corresponds to α = β = 1 ; a machine that scales not at all corresponds to α = β = 0 . We have determined the two scaling parameters by imposing a fixed-time constraint on the problem size such that the execution time remains constant as the number of processors changes. Results for a collection of machines confirm that the formula suggested by dimensional analysis is correct. Machines with the same values for these parameters are self-similar. They scale the same way even though the details of their specific hardware and software may be quite different.

High-Speed Distributed Video Transcoding for Multiple Rates and Formats

This paper describes a distributed video transcoding system that can simultaneously transcode an MPEG-2 video file into various video coding formats with different rates. The transcoder divides the MPEG-2 file into small segments along the time axis and transcodes them in parallel. Efficient video segment handling methods are proposed that minimize the inter-processor communication overhead and eliminate temporal discontinuities from the re-encoded video. We investigate how segment transcoding should be distributed to obtain the shortest total transcoding time. Experimental results show that implementing distributed transcoding on 10 PCs can decrease the total transcoding time by a factor of about 7 for single transcoding and by a factor of 9.5 for simultaneous three kinds of transcoding rates.

An Efficient Simulation Environment and Simulation Techniques for Bluetooth Device Design

Validation of an System-on-Chip (SoC) design with networking capability needs global simulation of the whole system including the network as well as the SoC design itself. Especially, it is needed to validate the interoperability of SoCs from different vendors. In this paper, we propose a simulation environment and simulation techniques for efficient validation of such SoC designs and apply them to networked Bluetooth SoC designs. The environment enables two types of simulation. One is modular enough to include the simulation of other vendors' Bluetooth devices and the other is optimized to achieve fast simulation in developing in-house Bluetooth devices. Especially, the former is scalable in that it keeps the constant simulation runtime despite the increase of the number of Bluetooth devices. Since multiple simulators are involved, the global simulation is still slow. Thus, the simulation efforts need to be minimized to shorten the design cycle. We present two simulation techniques, a concept called grouped message for reduction in simulation runtime and a system debug scenario called fix---modify---restart for reduction in the number of simulation runs. The former is to reduce inter-process communication overhead between simulators in the global simulation. The latter is to reduce repeated simulation runs in the conventional design cycle. Experimental results show the scalability of the presented simulation environment, reduction in simulation efforts by two simulation techniques.