Intelligent Platform Management Controller Research Articles

Novel developments on the OpenIPMC project

We present the recent developments in the context of the OpenIPMC project, which proposes a free and open-source Intelligent Platform Management Controller (IPMC) software and an associated controller mezzanine card for use in ATCA electronic boards. We discuss our experience in the operation of OpenIPMC on prototype boards designed for the upgrades of particle physics experiments at CERN and we show the addition of new features and support for new protocols in the firmware of the controller mezzanine card.

ZynqMP-based board-management mezzanines for Serenity ATCA-blades

In the context of the CMS Phase-2 tracker back-end processing system, two mezzanines based on the Zynq Ultrascale+ Multi-Processor System-on-Chip (MPSoC) device have been developed to serve as centralized slow control and board management solution for the Serenity-family Advanced Telecommunications Computing Architecture (ATCA) blades. This paper presents the developments of the MPSoC mezzanines to execute the Intelligent Platform Management Controller (IPMC) software in the real-time capable processors of the MPSoC. In coordination with the Shelf Manager, once full-power is enabled, a CentOS-based Linux distribution is executed in the application processors of the MPSoC, on which EMPButler and the Serenity Management Shell (SMASH) are running.

A flexible and low-cost open-source IPMC mezzanine for ATCA boards based on OpenIPMC

This work presents the development of an Intelligent Platform Management Controller mezzanine in a Mini DIMM form factor for use in electronic boards compliant to the PICMG Advanced Telecommunication Computing Architecture (ATCA) standard. The module is based on an STMicroelectronics STM32H745 microcontroller running the OpenIPMC open-source software. The mezzanine has been successfully tested on a variety of ATCA boards being proposed for the upgrade of the experiments at the HL-LHC, with its design and firmware being distributed under open-source hardware license.

OpenIPMC: A Free and Open-Source Intelligent Platform Management Controller Software

OpenIPMC is a free and open source firmware designed to operate as an Intelligent Platform Management Controller (IPMC). An IPMC is a fundamental component of electronic boards conformant to the Advanced Telecommunications Computing Architecture (ATCA) standard, currently being adopted by a number of high energy physics experiments, and is responsible for monitoring the health parameters of the board, managing its power states, and providing board control, debug and recovery functions to remote clients. OpenIPMC is based on the FreeRTOS real-time operating system and is designed to be architecture-independent, allowing it to be built for a variety of different Microcontrollers. Having a fully free and open source code is an innovative aspect for this kind of firmware, allowing full customization by the user. In this work we present the features and structure of OpenIPMC and its example implementations on Xilinx Zynq UltraScale+ (ZynqUS+), Espressif ESP32, and ST Microelectronics STM32 architectures.

Taking advantage of the intercommunication features of IPMCs in ATCA CDAQ systems

The PCI Industrial Computer Manufacturers Group (PICMG) 3.x AdvancedTCA Base Specification and Intelligent Platform Management Interface (IPMI) standards specify a modular system for Control and Data Acquisition (CDAQ) where the boards can communicate through the Intelligent Platform Management Bus-0 (IPMB-0).CDAQ systems applied to large physics experiments like ITER, are designed, among other features, for High-Availability (HA). A CDAQ system based on the PICMG 3.x AdvancedTCA Base Specification and IPMI standards grants these features. One of the key functions of the HA is the hot swapping possibility of the CDAQ system elements which is granted by those standards. An Advanced Telecommunications Computers Architecture (ATCA) CDAQ system can be designed implementing the Peripheral Component Interconnect Express (PCIe) standard communication protocol in their fabric lines. Despite the fact that this protocol has its own rules for hot swapping, defined as hot-plug, ATCA and PCIe standards are not entirely compatible in what concerns this aspect.Instituto de Plasmas e Fusão Nuclear (IPFN) has developed and implemented a CDAQ system using the ATCA and PCIe standards.This paper describes the software architecture and functions implemented in the microcontroller of the Intelligent Platform Management Controller (IPMC) of the ATCA boards in order to render those standards compatible in what concerns hot-swap and hot-plug processes as an example of the possibilities that can be achieved taking advantage of the intercommunication features of IPMCs through the Intelligent Platform Management Bus-0 (IPMB-0).

Design of an AdvancedTCA board management controller (IPMC)

The AdvancedTCA (ATCA) standard has been selected as the hardware platform for the upgrade of the back-end electronics of the CMS and ATLAS experiments of the Large Hadron Collider (LHC) . In this context, the electronic systems for experiments group at CERN is running a project to evaluate, specify, design and support xTCA equipment. As part of this project, an Intelligent Platform Management Controller (IPMC) for ATCA blades, based on a commercial solution, has been designed to be used on existing and future ATCA blades. This paper reports on the status of this project presenting the hardware and software developments.

Evaluation of a commercial AdvancedTCA board management controller solution (IPMC)

The MicroTCA (MTCA) and AdvancedTCA (ATCA) industry standards have been selected as the hardware platform for the upgrade of the electronic systems of some of the experiments at the Large Hadron Collider (LHC) . In this context, the electronics support group for experiments at CERN is running a project to perform technical evaluations of MTCA and ATCA equipment. As part of this activity, a commercial solution for an Intelligent Platform Management Controller (IPMC), an essential component of any ATCA blade design, is being evaluated. We validated the supported IPMC features, checked the interoperability and adapted the reference design for use on an existing ATCA carrier board.

Intelligent Platform Management Controller Software Architecture in ATCA Modules for Fast Control Systems

The Intelligent Platform Management Controller (IPMC) is one of the main elements in an Advanced Telecommunications Computing Architecture (ATCA) crate that is responsible for the ATCA/xTCA hardware management. Hardware failure detection, redundancy procedures and hot insertion/removal of the modules, are tasks that grant high-availability to a control and data acquisition system. So, IPFN/IST decided to develop software to an IPMC sodimm module from CoreIPM® and integrate it in the ATCA modules that are being developed aiming to be included in the instrumentation catalogue of tokamak ITER. This paper outlines the architecture and the main tasks that the software of the IPMC module executes.

Control and data acquisition ATCA/AXIe board designed for high system availability and reliability of nuclear fusion experiments

This paper describes the implementation and test of a control and data acquisition board designed to be integrated on systems demanding high availability and reliability, foreseen for future experiments like ITER or other long operation fusion devices. The Advanced Telecommunications Computing Architecture (ATCA) standard (PICMG 3.0 and 3.4) was selected for board implementation, which has support for the desired system robustness and performance. Some board features such as rear Input/Output (IO) signals connectivity (passive, copper tracks only), cable-less hot-swap maintenance, Intelligent Platform Management Controller (IPMC) and redundancy on timing signals, communications links and power supplies are significant board improvements, relatively to previous control and data acquisition boards, allowing the development of more reliable system architectures. Moreover, the developed board is also compatible with the emerging ATCA eXtensions for Instrumentation (AXIe) specifications, which provides additional timing and synchronization signals on the backplane. ATCA full-mesh, multi-gigabit, full-duplex, point-to-point communication links between Field Programmable Gate Arrays (FPGA), of peer boards inside the shelf, allow the implementation of distributed algorithms and development of Multi-Input Multi-Output (MIMO) systems. Up to 48 analog input channels, simultaneously digitized (2 MSPS @ 18-bits), are filtered/decimated by the board FPGA and sent to the ATCA/AXIe host through Peripheral Component Interconnect express (PCIe) using Direct Memory Access (DMA). In real-time, the host can update up to 48 analog output channels (1 MSPS @ 18-bits), per board, through PCIe. Further board characteristics comprise analog IO channels with galvanic isolation and an optional signal chopper mode, for offset compensation over time on digital integration of magnetic signals. Board time synchronization is attained by means of the Inter-Range Instrumentation Group (IRIG) time-code.

ATCA/AXIe compatible board for fast control and data acquisition in nuclear fusion experiments

An in-house development of an Advanced Telecommunications Computing Architecture (ATCA) board for fast control and data acquisition, with Input/Output (IO) processing capability, is presented. The architecture, compatible with the ATCA (PICMG 3.4) and ATCA eXtensions for Instrumentation (AXIe) specifications, comprises a passive Rear Transition Module (RTM) for IO connectivity to ease hot-swap maintenance and simultaneously to increase cabling life cycle.The board complies with ITER Fast Plant System Controller (FPSC) guidelines for rear IO connectivity and redundancy, in order to provide high levels of reliability and availability to the control and data acquisition systems of nuclear fusion devices with long duration plasma discharges.Simultaneously digitized data from all Analog to Digital Converters (ADC) of the board can be filtered/decimated in a Field Programmable Gate Array (FPGA), decreasing data throughput, increasing resolution, and sent through Peripheral Component Interconnect (PCI) Express to multi-core processors in the ATCA shelf hub slots. Concurrently the multi-core processors can update the board Digital to Analog Converters (DAC) in real-time. Full-duplex point-to-point communication links between all FPGAs, of peer boards inside the shelf, allow the implementation of distributed algorithms and Multi-Input Multi-Output (MIMO) systems. Support for several timing and synchronization solutions is also provided.Some key features are onboard ADC or DAC modules with galvanic isolation, Xilinx Virtex 6 FPGA, standard Dual Data Rate (DDR) 3 SODIMM memory, standard CompactFLASH memory card, Intelligent Platform Management Controller (IPMC), two PCI Express x4 (generation 2) ATCA Fabric channels (dual-star topology), eleven Xilinx Aurora x1 (or other ATCA compatible communications protocol) ATCA fabric channels (full-mesh topology) and two Fast Ethernet (Precision Time Protocol – PTP IEEE1588-V2 and Lan eXtensions for Instrumentation – LXI compatible) ATCA base channels (dual-star topology).

Real-Time IPMI Protocol Analyzer

The Advanced Telecommunications Computing Architecture (ATCA) is a modern platform, which gains popularity, not only in telecommunication applications, but also in others fields like High Energy Physics (HEP) experiments. Computing systems based on ATCA provide high performance and efficiency and are characterized by significant reliability, availability and serviceability. ATCA offers these features because of an integrated management system realized by the Intelligent Platform Management Interface (IPMI) implemented on dedicated Intelligent Platform Management Controller (IPMC). IPMC is required on each ATCA board to fulfill the ATCA standard and is responsible for many vital procedures performed to support proper operation of ATCA system. It covers, among others, activation and deactivations of modules, monitoring of actual parameters or controlling fans. The commercially available IPMI implementations are expensive and often not suited to demands of specific ATCA applications and available hardware. Thus, many research centers and commercial companies decide to develop their own version of IPMC software. Despite precise IPMI specification of communication requests and responses, these implementations are often incompatible with each other, which leads to incorrect in-system behavior of devices equipped with IPMCs from various vendors. ATCA specifies the I2C protocol as a physical layer of IPMI. There are many devices able to monitor the I2C bus such as logic analyzers or specialized oscilloscopes. However, there is no available equipment capable of debugging IPMI as a higher level protocol. The article compares available methods of IPMI debugging and describes a custom made device prepared to monitor in realtime up to eight IPMI lines and analyze the IPMI protocol. Accessibility of this kind of equipment allows to discover errors and find the reasons of faulty behavior of the IPMC under development, greatly reduce the time to market factor and decrease costs of ATCA system development.

Intelligent Platform Management Controller for Nuclear Fusion Fast Plant System Controllers

An Intelligent Platform Management Controller (IPMC) is being developed by IPFN/IST. This controller will be integrated in the Advanced Telecommunications Computing Architecture (ATCA) and Advanced Mezzanine Cards (AMC) modules that are under development for application in nuclear fusion experiments such as the ITER Fast Plant System Controller (FPSC) prototype. This controller in addition with the Shelf Manager module is responsible for the management of hardware failure, redundancy procedures, and hot swapping of the modules in the ATCA crate. The verification of compatibility between modules that share ATCA resources, the power management of each module, temperature monitoring, and fan control are, as well, tasks that the IPMC has the responsibility to manage. Other important functions of the controller are the programming of ATCA and AMC modules firmware, application specific program selection, and firmware version control. In this paper, the hardware architecture of the IPMC implementation at IPFN ATCA modules will be described.

Intelligent Platform-Management Controller for Low-Level RF Control System ATCA Carrier Board

High availability and reliability are among the most desirable features of control systems in modern high-energy physics (HEP) and other big-scale scientific experiments. One of the recent developments that has influenced this field has been the emergence of the Advanced Telecommunications Computing Architecture (ATCA). Designed for the telecommunications industry, it has been successfully applied in other domains, such as accelerator control systems. A good example is the application of ATCA standard for the design of the low-level RF (LLRF) control system for the X-Ray Free Electron Laser (XFEL) being developed in Deutsches Elektronen Synchrotron (DESY). Reliability and availability requirements for such a facility play a crucial role among other parameters. Thus, the ATCA standard, with five-nines availability, is considered to be one of the best candidates for this system. This paper focuses on the central-management unit of every ATCA board, namely, the intelligent platform-management controller (IPMC), developed for the LLRF ATCA carrier board. It is also argued that it is possible to create a fully functional IPMC using base specifications which is only a more economical solution than acquiring such products from ATCA vendors. This work supports the concept of an open-source community solution under the xTCA for physics collaboration dealing with IPMC/MMC development and wishes to contribute to it. The IPMC solution presented here is mainly hardware independent as proper code organization allowed to separate low-level device drivers and high-level application logic dealing with the ATCA standard, which makes it portable for new carrier-board designs. It also follows the latest trends in xTCA development introduced by the xTCA for Physics initiative. A firmware upgrade of programmable devices (field-programmable gate arrays and digital signal processors) has been proposed. Currently, this is not included in the standard. However, this functionality is needed in HEP applications by using xTCA and is useful in these cases.