Intel XScale Research Articles

Customization of GPRS, and Wi-Fi device drivers for PXA270 of Linux OS based barcode scanner

To access any device, it is necessary to have an access point. A device driver is an entry point to access a device. This project is aimed to customize the Wi-Fi and general packet radio service (GPRS) device drivers in Linux OS for PXA270 (Intel Xscale ARM processor). Customizing a device driver is a special way of designing software that can be more easily ported from one architecture to another without rewriting it from scratch. The paper is discussing about the customisation of Wi-Fi and GPRS device driver in Linux OS for PXA270 (Intel Xscale ARM processor). To develop a device driver, it is necessary to understand the processor architecture and Linux kernel internals and other design constraints. Since dynamically loaded driver module is attached to the existing kernel, and any error in the driver will crash the entire system. Resource allocation and implementation for a device is one of the main concerns for device driver developers. The device resources are input/output, memory, IRQs and ports. The required toolchain to build the cross-complier for the Intel Xscale ARM processor was built on Linux platform. The customised device drivers of Wi-Fi, and GPRS was customised, and the customised images are made to port for PXA270 processor architecture on EMX-270 board. With all the supporting parameters the kernel images with drivers are build and ported efficiently. Also, a successful verification and testing had been performed for their functionalities.

Pemanfaatan ED-255EK Embedded Education Platform sebagai Modul Praktikum Embedded System Berbasis Linux

The development of embedded systems is of particular concern to the field of technology. Embedded systems have been widely applied in everyday life, such as automatic washing machines, electric stoves, radios, and so forth. So as to give indirect demands to understand the basic configuration of the application of embedded system itself. Learning about the basics of embedded system application can be done using ED-255EK Embedded Education Platform. ED-255EK is powered by an Intel XScale PXA255 CPU that is compatible with ARM Version 5TE ISA, Linux operating system, adopts RISC super-pipeline, and operates at 200/300/400 Mhz with low power consumption. How to operate ED-255EK is to configure the operating system first, such as package upgrades, network configuration and serial communication. Followed by configuration on ED-255EK which includes downloading file system and setting IP Address. The final step is the configuration of the module, which includes the installation of driver files and application programs, so that the input data provided will be displayed on the ED-255EK module and serialized also displayed on the laptop screen. The modules used are LED, LCD, DOT-Matrix, FND, Key-pad, DIP-Switch, Motor Stepper, IrDA, RF, and uWave modules.

The Research of the Real-Time High-Resolution Image Acquisition Based on Embedded System

This paper presents the design of a real-time high-definition image acquisition. The hardware platform combines Intel Xscale PXA270 processor, high-resolution camera and SAA7114H. The system is based on the embedded Linux system. Beetween the image sensor and the system memory,there is a quick capture interface.The interface receives the data from the image sensor,and converts the raw image data to a suitable format, and sends H.264 stream to the memory via the DMA channel. The result shows that the design can realize the real-time and high-definition image acquisition in a complicated environment. The advantage of this system is small volume, low power consumption and low cost. It can be widely used in agricultural and hydrological monitoring, intelligent transportation, security monitoring and intelligent home.

A Mobile-Based Face Verification System

Intelligent mobile phones equipped with a camera are very popular in our daily lives now. Face verification running on mobile phone provides not only a tool for the protection of the owner's authority but also an approach for verification from a distance. The combination of biometrics and telecommunication technologies possesses broad application potentials in information exchanges. However, there are also some critical issues needing solving. Usually the processing power and memory size of a mobile phone system are limited, and the acquisition images are suffered from the illumination changes. An acquisition image I(x,y) can be modeled as a product of the reflectance R and Illuminant effect L shown as I(x,y) = R(x,y)∗L(x,y). The reflectance attribution R(x,y) is the inherent feature of a human face for verification. Compared with the reflectance changes rapidly across the contour of a face, usually the illumination changes smoothly and slowly. If two pixels are located nearby, the ratio of the reflectance between these two pixels can be calculated via the ratio of their illuminations, which is approximately independent from illumination changes. Based on this invariant property of the ratio of illumination at a pixel to its surrounding neighbor illuminations, an illumination normalization technique was developed and adapted to the mobile system. A dedicated scheme composed of special wavelets called Gab features was proposed for representation of human faces. Gabor features reveal more structure information of images; however, the data dimensionality is becoming very high. An optimization processing was designed for searching the optimal Gabor node configuration and reducing the number of Gabor nodes effectively. To fit the limitation of the phone processor, all the floating point calculations were implemented with integer calculations, the feature extraction and discriminating verification algorithms were carefully designed to accelerate implementation and control the heap and stack sizes. A mobile based face verification system was developed and embedded in the Lenovo ET980 mobile phone, which is equipped with CPU Intel XScale PX270, memory 128MB Flash/64 MB SDRAM, and a 4 million pixel camera. The experiments testing on FERET fafb dataset show that the system Equal False Accept Rate and False Reject Rate achieved 1.51%; and the False Accept Rates achieved 2.12% and 6.81%, while the False Reject Rate at 1% and 0.1% respectively. The processing time is about 1 second. The performance of this system is quite well.

Fault tolerant aggregation in heterogeneous sensor networks

Fault tolerance and scalability are important considerations in the design of sensor network applications. Data aggregation is an essential operation in sensor networks. Multiple techniques have been proposed recently to tackle the issues of scalability and fault tolerance of aggregation in sensor networks. In this article, we analyze the impact of using a few of the more reliable, though expensive, nodes–such as the Intel XScale–called microservers, in addition to the standard motes, on the fault tolerance and scalability of the aggregation algorithms in sensor networks. In particular, we propose a simple model that captures the essence of tree aggregation in such heterogeneous sensor networks. We validate this theoretical model with simulation results. We also study the effective impact on the sustainable probability of failure, and perform cost-benefit analysis. We also show how hybrid aggregation can be utilized instead of tree, to improve the performance of aggregation in heterogeneous sensor networks. We show that our work can be applied for effectively optimizing the use of expensive hardware while designing fault-tolerant, distributed sensor networks.

Register File Power Reduction Using Bypass Sensitive Compiler

This paper explores, develops, and investigates several bypass-sensitive compilation techniques to reduce the register file power by reducing the access frequency to the register file. We study the effectiveness of our techniques on the Intel XScale processor, which is based on the previously proposed ldquoon-demand register fetch readrdquo architectural feature. Furthermore, we show that our bypass-sensitive compilation technique is effective on various partial bypass configurations.

Accurate and fast system-level power modeling

Accurate and fast system modeling is central to the rapid design space exploration needed for embedded-system design. With fast, complex SoCs playing a central role in such systems, system designers have come to require MIPS-range simulation speeds and near-cycle accuracy. The sophisticated simulation frameworks that have been developed for high-speed system performance modeling do not address power consumption, although it is a key design constraint. In this paper, we define a simulation-based methodology for extending system performance modeling frameworks to also include power modeling. We demonstrate the use of this methodology with a case study of a real, complex embedded system, comprising the Intel XScale embedded microprocessor, its WMMX SIMD co processor, L1 caches, SDRAM, and the on-board address and data buses. We describe detailed power models for each of these components and validate them against physical measurements from hardware, demonstrating that such frameworks enable designers to model both power and performance at high speeds without sacrificing accuracy. Our results indicate that the power estimates obtained are accurate within 5% of physical measurements from hardware, while simulation speeds consistently exceed a million instructions per second (MIPS).

Effects of Instruction-Set Extensions on an Embedded Processor: A Case Study on Elliptic Curve Cryptography over GF(2/sup m/)

Elliptic-Curve cryptography (ECC) is promising for enabling information security in constrained embedded devices. In order to be efficient on a target architecture, ECCs require accurate choice/tuning of the algorithms that perform the underlying mathematical operations. This paper contributes with a cycle-level analysis of the dependencies of ECC performance from the interaction between the features of the mathematical algorithms and the actual architectural and microarchitectural features of an ARM-based Intel XScale processor. Another contribution is the cycle-level analysis of a modified ARM processor that includes a word-level finite field polynomial multiplier (poly_mul) in its data path. This extension constitutes a good trade-off between applicability in a number of contexts, the simplicity of integration within the processor, and performance. This paper points out the most advantageous mix of elliptic curve (EC) parameters both for the standard ARM-based Intel XScale platform and for the one equipped with the polyjnul unit. In particular, the latter case allows for more than 41 percent execution time reduction on the considered benchmarks. Last, this paper investigates the correlation between the possible architectural organizations of a processor equipped with poly_mul unit(s) and EC benchmark performance. For instance, only superscalar pipelines can exploit the features of out-of-order execution and only very complex organizations (for example, four way superscalar) can exploit a high number of available ALUs. Conversely, we show that there are no benefits in endowing the processor with more than one poly_mul, and we point out a possible trade-off between performance and complexity increase: A two-way in-order/out-of-order pipeline allows +50 percent and +90 percent of Instructions per Cycle (IPC), respectively. Finally, we show that there are no critical constraints on the latency and pipelining capability of the polyjnul unit for the basic EC point multiplication.

Automatic Design Space Exploration of Register Bypasses in Embedded Processors

Register bypassing is a popular and powerful architectural feature to improve processor performance in pipelined processors by eliminating certain data hazards. However, extensive bypassing comes with a significant impact on cycle time, area, and power consumption of the processor. Recent research therefore advocates the use of partial bypassing in a processor. However, accurate performance evaluation of partially bypassed processors is still a challenge, primarily due to the lack of bypass-sensitive retargetable compilation techniques. No existing partial bypass exploration framework estimates the power and area overhead of partial bypassing. As a result, the designers end up making suboptimal design decisions during the exploration of partial bypass design space. This paper presents PBExplore - an automatic design-space-exploration framework for register bypasses. PBExplore accurately evaluates the performance of a partially bypassed processor using a bypass-sensitive compilation technique. It synthesizes the bypass control logic and estimates the area and energy overhead of each bypass configuration. PBExplore is thus able to effectively perform multidimensional exploration of the partial bypass design space. We present experimental results of benchmarks from the MiBench suite on the Intel XScale architecture on and demonstrate the need, utility, and exploration capabilities of PBExplore.

Accurate and fast system-level power modeling

Accurate and fast system modeling is central to the rapid design space exploration needed for embedded-system design. With fast, complex SoCs playing a central role in such systems, system designers have come to require MIPS-range simulation speeds and near-cycle accuracy. The sophisticated simulation frameworks that have been developed for high-speed system performance modeling do not address power consumption, although it is a key design constraint. In this paper, we define a simulation-based methodology for extending system performance-modeling frameworks to also include power modeling. We demonstrate the use of this methodology with a case study of a real, complex embedded system, comprising the Intel XScale®g embedded microprocessor, its WMMX™ SIMD coprocessor, L1 caches, SDRAM and the on-board address and data buses. We describe detailed power models for each of these components and validate them against physical measurements from hardware, demonstrating that such frameworks enable designers to model both power and performance at high speeds without sacrificing accuracy. Our results indicate that the power estimates obtained are accurate within 5% of physical measurements from hardware, while simulation speeds consistently exceed a million instructions per second (MIPS).

The XTREM power and performance simulator for the Intel XScale core

Managing power concerns in microprocessors has become a pressing research problem across the domains of computer architecture, CAD, and compilers. As a result, several parameterized cycle-level power simulators have been introduced. While these simulators can be quite useful for microarchitectural studies, their generality limits how accurate they can be for any one chip family. Furthermore, their hardware focus means that they do not explicitly enable studying the interaction of different software layers, such as Java applications and their underlying runtime system software. This paper describes and evaluates XTREM, a power-simulation tool tailored for the Intel XScale microarchitecture. In building XTREM, our goals were to develop a microarchitecture simulator that, while still offering size parameterizations for cache and other structures, more accurately reflected a realistic processor pipeline. We present a detailed set of validations based on multimeter power measurements and hardware performance counter sampling. XTREM exhibits an average performance error of only 6.5% and an even smaller average power error: 4%. The paper goes on to present an application study enabled by the simulator. Namely, we use XTREM to produce an energy consumption breakdown for Java CDC and CLDC applications. Our simulator measurements indicate that a large percentage of the total energy consumption (up to 35%) is devoted to the virtual machine's support functions.

A VLIW Processor With Hardware Functions: Increasing Performance While Reducing Power

This brief presents a heterogeneous multicore embedded processor architecture designed to exceed performance of traditional embedded processors while reducing the power consumed compared to low-power embedded processors. At the heart of this architecture is a multicore very large instruction word (VLIW) containing homogeneous execution cores/functional units. Additionally, heterogeneous combinational hardware function cores are tightly integrated to the VLIW core providing an opportunity for improved performance and reduced energy consumption. Our processor has been synthesized for both a 90-nm Stratix II field-programmable gate array and a 160-nm cell-based application-specific integrated circuit from Oki each operating at a core frequency of 167 MHz. For selected multimedia and signal processing benchmarks, we show how this processor provides kernel performance improvements averaging 179X over an Intel StrongARM and 36X over an Intel XScale leading to application speedups averaging 30X over StrongARM and 10X over XScale

Retargetable pipeline hazard detection for partially bypassed processors

Register bypassing is a widely used feature in modern processors to eliminate certain data hazards. Although complete bypassing is ideal for performance, it has significant impact on the cycle time, area, and power consumption of the processor. Owing to the strict design constraints on the performance, cost, and the power consumption of embedded processor systems, architects seek a compromise between the design parameters by implementing partial bypassing in processors. However, partial bypassing in processors presents challenges for compilation. Traditional data hazard detection and/or avoidance techniques used in retargetable compilers that assume a constant value of operation latency, break down in the presence of partial bypassing. In this article, we present the concept of operation tables (OTs) that can be used to accurately detect data hazards, even in the presence of incomplete bypassing. OTs integrate the detection of all kinds of pipeline hazards in a unified framework, and can, therefore, be easily deployed in a compiler to generate better schedules. Our experimental results on the popular Intel XScale embedded processor running embedded applications from the MiBench suite, demonstrate that accurate pipeline hazard detection by OTs can result in up to 20% performance improvement over the best performing GCC generated code. Finally, we demonstrate the usefulness of OTs over various bypass configurations of the Intel XScale

Bypass aware instruction scheduling for register file power reduction

Since register files suffer from some of the highest power densities within processors, designers have investigated several architectural strategies for register file power reduction, including "On Demand RF Read" where the register file is read only if the operand value is not available from the bypasses. However, we show in this paper that significant additional reductions in the register file power consumption can be obtained by scheduling instructions so that they transfer the operands via bypasses, rather than reading from the register file. Such instruction scheduling requires the compiler to be cognizant of the bypasses in the processor pipeline. In this paper, we develop several bypass aware instruction scheduling heuristics varying in time complexity, and study their effectiveness on the Intel XScale processor pipeline running MiBench benchmarks. Our experimental results show additional power consumption reductions of up to 26% and on average 12% over and above the register file power reduction achieved through existing techniques.

Page mapping for heterogeneously partitioned caches: Complexity and heuristics

Embedded processors such as the Intel StrongARM SA-1110 and the Intel XScale utilize multiple caches at the same level in the cache hierarchy. The main cache and the mini-cache differ in both the s...

Specification and analysis of power-managed systems

Dynamic power management encompasses several techniques for reducing energy dissipation in electronic systems by selective slowdown or shutdown of components. We present a theoretical framework for explaining and classifying different approaches to power management. Within this framework, we model power-manageable components, workloads, and controllers as discrete-event systems (DESs). The structure of these DESs is specified in terms of physical states (representing operation modes) and events (triggering state transitions), while system behavior is specified in terms of next-event and next-state functions. In particular, nondeterministic next-event and next-state functions are modeled by conditional probability distributions, according to generalized semi-Markov processes (GSMPs). The modeling framework provides a general denotational model for system specification and a rigorous execution semantics that enables event-driven simulation. We introduce a modeling framework, built on top of MathWork's Simulink, supporting the specification and execution of our model. In particular, we present templates for the Simulink simulator to execute GSMP models, and we describe how to use such templates for specifying, analyzing, and optimizing dynamic power-managed systems. Finally, we demonstrate the expressive power and versatility of the proposed approach by using the modeling framework and the simulator for the analysis of representative real-life case studies, including the Intel Xscale processor architecture, a multitasking real-time system, and a sensor network.

XTREM

Managing power concerns in icroprocessors has become a pressing research problem across the domains of computer architecture, CAD, and compilers. As a result, several parameterized cycle-level power simulators have been introduced. While these simulators can be quite useful for microarchitectural studies, their generality limits how accurate they can be for any one chip family. Furthermore, their hardware focus means that they do not explicitly enable studying the interaction of different software layers, such as Java applications and their underlying Runtime system software.This paper describes and evaluates XTREM, a power simulation tool tailored for the Intel XScale icroarchitecture. In building XTREM, our goals were to develop a icroarchitecture simulator that, while still offering size parameterizations for cache, TLB, etc., more accurately reflected a realistic processor pipeline. We present a detailed set of validations based on ultimeter power measurements and hardware performance counter sampling. Based on these validations across a wide range of stressmarks, Java benchmarks, and non-Java benchmarks, XTREM has an average performance error of only 6.5% and an even smaller average power error: 4%. The paper goes on to present a selection of application studies enabled by the simulator. For example, presenting power behavior vs. time for selected embedded C and Java CLDC benchmarks, we can make power distinctions between the two programming domains as well as distinguishing Java application (JITted code) power from Java Runtime system power. We also study how the Intel XScale core 's power consumption varies for different data activity factors, creating power swings as large as 50mW for a 200Mhz core. We are planning to release XTREM for wider use, and feel that it offers a useful step forward for compiler and embedded software designers.

A workload characterization of elliptic curve cryptography methods in embedded environments

Elliptic Curve Cryptography (ECC) is emerging as an attractive public-key system for constrained environments, because of the small key sizes and computational efficiency, while preserving the same security level as the standard methodsWe have developed a set of benchmarks to compare standard and corresponding elliptic curve public-key methods. An embedded device based on the Intel XScale architecture, which utilizes an ARM processor core was modeled and used for studying the benchmark performance. Different possible variations for the memory hierarchy of such basic architecture were considered. We compared our benchmarks with MiBench/Security, another widely accepted benchmark set, to provide a reference for our evaluation.We studied operations and impact on memory of Diffie-Hellman key exchange, digital signature algorithm, ElGamal, and RSA public-key cryptosystems. Elliptic curve cryptosystems are more efficient in terms of execution time, but their impact on memory subsystem has to be taken into account when designing embedded devices in order to achieve better performance.

Compile-time dynamic voltage scaling settings

With power-related concerns becoming dominant aspects of hardware and software design, significant research effort has been devoted towards system power minimization. Among run-time power-management techniques, dynamic voltage scaling (DVS) has emerged as an important approach, with the ability to provide significant power savings. DVS exploits the ability to control the power consumption by varying a processor's supply voltage (V) and clock frequency (f). DVS controls energy by scheduling different parts of the computation to different (V, f) pairs; the goal is to minimize energy while meeting performance needs. Although processors like the Intel XScale and Transmeta Crusoe allow software DVS control, such control has thus far largely been used at the process/task level under operating system control. This is mainly because the energy and time overhead for switching DVS modes is considered too large and difficult to manage within a single program.In this paper we explore the opportunities and limits of compile-time DVS scheduling. We derive an analytical model for the maximum energy savings that can be obtained using DVS given a few known program and processor parameters. We use this model to determine scenarios where energy consumption benefits from compile-time DVS and those where there is no benefit. The model helps us extrapolate the benefits of compile-time DVS into the future as processor parameters change. We then examine how much of these predicted benefits can actually be achieved through optimal settings of DVS modes. This is done by extending the existing Mixed-integer Linear Program (MILP) formulation for this problem by accurately accounting for DVS energy switching overhead, by providing finer-grained control on settings and by considering multiple data categories in the optimization. Overall, this research provides a comprehensive view of compile-time DVS management, providing both practical techniques for its immediate deployment as well theoretical bounds for use into the future.

An embedded 32-b microprocessor core for low-power and high-performance applications

An embedded RISC microprocessor core fabricated in a six-layer metal 0.18-/spl mu/m CMOS process implementing the ARM/sup TM/ V.5TE instruction set is described. The core described is the first implementation of the Intel XScale Microarchitecture/sup TM/. The microprocessor core, which includes caches, memory management units, and a bus controller, comprises a hard-embedded block 16.77 mm/sup 2/ in size. The implementation is primarily custom logic in a variety of circuit styles. The processor dissipates 450 mW at 1.3 V, 600 MHz, and scales between 55 mW at 0.7 V, 200 MHz, and 900 mW at 1.65 V 800 MHz. Architectural performance is 1000 MIPS at 800 MHz with efficiency ranging from over 850 MIPS/W at 1.65 V to over 4500 MIPS/W at 0.75 V. Architectural and circuit design approaches for low power and high performance are described and measured results from the initial implementation are shown. The first implementation VLSI chip has a 3.3-V pin interface and supports a 0.75-1.65-V core voltage range.