Intel Xeon Processor Research Articles

“Whispering MLaaS”

While recent advancements of Deep Learning (DL) in solving complex real-world tasks have spurred their popularity, the usage of privacy-rich data for their training in varied applications has made them an overly-exposed threat surface for privacy violations. Moreover, the rapid adoption of cloud-based Machine-Learning-asa-Service (MLaaS) has broadened the threat surface to various remote side-channel attacks. In this paper, for the first time, we show one such privacy violation by observing a data-dependent timing side-channel (naming this to be Class-Leakage) originating from non-constant time branching operation in a widely popular DL framework, namely PyTorch. We further escalate this timing variability to a practical inference-time attack where an adversary with user level privileges and having hard-label black-box access to an MLaaS can exploit Class-Leakage to compromise the privacy of MLaaS users. DL models have also been shown to be vulnerable to Membership Inference Attack (MIA), where the primary objective of an adversary is to deduce whether any particular data has been used while training the model. Differential Privacy (DP) has been proposed in recent literature as a popular countermeasure against MIA, where inclusivity and exclusivity of a data-point in a dataset cannot be ascertained by definition. In this paper, we also demonstrate that the existence of a data-point within the training dataset of a DL model secured with DP can still be distinguished using the identified timing side-channel. In addition, we propose an efficient countermeasure to the problem by introducing constant-time branching operation that alleviates the Class-Leakage. We validate the approach using five pre-trained DL models trained on two standard benchmarking image classification datasets, CIFAR-10 and CIFAR-100, over two different computing environments having Intel Xeon and Intel i7 processors.

Efficient real-time selective genome sequencing on resource-constrained devices.

Third-generation nanopore sequencers offer selective sequencing or "Read Until" that allows genomic reads to be analyzed in real time and abandoned halfway if not belonging to a genomic region of "interest." This selective sequencing opens the door to important applications such as rapid and low-cost genetic tests. The latency in analyzing should be as low as possible for selective sequencing to be effective so that unnecessary reads can be rejected as early as possible. However, existing methods that employ a subsequence dynamic time warping (sDTW) algorithm for this problem are too computationally intensive that a massive workstation with dozens of CPU cores still struggles to keep up with the data rate of a mobile phone-sized MinION sequencer. In this article, we present Hardware Accelerated Read Until (HARU), a resource-efficient hardware-software codesign-based method that exploits a low-cost and portable heterogeneous multiprocessor system-on-chip platform with on-chip field-programmable gate arrays (FPGA) to accelerate the sDTW-based Read Until algorithm. Experimental results show that HARU on a Xilinx FPGA embedded with a 4-core ARM processor is around 2.5× faster than a highly optimized multithreaded software version (around 85× faster than the existing unoptimized multithreaded software) running on a sophisticated server with a 36-core Intel Xeon processor for a SARS-CoV-2 dataset. The energy consumption of HARU is 2 orders of magnitudes lower than the same application executing on the 36-core server. HARU demonstrates that nanopore selective sequencing is possible on resource-constrained devices through rigorous hardware-software optimizations. The source code for the HARU sDTW module is available as open source at https://github.com/beebdev/HARU, and an example application that uses HARU is at https://github.com/beebdev/sigfish-haru.

Direction-optimizing Label Propagation Framework for Structure Detection in Graphs: Design, Implementation, and Experimental Analysis

Label Propagation is not only a well-known machine learning algorithm for classification but also an effective method for discovering communities and connected components in networks. We propose a new Direction-optimizing Label Propagation Algorithm (DOLPA) framework that enhances the performance of the standard Label Propagation Algorithm (LPA), increases its scalability, and extends its versatility and application scope. As a central feature, the DOLPA framework relies on the use of frontiers and alternates between label push and label pull operations to attain high performance. It is formulated in such a way that the same basic algorithm can be used for finding communities or connected components in graphs by only changing the objective function used. Additionally, DOLPA has parameters for tuning the processing order of vertices in a graph to reduce the number of edges visited and improve the quality of solution obtained. We present the design and implementation of the enhanced algorithm as well as our shared-memory parallelization of it using OpenMP. We also present an extensive experimental evaluation of our implementations using the LFR benchmark and real-world networks drawn from various domains. Compared with an implementation of LPA for community detection available in a widely used network analysis software, we achieve at most five times the F-Score while maintaining similar runtime for graphs with overlapping communities. We also compare DOLPA against an implementation of the Louvain method for community detection using the same LFR-graphs and show that DOLPA achieves about three times the F-Score at just 10% of the runtime. For connected component decomposition, our algorithm achieves orders of magnitude speedups over the basic LP-based algorithm on large-diameter graphs, up to 13.2× speedup over the Shiloach-Vishkin algorithm, and up to 1.6× speedup over Afforest on an Intel Xeon processor using 40 threads.

Energy Efficiency of a New Parallel PIC Code for Numerical Simulation of Plasma Dynamics in Open Trap

The generation of energy-efficient parallel scientific codes became very important in the time of carbon footprint reduction. In this paper, we briefly present our latest particle-in-cell code with the results of a numerical simulation of plasma dynamics in an open trap. This code can be auto-vectorized by the Fortran compiler for Intel Xeon processors with AVX-512 instructions such as Intel Xeon Phi and the highest series of all generations of Intel Xeon Scalable processors. Efficient use of processor architecture is the main feature of an energy-efficient solution. We present a step-by-step methodology of energy consumption calculation using Intel hardware features and Intel VTune software. We also give an estimated value of carbon footprint with the impact of high-performance water cooled hardware. The Power Usage Effectiveness (PUE) in the case of high-performance water cooled hardware is equal to 1.03–1.05, and is up to 1.3 in the case of air-cooled systems. This means that power consumption of liquid cooled systems is lower than that air-cooled ones by up to 25%. All these factors play an important role in the carbon footprint reduction problem.

High-Level Synthesis Implementation of an Embedded Real-Time HEVC Intra Encoder on FPGA for Media Applications

High Efficiency Video Coding (HEVC) is the key enabling technology for numerous modern media applications. Overcoming its computational complexity and customizing its rich features for real-time HEVC encoder implementations, calls for automated design methodologies. This article introduces the first complete High-Level Synthesis (HLS) implementation for HEVC intra encoder on FPGA. The C source code of our open-source Kvazaar HEVC encoder is used as a design entry point for HLS that is applied throughout the whole encoder design process, from data-intensive coding tools like intra prediction and discrete transforms to more control-oriented tools such as context-adaptive binary arithmetic coding (CABAC). Our prototype is run on Nokia AirFrame Cloud Server equipped with 2.4 GHz dual 14-core Intel Xeon processors and two Intel Arria 10 PCIe FPGA accelerator cards with 40 Gigabit Ethernet. This proof-of-concept system is designed for hardware-accelerated HEVC encoding and it achieves real-time 4K coding speed up to 120 fps. The coding performance can be easily scaled up by adding practically any number of network-connected FPGA cards to the system. These results indicate that our HLS proposal not only boosts development time, but also provides previously unseen design scalability with competitive performance over the existing FPGA and ASIC encoder implementations.

Performance exploration of various C/C++ compilers for AMD EPYC processors in numerical modeling of solidification

The phase-field (PF) method is a powerful tool for solving interfacial problems in materials science. This paper’s primary goal is to assess the impact of various state-of-the-art C/C++ compilers available for novel AMD EPYC Rome and Milan multi-core processors on the performance of real-world scientific codes corresponding to the solidification modeling application using the PF method and generalized finite difference scheme for solving governing PDEs. Among the studied compilers are AOCC, Clang, GCC, Intel compiler, and PGI. Besides performance, the numerical accuracy of the simulation is verified since various optimizations used by the compilers can cause differences in the simulation results. For the objectivity of the assessment, we study different application versions with the increasing complexity of memory access patterns and control structures. All tested codes are executed on a dual-socket server equipped with 64-core AMD EPYC Rome 7742 CPUs.This assessment confirms the advantage of the Intel compiler over other compilers. In particular, while for the static intensity only GCC lags noticeably behind other compilers, in the case of the dynamic intensity, the clear winner is the Intel compiler, which allows increasing the performance up to about 1.3 times over the AMD compiler. Moreover, we reveal the sensitivity of the application version and compiler to selecting a different number of NUMA domains and enabling/disabling the NUMA balancing option in EPYC processors. By comparing the performance gain achieved by various compilers due to vectorization of the application codes, we show that the Intel compiler’s performance advantage results primarily from considerably better utilization of capabilities of AVX2 vector instructions. Finally, we show the importance of choosing a compiler when comparing the performance of AMD EPYC and Intel Xeon processors.

Analysis of shock wave-boundary layer interaction in a shock tube using higher order scheme

Over the last couple of decades, the shock-wave boundary-layer interaction has gained a lot of attention due to its practical importance in many engineering applications. It is a complex problem involving shock-wave bifurcation, boundary-layer separation, the interaction of contact discontinuity with the shock wave, the formation of shocklets, and the evolution of vortical structures having different length scales. It is difficult to capture experimentally the detailed flow field having the shocklets and vortices. Numerical solvers having negligible numerical dissipation are highly essential to predict these structures accurately. Over the years, many researchers have obtained a grid-converged solution for shock-wave boundary-layer interaction at Reynolds numbers of 200 and 1000. The shock-wave boundary-layer interaction at higher Reynolds numbers is not attempted due to the requirement of huge computational resources and challenges associated with convergence. In the investigation, the grid-converged solution is obtained for a Reynolds number of 2500 with a 13th order high-resolution hybrid scheme using 100 cores of a computational cluster equipped with 3.0 GHz Intel Xeon processors incorporating the MPI library for parallelization. The complex flow field is analysed in detail using wall density, density gradient, vorticity, pressure, and enstrophy plots after validating the solver with the benchmark wall pressure, density, and v-velocity around the primary vortex provided by Zhou et al. (2018), Phys. Fluids, 30, 016102 for a Reynolds number 1000. It is observed that the triple point height and number of vortices in both separated zone and at the shear layer increase with an increase in Reynolds number. The grid-converged data obtained from the present simulation can be used as benchmark data to validate different numerical schemes/solvers at higher Reynolds numbers.

A CCSD(T)-Based 4-Body Potential for Water.

High-level, ab initio calculations find that the 4-body (4-b) interaction is needed to account for near-100% of the total interaction energy for water clusters as large as the 21-mer. Motivated by this, we report a permutationally invariant polynomial potential energy surface (PES) for the 4-body interaction. This machine-learned PES is a fit to 2119 symmetry-unique, CCSD(T)-F12a/haTZ 4-b interaction energies. Configurations for these come from tetramer direct-dynamics calculations, fragments from an MD water simulation at 300 K, and tetramer fragments in a variety of water clusters. The PIP basis is purified to ensure that the PES goes rigorously to zero in monomer+trimer and dimer+dimer dissociations. The 4-b energies of isomers of the hexamer calculated with the new PES are shown to be in better agreement with benchmark CCSD(T) results than those from the MB-pol potential. Tests on larger clusters further validate the high-fidelity of the PES. The PES is shown to be fast to evaluate, taking 2.4 s for 105 evaluations on a single core of 2.4 GHz Intel Xeon processor, and significantly faster using a parallel version of the PES.

Deep sequence to sequence learning-based prediction of major disruptions in ADITYA tokamak

Major disruptions in tokamak plasmas need to be identified well before their occurrence and appropriately mitigated. Otherwise, it may dump the heat and electromagnetic load to the vessel and its surrounding plasma-facing components. A predictor system based on precursor diagnostics may help in forecasting the disruptive events in tokamak plasma and raise the alert beforehand to take necessary actions to prevent the major damages inside the vacuum vessel. This paper describes a predictor system built with a few selected diagnostic signals from the ADITYA tokamak and trained on a time-sequence long short-term memory network to predict the occurrence of disruption to 7–20 ms in advance with an accuracy of 89% on the testing set of 36 disruptive and 6 non-disruptive shots. This real-time network can infer to one time-step results under 170 µs on an Intel Xeon processor running python, suggesting minimal computation cost and best suited for the real-time plasma control applications.

Impregnation quality diagnosis in Resin Transfer Moulding by machine learning

In recent years, several optimization strategies have been developed which reduce the overall defectiveness of the RTM manufactured part. RTM filling simulations showed that, even using optimized injection strategies, local variations in permeability could still generate local defects in the part. Such defects must be identified quickly and accurately right after the injection phase in order to repair or scrap the part. The present paper analyses the feasibility of diagnosing the quality after the injection stage of RTM parts by Machine Learning. The diagnosis was performed using a Supervised Learning binary classification model trained with synthetic data set. Among the different predictive models studied, Extreme Gradient Boosting and Light Gradient Boosting Machine were the most accurate models for predicting the filling quality of RTM, with an accuracy of 84.9% and 83.35%, respectively. In addition, a scaling of the ML model allowed not only to predict the quality of the part but also to locate the areas where the defect was generated. The computation time of the trained ML model versus the FEM model, both computed with a workstation (CPU Intel Xeon Processor E5.2690 with 2.9 GHz–8 core), were compared. In the specific case studied, a reduction from 360 s to 1 s was observed in the computation time utilizing the trained ML model. Thus, Supervised Learning predictive models can be used for diagnosing the composite quality. They are fast enough to be integrated in real processes and could be helpful for designing the monitoring system.

Evaluating the performance of FFT library implementations on modern hybrid computing systems

Fast Fourier transform is widely used to solve numerous scientific and engineering problems. In particular, this transform is behind the software dealing with speech and image recognition, signal analysis, modeling of properties of new materials and substances, etc. Newly emerging high-performance hybrid computing systems, as well as systems with alternative architectures, require research on discrete Fourier transform computation efficiency on these new platforms. The results of such research allow assessing the feasibility of certain solutions for building modern computing and data processing centers. This paper presents the results of such research covering modern hybrid computing systems based on the IBM POWER and Intel Xeon processors, as well as on NVIDIA Tesla co-processors. The analysis is carried out, and conclusions are presented on their performance when executing fast Fourier transforms. The impact of the existing architectural aspects of the hardware (CPU simultaneous multithreading mode, GPU data transfer bus, etc.) on the transform performance efficiency is assessed. The obtained results are used to provide recommendations on the optimal operation modes and settings of the considered mathematical libraries.

Portability and Acceleration of Deep Learning Inferences to Detect Rapid Earthquake Damage From VHR Remote Sensing Images Using Intel OpenVINO Toolkit

Accurate and effective rapid detection in remote sensing images plays an extremely important role in natural disasters, landslides, flooding problems, and military defense. Specially in earthquake damage detection, time critical tasks, such as performing the damage assessment or providing immediate delivery of relief assistance, require responses for swift decisions. To minimize response time, this article proposes the portability and acceleration of the inferences process on a deep convolution neural network model to detect rapid earthquake damage on very high resolution (VHR) remote sensing data using the Intel OpenVINO toolkit. This model, based on a previous work, has been optimized for high performance computing techniques to minimize processing times. Along with the immediate responses, the correctness of the result is also very crucial parameter for such type of applications. For analysis and performance, we use the GeoEye-1 VHR disaster images of the Haiti earthquake occurred in year 2010. Experimental results show that the optimized model provides good accuracy for damage detection with significant execution speed on CPU+GPU using mixed precision technique compared to other previous work. Moreover, OpenVINO toolkit presents satisfactory performance in the inference stage compared to other toolkits, such as TensorFlow serving, using asynchronous inference mode executed on an Intel Xeon processor and Intel Movidius NCS as coprocessor.

Performance analysis of CUDA, OpenACC and OpenMP programming models on TESLA V100 GPU

Graphics processors are widely utilized in modern supercomputers as accelerators. Ability to perform efficient parallelization and low-level allow scientists to greatly boost performance of their codes. Modern Nvidia GPUs feature low-level approaches, such as CUDA, along with high-level approaches: OpenACC and OpenMP. While the low-level approach aims to explore all possible abilities of SIMT GPU architecture by writing low-level C/C++ code, it takes significant effort from programmer. OpenACC and OpenMP programming models are opposite to CUDA. Using these models the programmer only have to identify the blocks of code to be parallelized using pragmas. We compare the performance of CUDA, OpenMP and OpenACC on state-of-the-art Nvidia Tesla V100 GPU in various typical scenarios that arise in scientific programming, such as matrix multiplication, regular memory access patterns and evaluate performance of physical simulation codes implemented using these programming models. Moreover, we study the performance matrix multiplication implemented in vendor-optimized BLAS libraries for Nvidia Tesla V100 GPU and modern Intel Xeon processor.

Cross-platform implementation of Particle-In-Cell method for simulation of high-temperature and fusion plasma by means of hybrid supercomputers equipped with GPU or Intel Xeon Phi accelerators

A new Python-based Particle-In-Cell code is presented. The code uses leapfrog particle pusher. The important feature of our code is that all the particles are pushed at once, thus the code is vectorized to improve performance. Electric field is given by Poisson equation with Least squares solver. The code involves collision simulation by PIC-MC method. Both large-scale (MPI) and fine-grain parallelization are being used. The implementation is based on the efficient NumPy library in Python language with the help of Dask package to improve Numpy performance. GPU implementation involves PyCUDA and the performance with Intel Xeon processors and Intel Xeon Phi accelerators is supported by high-performance Intel Python.

Performance analysis of parallel high‐resolution image restoration algorithms on Intel supercomputer

SummaryIn this article, we present an experimental performance study of a parallel implementation of two Poissonian image restoration algorithms. Hybrid parallelization, based on MPI and OpenMP standards, is investigated. The implementation is tested for high‐resolution radiographic images, on a supercomputer based on Intel Xeon processors, combined with Intel Xeon Phi coprocessors. The experimental results show an essential improvement in the execution times, when running experiments for a variety of problem sizes, and number of threads.

An FPGA Based Accelerator for Clustering Algorithms With Custom Instructions

Clustering algorithms are becoming popular and widely applied in many academic fields, such as machine learning, pattern recognition, and artificial intelligence. It has posed significant challenges to accelerate the algorithms due to the explosive data scale and wide variety of applications. However, previous studies mainly focus on the raw speedup with insufficient attention to the flexibility of the accelerator to support various applications. In order to accelerate different clustering algorithms in one accelerator, in this article, we design an accelerating framework based on FPGA for four state-of-the-art clustering methods, including K-means, PAM, SLINK, and DBSCAN algorithms. Moreover, we provide both euclidean and Manhattan distances as similarity metrics in the accelerator design paradigm. Moreover, we provide a custom instruction set to operate the accelerators within each application. In order to evaluate the performance and hardware cost of the accelerator, we constructed a hardware prototype on the state-of-the-art Xilinx FPGA platform. Experimental results demonstrate that the accelerator framework is able to achieve up to 23× speedup than Intel Xeon processor, and is 9.46× more energy efficient than NVIDIA GTX 750 GPU accelerators.

Put an elephant into a fridge

In today's data centers, memory-based key-value systems, such as Memcached and Redis, play an indispensable role in providing high-speed data services. The rapidly growing capacity and quickly falling price of DRAM memory in the past years have enabled us to create a large memory-based key-value store, which is able to serve hundreds of Gigabytes to even Terabytes of key-value data all in memory. Unfortunately, CPU cache in modern processors has not seen a similar growth in capacity, still remaining at the level of a few dozens of Megabytes. Such an extremely low cache-to-memory ratio (less than 0.1%) poses a significant new challenge---the limited CPU cache is becoming a severe performance bottleneck that hinders us from fully exploiting the great potential of high-speed memory-based key-value stores. To address this critical challenge, we propose a highly cache-efficient scheme, called Cavast , to optimize the cache utilization of large-capacity in-memory key-value stores. Our goal is to maximize cache efficiency and system performance without any hardware changes. We first present two light-weight, software-only mechanisms to enable user to indirectly control the cache content at application level. Then we propose a set of optimization policies to address several critical design issues that impair cache's efficacy in the current key-value store systems. By carefully reorganizing the data layout in memory, redesigning the hash indexing structure, and offloading garbage collection, we can effectively improve the utilization of the limited cache space. We have developed a module in Linux as a kernel-level support, and implemented two prototypes based on Memcached and Redis with the proposed Cavast scheme. Our experimental studies show promising results. On a 6-core Intel Xeon processor with only 15-MB cache, we can raise the cache hit ratio up to 82.7% with a very small cache-to-memory ratio (0.023%), and significantly increase the key-value system throughput by a factor of up to 4.2.

Production Application Performance Data Streaming for System Monitoring

In this article, we present an approach to streaming collection of application performance data. Practical application performance tuning and troubleshooting in production high-performance computing (HPC) environments requires an understanding of how applications interact with the platform, including (but not limited to) parallel programming libraries such as Message Passing Interface (MPI). Several profiling and tracing tools exist that collect heavy runtime data traces either in memory (released only at application exit) or on a file system (imposing an I/O load that may interfere with the performance being measured). Although these approaches are beneficial in development stages and post-run analysis, a systemwide and low-overhead method is required to monitor deployed applications continuously. This method must be able to collect information at both the application and system levels to yield a complete performance picture.In our approach, an application profiler collects application event counters. A sampler uses an efficient inter-process communication method to periodically extract the application counters and stream them into an infrastructure for performance data collection. We implement a tool-set based on our approach and integrate it with the Lightweight Distributed Metric Service (LDMS) system, a monitoring system used on large-scale computational platforms. LDMS provides the infrastructure to create and gather streams of performance data in a low overhead manner. We demonstrate our approach using applications implemented with MPI, as it is one of the most common standards for the development of large-scale scientific applications.We utilize our tool-set to study the impact of our approach on an open source HPC application, Nalu. Our tool-set enables us to efficiently identify patterns in the behavior of the application without source-level knowledge. We leverage LDMS to collect system-level performance data and explore the correlation between the system and application events. Also, we demonstrate how our tool-set can help detect anomalies with a low latency. We run tests on two different architectures: a system enabled with Intel Xeon Phi and another system equipped with Intel Xeon processor. Our overhead study shows our method imposes at most 0.5% CPU usage overhead on the application in realistic deployment scenarios.

A WORK DISTRIBUTION STRATEGY FOR GLOBAL SEQUENCE ALIGNMENT

The sequence alignment comprises to identify similarities and dissimilarities between two given sequences. In this paper, we propose a work distribution strategy for the implementation of DNA global sequence alignment. The main objective of this work is to minimize the execution time required for DNA global alignment of large biological sequences. The proposed approach dealt the issues with the memory optimizations and minimization of execution time. We considered the biological sequences of different size to fit into the global memory of the system. The proposed strategy is implemented in shared memory architecture using OpenMP programming for large biological sequences. Parallelization using OpenMP directive is relatively easy and execute the code fast. We experimented on the Dell Precision Tower 7910 with Intel Xeon processor with 32GB RAM and 28 CPU cores. The efficient use of global memory and cache memory optimization dominate the results of execution time. The results demonstrate the significantly high speed up using OpenMP as compared with other implementations.

4K Real Time Software Solution of Scalable HEVC for Broadcast Video Application

Scalable high-efficiency video coding (SHVC) is the scalable extension of the high-efficiency video coding (HEVC) standard. SHVC enables spatial, quality, bit-depth, color gamut, and codec scalability. The architecture of the SHVC encoder is based on multiple instances of the HEVC encoder where each instance encodes one video layer. This architecture offers several advantages of being modular and close to the native HEVC coding block scheme. However, the close-loop SHVC architecture requires the complete decoding of the reference lower layer frames to decode a higher quality layer, which considerably increases the complexity of both encoder and decoder processes. In this paper, we propose an end-to-end 4K real-time SHVC solution, including both software encoder and decoder, for video broadcast applications. The SHVC codec relies on low-level optimizations for specific Intel ×86 platform and parallel processing to speed up the encoding and decoding processes. The proposed encoder enables real-time processing of 4Kp30 video in 2× spatial scalabilities on the 4 × 10 cores Intel Xeon processor (E5-4627V3) running at 2.6 GHz. In addition, the SHVC decoder enables to decode, respectively, the lower quality layer in full HD (1920 × 1080p30) resolution, an advanced RISC machine (ARM) Neon mobile platform, and the enhancement layer in UHD (3840 × 2160p30), on a fitted laptop, with 4 cores Intel i7 processor running at 2.7 GHz. Finally, experimental results have shown that the proposed solution can reach a high rate-distortion performance close to the reference SHVC reference software model (SHM) with a speedup of 37 and 66 in intra and inter coding configurations.