Intel IXP Research Articles

Research of IPv6 High Performance Router Based on IXP2400

With a variety of new services, the rapid development of Internet network technology and people's demand, the scale and performance of the rapid growth of the network, the network information on the data processing must provide the required quality of service and maintenance management, solve the problems in the development of high speed network. This paper gives a detailed analysis of the hardware structure, system architecture and programming model of Intel IXP2400 network processor, the network processor to carry on the exploration of IPv6 high performance router design technology based on network processor, first understand the characteristics and functions, then introduces the network processor design to comply with a series of standards and their scope of application, and then combined with the basic principle of common the comparison of IPv4 and IPv6 router, router, the final analysis of the IPv6 network processor in the future will cause rapidly popularization, represent the core function unit of the next generation network device, there must be a great space for development.

Dynamically Reconfigurable Queue for Intel IXP2400 Network Processor

Network Processor (NP) is a programmable processor, which is used for packet processing in Network applications. Nowadays, many vendors are manufacturing different models of NPs for various applications. The major difference between each model is the number of microengines (ME), which varies from 6 to 32 (e.g., 6 or 8 or 16 or 32). The main objective of the Dynamic Reconfiguration in this work, is to optimize the usage of MEs depending on the network traffic fluctuation. The usage of MEs is either increased or decreased depending on the packet queue length. This paper proposes a new queuing system for dynamically reconfigurable NPs for traffic fluctuation. The number of MEs used, is dynamically increased when the queue size was increased by k packets and it was dynamically decreased when queue size reduced. We have used Intel IXP2400 NP for validating the queuing model for different traffic fluctuations.

Performance analysis of a hierarchical switched network architecture

In an effort to solve the problems encountered by the current internet, we have proposed an original hierarchical switched network HSNet architecture with the new address structure and hierarchical switching and controlling protocols including a per-flow load-balancing algorithm for HSNet. To evaluate the effectiveness and accuracy of the proposed architecture and the load-balancing algorithm, this paper conducts extensive NS-2 simulation experiments. Furthermore, we prototype the switching equipment of HSNet based on the Intel IXP2800 Network Processor and test the equipment by virtue of the professional measuring instrument, i.e., Agilent N2X. In addition to the simulation experiments, a test-bed of HSNet is then built based on the developed switching equipments. Both the simulation and real experimental results demonstrate that the per-flow load balancing algorithm can effectively balance the load on network channels for HSNet, and the developed switching equipment can achieve a high throughput.

Special issue on intelligent e‐services

The ubiquitous nature of the World Wide Web (WWW) coupled with the flexibility and agility associated with Software Services is one of the primary contributing factors in the development and deployment of intelligent (Software) e-services. The applications of these intelligent e-services span a number of domains such as manufacturing, transportation, and health. The aim of this special issue (SI) is to present some of the cutting-edge research done in this area. In response to the call-for-papers for this SI, more than 40 submissions were received. After thorough peer-review process, which spanned multiple rounds, six papers were selected. The first paper of this special issue, authored by Casado et al. 1, proposes an abstract web-services transaction model. The advantage of this abstract transaction model is that various specific transaction models can be derived from it. The authors validate the proposed abstract transaction model and conclude that their approach can be used to define different test cases in order to test the reliability and failures of different Web Services (WS) Transaction standards. The second paper of this special issue, authored by Flahive et al. 2, proposes a dynamic methodology for reusing, extracting, and updating ontology in a semantic grid environment. Mathematical formulations covering various aspects of ontology extraction and updating have been proposed. A case study based on the Unified Medical Language System ontology is used for validation of the proposed methodology. The third paper of this special issue, authored by Kołodziej et al. 3, proposes three different genetic algorithms (GA)-based energy-aware scheduling methods in computational grids. The proposed approach makes use of two parameters, namely, dynamic voltage and frequency scaling model for modeling the overall grid energy usage. For validation purposes, the performance of the three GA-based approaches was tested under various parameters. The results demonstrate the robustness of the proposed GA-based schedulers in optimizing the energy usage of the grid clusters. The fourth paper of this special issue addresses an interesting decision-making problem in distributed environments—bilevel decision making. This paper, authored by Lu et al. 4, outlines a set of rules for bilevel decision making. The authors use a case study to demonstrate the validity and applicability of the proposed rule-based approach. They additionally carry out experiments to demonstrate the effectiveness of the proposed method in finding a solution to a bilevel decision problem. The fifth paper of this special issue proposes an intelligent profiling-based task scheduling approach for multicore network processors. A key objective of the proposed approach by Tang et al. 5 is to optimize the system throughput under a given set of system parameters. In the past few years, various web-based applications that leverage multicore processors have emerged. The proposed approach has been validated by implementing it on the Intel IXP network processor. Simulation results demonstrate both the feasibility and the applicability of the proposed task-scheduling approach. The final paper of this special issue, authored by Xhafa et al. 6, presents an intelligent e-service for content management in a peer-to-peer environment. The design of the e-service is grounded on a super-peer architecture. The proposed e-service dynamically and efficiently replicates documents (as XML files) and data to support group-based processes in large and distributed environments. Extensive experimentation is carried out under various scenarios (using JXTA). In concluding this editorial, I would like to thank everyone involved in bringing this special issue to this fruition. I would like to thank all the authors who submitted their manuscripts for consideration in this special issue. Additionally, I would like to thank all the reviewers in providing high-quality reviews to the authors. In particular, I would like to thank Professor Geoffrey Fox, the editor-in-chief of this journal for his strong encouragement and support. This special issue would not come to its fruition without his support.

A profiling based task scheduling approach for multicore network processors

SummaryMulticore network processors have been playing an increasingly important role in computational processes, which emphasize on scalability and parallelism of the systems, in distributed environments especially in Internet‐based delay‐sensitive applications. It is an important but unsolved issue, however, to efficiently schedule tasks in network processors with multicore and multithread for improving the system throughput as much as possible. Profiling can gather runtime environment information and guide the compiler to optimize programs through scheduling tasks based on the runtime context. This paper proposes a profiling‐based task scheduling approach, targeting on improving the throughput of multicore network processor (Intel IXP) systems in the balanced pipeline way. In this work, we investigate a profiling‐based task scheduling framework, a task scheduling algorithm, and a set of performance models. Our task allocation scheme maps tasks onto the pipeline architecture and multiple threads of network processors in parallel, which incorporates the profiling context and global thread refinement. We evaluate our task scheduling algorithm by implementing representative network applications on the Intel IXP network processor. Experimental results demonstrate that our algorithm is able to schedule tasks in a balanced pipeline fashion and achieve the high throughput and data transmission rate. Copyright © 2012 John Wiley & Sons, Ltd.

Active Network Based Queue Management for Providing QoS Using IXP 2400 Network Processor

The objective of this paper is to implement the Active Network based Active Queue Management Technique for providing Quality of Service (QoS) using Network Processor (NP) based router to enhance multimedia applications. The performance is evaluated using Intel IXP2400 NP Simulator. The results demonstrate that, Active Network based Active Queue Management has better performance than RED algorithm and is well suited to achieve high speed packet classification to support multimedia applications with minimum delay and Queue loss. Using simulation, we show that the proposed system can provide assurance for prioritized flows with improved network utilization where bandwidth is shared among the flows according to the levels of priority. We first analyze the feasibility and optimality of the load distribution schemes and then present separate solutions for non-delaysensitive streams and delay-sensitive streams. Rigorous simulations and experiments have been carried out to evaluate the performance.

Network Applications on Simultaneous Multithreading Processors

As network applications become increasingly sophisticated and Internet traffic is getting heavier, future network processors must continue processing computation-intensive network applications at line rates. Most programmable network processors on the market today, such as the Intel IXP2800, target relatively low performance (from 100 Mbps to 10 Gbps). However, low cost edge routers will find it hard to cope with the forthcoming sophistication of network applications to be processed at those speeds. Hence, new architectures should be designed for the programmable network processors of the future. The goal of this paper is to evaluate the applicability and efficiency of Simultaneous MultiThreaded (SMT) as the base architecture of a network processor. Indeed, the SMT model inherently allows the multiple parallel threads which must be dealt with in network processor applications. In this paper, we investigate the architectural implications of network applications on the SMT architecture. We demonstrate that, when executed as independent threads, applications chosen from different network layers show an improved Instructions Per Cycle (IPC) and cache behavior when compared with the situation where the program executed comes from a single network application. Finally, a new architectural solution to cope with packet dependency is proposed and evaluated.

Evaluation of Router Implementations for Explicit Congestion Control Schemes

Explicit congestion control schemes use router feedback to overcome limitations of the standard mechanisms of the Transmission Control Protocol (TCP). These approaches require additional packet processing in every router and therefore raise the question whether, and how, this can be achieved in high-speed routers. This paper investigates the realization complexity of these router functions of two such schemes, the TCP Quick-Start extension and the Explicit Control Protocol (XCP). Our focus lies on the implementation using a network processor. We show that synchronization issues among parallel processing entities have to be considered, and that this affects the router performance. We develop and compare different synchronization mechanisms for highly parallel packet processing. Our prototype implementation on an Intel IXP network processor allows to quantify the impact on throughput and delay caused by the additional packet processing in the fast path. The measurements reveal that Quick-Start and XCP processing is feasible at multiple Gbit/s line speed, with Quick-Start being simpler to scale. We expect similar results for the implementation of the Rate Control Protocol (RCP), which is another router-assisted congestion control scheme, requiring no elaborate synchronization. Finally, we study the implementation using programmable logic and show the applicability of XCP and in particular Quick-Start even at significantly higher line speeds.

A cooperative PC/network-processor platform for gigabit traffic generation

Evaluating the performance of high-speed networks is a critical task that requires reliable tools to generate traffic workloads at high rates. The current software tools provide poor performance in terms of packets per second and timing/rate accuracy, because of the intrinsic limitations of the PC architecture. This paper proposes a different approach, based on a cooperative PC/NP architecture: an advanced software tool runs on a host PC and instructs the processing engines of an Intel IXP2400 network processor, which take care of the actual traffic generation. This way we keep the high flexibility of PC tools while achieving the high packet rates of hardware solutions. The system is able to generate several traffic models (to date, constant bit rate, Poisson and Poissonian arrival of burst are implemented); however the tool is easily extensible in that any other traffic models can be added through the available APIs. In order to improve the system precision, a time correction mechanism is also introduced. Finally, the capability of manipulating and reproducing an actual trace is provided.

In-Network Adaptation of Video Streams Using Network Processors

The increasing variety of networks and end systems, especially wireless devices, pose new challenges in communication support for, particularly, multicast-based collaborative applications. In traditional multicasting, the sender transmits video at the same rate and resolution to all receivers independent of their network characteristics, end system equipment, and users' preferences about video quality and significance. Such an approach results in resources being wasted and may also result in some receivers having their quality expectations unsatisfied. This problem can be addressed, near the network edge, by applying dynamic, in-network adaptation (e.g., transcoding) of video streams to meet available connection bandwidth, machine characteristics, and client preferences. In this paper, we extrapolate from earlier work of Shorfuzzaman et al. 2006 in which we implemented and assessed an MPEG-1 transcoding system on the Intel IXP1200 network processor to consider the feasibility of in-network transcoding for other video formats and network processor architectures. The use of “on-the-fly” video adaptation near the edge of the network offers the promise of simpler support for a wide range of end devices with different display, and so forth, characteristics that can be used in different types of environments.

Self-Configurable Environment for the Intel Ixp2400 Network Processor

Network processors (NPs) are programmable multi-processor devices that offer both the flexibility and speed required for the network packet processing applications. Current NP systems do not simultaneously deal well with fluctuating workloads. Because of the traffic fluctuations inherent in packet networks, the workload on each pipeline stage in NP may vary significantly over time, thus affecting performance. One solution would be to change the code running at these stages so as to adapt to the fluctuations. Hence, the allocation of processors to pipeline stages needs to be adapted over time. Run-time adaptation is a potential solution to this problem. With run-time adaptation, the mapping of services to system resources can be dynamically adjusted based on the workload. Dynamically adapting processor allocations reduces the overall resource provisioning requirement for the system. This results in achieving robustness to traffic fluctuations. In this paper, we focus on reconfiguring the system based on the traffic fluctuation. To make decision about the deployment of code, the traffic is monitored and its statistic is maintained. Moreover, active network concept is used for reconfiguring the system, wherein the binary code is transferred to the NP through the SOAP protocol.

A novel resource scheduling algorithm for QoS-aware services on the Internet

The popularity and availability of Internet connection has opened up the opportunity for network-centric collaborative work that was impossible a few years ago. Contending traffic flows in this collaborative scenario share different kinds of resources such as network links, buffers, and router CPU. The goal should hence be overall fairness in the allocation of multiple resources rather than a specific resource. In this paper, firstly, we present a novel QoS-aware resource scheduling algorithm called Weighted Composite Bandwidth and CPU Scheduler (WCBCS), which jointly allocates the fair share of the link bandwidth as well as processing resource to all competing flows. WCBCS also uses a simple and adaptive online prediction scheme for reliably estimating the processing times of the incoming data packets. Secondly, we present some analytical results, extensive NS-2 simulation work, and experimental results from our implementation on Intel IXP2400 network processor. The simulation and implementation results show that our low complexity scheduling algorithm can efficiently maximise the CPU and bandwidth utilisation while maintaining guaranteed Quality of Service (QoS) for each individual flow.

Traffic control based on IXP2400

Network Traffic Control(TC) is to satisfy the needs of Different Services in network.With the premise of providing business reliability,delay,delay jitter,throughput,packet loss rate,it takes full use of scheduling mechanism to control the states of all the business flows.Based on the Intel IXP2400 platform,this paper achieved better network traffic control through changing and judging the Type of Service(ToS) field of IPv4 header.

High-performance packet classification algorithm for multithreaded IXP network processor

Packet classification is crucial for the Internet to provide more value-added services and guaranteed quality of service. Besides hardware-based solutions, many software-based classification algorithms have been proposed. However, classifying at 10 Gbps speed or higher is a challenging problem and it is still one of the performance bottlenecks in core routers. In general, classification algorithms face the same challenge of balancing between high classification speed and low memory requirements. This paper proposes a modified recursive flow classification (RFC) algorithm, Bitmap-RFC, which significantly reduces the memory requirements of RFC by applying a bitmap compression technique. To speed up classifying speed, we exploit the multithreaded architectural features in various algorithm development stages from algorithm design to algorithm implementation. As a result, Bitmap-RFC strikes a good balance between speed and space. It can significantly keep both high classification speed and reduce memory space consumption. This paper investigates the main NPU software design aspects that have dramatic performance impacts on any NPU-based implementations: memory space reduction , instruction selection , data allocation , task partitioning , and latency hiding . We experiment with an architecture-aware design principle to guarantee the high performance of the classification algorithm on an NPU implementation. The experimental results show that the Bitmap-RFC algorithm achieves 10 Gbps speed or higher and has a good scalability on Intel IXP2800 NPU.

ILP and heuristic techniques for system-level design on network processor architectures

Network processors incorporate several architectural features, including symmetric multiprocessing (SMP), block multithreading, and multiple memory elements, to support the high-performance requirements of current day applications. This article presents automated system-level design techniques for application development on such architectures. We propose integer linear programming formulations and heuristic techniques for process allocation and data mapping on SMP and block-multithreading-based network processors. The techniques incorporate process transformations and multithreading-aware data mapping to maximize the throughput of the application. The article presents experimental results that evaluate the techniques by implementing network processing applications on the Intel IXP 2400 architecture.

Reconciling performance and programmability in networking systems

Challenges in addressing the memory bottleneck have made it difficult to design a packet processing platform that simultaneously achieves both ease-of-programming and high performance. Today's commercial processors support two architectural mechanisms - namely, hardware multithreading and caching - to overcome the memory bottleneck. The configurations of these mechanisms (e.g., cache capacity, number of threads per processor core) are fixed at processor-design time. The relative effectiveness of these mechanisms, however, varies significantly with application, traffic, and system characteristics. Thus, programmers often struggle to achieve high performance from a processor that is not well-suited to a particular deployment. To address this challenge, we first make a case for, and then develop a malleable processor architecture that facilitates the dynamic reconfiguration of cache capacity and number of threads to best-suit the needs of each deployment. We then present an algorithm that can determine the optimal thread-cache balance at run-time. The combination of these two allows us to simultaneously achieve the goals of ease-of-programming and high performance. We demonstrate that our processor outperforms a processor similar to Intel's IXP2800 - a state-of-the-art commercial Network Processor - in about 89% of the deployments we consider. Further, in about 30% of the deployments our platform improves the throughput by as much as 300%.

Design, Analysis and Implementation of a Novel Multiple Resource Scheduler

Over the past decade, the problem of achieving fair bandwidth allocation on a link shared by multiple traffic flows has been extensively researched. However, as these flows traverse a computer network, they share many different kinds of resources, such as links, buffers, and router CPU. The ultimate goal should hence be overall fairness in the allocation of multiple resources rather than a single specific resource such as link bandwidth. In this paper, we present a novel scheduler, called prediction-based composite fair queuing (PCFQ), which jointly allocates the fair share of the link bandwidth and processing resources to all competing flows. We derive the worst-case delay bound, the work complexity, and the relative fairness bound for the PCFQ scheduler and show that it outperforms a system consisting of separate bandwidth and CPU schedulers. We further present simulation results which illustrate the improved performance characteristics achieved by PCFQ. We also demonstrate that our composite scheduler can be easily implemented on an off-the-shelf network processor such as the Intel IXP 2400. Experimental results from the IXP 2400 implementation highlight the effectiveness and high performance of this algorithm in a real-world system.

Design, Analysis, and Implementation of a Novel Low Complexity Scheduler for Joint Resource Allocation

Over the past decade, the problem of fair bandwidth allocation among contending traffic flows on a link has been extensively researched. However, as these flows traverse a computer network, they share different kinds of resources (e.g., links, buffers, router CPU). The ultimate goal should hence be overall fairness in the allocation of multiple resources rather than a specific resource. Moreover, conventional resource scheduling algorithms depend strongly upon the assumption of prior knowledge of network parameters and cannot handle variations or lack of information about these parameters. In this paper, we present a novel scheduler called the composite bandwidth and CPU scheduler (CBCS), which jointly allocates the fair share of the link bandwidth as well as processing resource to all competing flows. CBCS also uses a simple and adaptive online prediction scheme for reliably estimating the processing times of the incoming data packets. Analytically, we prove that CBCS is efficient, with a per-packet work complexity of O(1). Finally, we present simulation results and experimental outcomes from a real-world implementation of CBCS on an Intel IXP 2400 network processor. Our results highlight the improved performance achieved by CBCS and demonstrate the ease with which it can be implemented on off-the-shelf hardware

Resource allocation in network processors for network intrusion prevention systems

Networking applications with high memory access overhead gradually exploit network processors that feature multiple hardware multithreaded processor cores along with a versatile memory hierarchy. Given rich hardware resources, however, the performance depends on whether those resources are properly allocated. In this work, we develop an NIPS (Network Intrusion Prevention System) edge gateway over the Intel IXP2400 by characterizing/mapping the processing stages onto hardware components. The impact and strategy of resource allocation are also investigated through internal and external benchmarks. Important conclusions include: (1) the system throughput is influenced mostly by the total number of threads, namely I × J, where I and J represent the numbers of processors and threads per processor, respectively, as long as the processors are not fully utilized, (2) given an application, algorithm and hardware specification, an appropriate ( I, J) for packet inspection can be derived and (3) the effectiveness of multiple memory banks for tackling the SRAM bottleneck is affected considerably by the algorithms adopted.

SUPPORTING RUNTIME RECONFIGURATION ON NETWORK PROCESSORS

Network Processors (NPs) are set to play a key role in the next generation of networking technology. They have the performance of ASIC-based routers whilst offering a high degree of programmability. However, the programmability potential of NPs can only be realised with appropriate software. In this paper we argue that specialised software to support runtime reconfiguration is needed to fully exploit the potential of NPs. We first justify supporting runtime reconfiguration on NPs by offering real-world scenarios and discussing the issues associated with these. We then demonstrate how runtime reconfiguration can be achieved in practice through a case study of our component-based programming approach on the Intel IXP2400 NP.