Intel Integrated Performance Primitives Research Articles

Implementation of radar digital receiver using intel integrated performance primitives

Radar Digital Receiver (RDR) requires to perform many computationally intensive operations in real-time. Therefore, RDRs have been implemented using DSP (Digital Signal Processor) or high performance FPGA (Field Programmable Gate Array) based customized hardware and software, and optimized for heavy math computation. These designs have a few limitations like long development cycle and high implementation cost due to customized hardware and proprietary software including development tools, Board Support Package and Operating System (OS). A new design is proposed to overcome these limitations by making use of low-cost COTS (Commercially Off The Shelf) hardware containing multi-core processors that are enabled to perform complex math efficiently, open source software and ready to use Intel’s IPP (Integrated Performance Primitives) library of functions. A prototype RDR for tracking application is developed and evaluated by integrating with an S-Band Radar and tracking various targets. The details of design, implementation and performance evaluation of the prototype RDR are presented in this paper.

MemJam: A False Dependency Attack Against Constant-Time Crypto Implementations

Cache attacks exploit memory access patterns of cryptographic implementations. Constant-Time implementation techniques have become an indispensable tool in fighting cache timing attacks. These techniques engineer the memory accesses of cryptographic operations to follow a uniform key independent pattern. However, the constant-time behavior is dependent on the underlying architecture, which can be highly complex and often incorporates unpublished features. CacheBleed attack targets cache bank conflicts and thereby invalidates the assumption that microarchitectural side-channel adversaries can only observe memory with cache line granularity. In this work, we propose MemJam, a side-channel attack that exploits false dependency of memory read-after-write and provides a high quality intra cache level timing channel. As a proof of concept, we demonstrate the first key recovery attacks on a constant-time implementation of AES, and a SM4 implementation with cache protection in the current Intel Integrated Performance Primitives (Intel IPP) cryptographic library. Further, we demonstrate the first intra cache level timing attack on SGX by reproducing the AES key recovery results on an enclave that performs encryption using the aforementioned constant-time implementation of AES. Our results show that we can not only use this side channel to efficiently attack memory dependent cryptographic operations but also to bypass proposed protections. Compared to CacheBleed, which is limited to older processor generations, MemJam is the first intra cache level attack applicable to all major Intel processors including the latest generations that support the SGX extension.

AOI Multi-Core Parallel System for TFT-LCD Defect Detection

The present Automatic Optical Inspection (AOI) technology can hardly satisfy online inspection requirements for large-scale high-speed, high-precision and high-sensitivity TFT-LCD. First, through studying the working principle of TFT-LCD Defect AOI System, the system architecture for mixed-parallel multi-core computer cluster is proposed to satisfy design requirements. Second, the study focuses on the software framework of AOI system and related key software technology. Finally, the fusion programming model for parallel image processing and its implementation strategy is proposed based on OpenMP, MPI, OpenCV, and Intel Integrated Performance Primitives (IPP).