Intel Advanced Vector Extensions Research Articles

Real-time processing approaches for interactive room acoustic auralization in the rtSOFE

Room acoustic simulation of early reflections with the mirror-image method for arbitrary room geometries is an exponential problem, which, if computed to a high reflection order, will quickly exceed available computational and memory resources. The real-time Simulated Open Field Environment (rtSOFE) is freely available room-acoustic simulation and auralization software based on the mirror-image method. For auralization, rtSOFE synthesizes room impulse responses for each playback channel from the list of mirror images. A convolver program receives these seconds-long room impulse responses and convolves them for each sound source, sums across sources, and performs the playback equalization. Both programs perform computations in multiple threads in parallel using the OpenMP library. Many operations are implemented with Intel Advanced Vector Extensions (AVX) to increase processing speed. Image source trees are terminated after a definable number of invisible parent sources, keeping the number of computed mirrors manageable. With this, rtSOFE is capable of computing room impulse responses to high reflection orders in interactive real-time settings. I will present the software concept and discuss the approaches that speed up the computation.

Fast Multiple-Precision Integer Division Using Intel AVX-512

This paper reports on the implementation of a large integer division method that uses Intel Advanced Vector Extensions 512 (AVX-512), which is a 512-bit Single Instruction Multiple Data (SIMD) instruction set, and proposes a modification to a conventional division algorithm that makes it more SIMD instruction-friendly. More specifically, we use the Integer Fused Multiply-Add AVX-512 (AVX-512IFMA) subset, which is an instruction set that works well with large integer multiplication, to compute large integer divisions via a multiplication-based approach with a reciprocal. For the division process, we apply the most basic algorithm and divide-and-conquer methods and then use several techniques to compute efficiently with SIMD instructions in our implementation. We then combine these techniques and methods to implement our division function so that it can flexibly handle various sizes. To evaluate the performance of our proposed implementation, we executed our division program and the GNU Multiple Precision Arithmetic Library (GMP) on a Cannon Lake microarchitecture processor. A comparison of the execution times for our division program and GMP with various sizes showed that our method resulted in performance improvements of 25% to 35% on average, thus indicating that SIMD instructions are effective for fast arbitrary precision integer divisions.

Raising the Performance of the Tinker-HP Molecular Modeling Package [Article v1.0

This living paper reviews the present High Performance Computing (HPC) capabilities of the Tinker-HP molecular modeling package. We focus here on the reference, double precision, massively parallel molecular dynamics engine present in Tinker-HP and dedicated to perform large scale simulations. We show how it can be adapted to recent Intel Central Processing Unit (CPU) petascale architectures. First, we discuss the new set of Intel Advanced Vector Extensions 512 (Intel AVX-512) instructions present in recent Intel processors (e.g., the Intel Xeon Scalable and Intel Xeon Phi 2nd generation processors) allowing for larger vectorization enhancements. These instructions constitute the central source of potential computational gains when using the latest processors, justifying important vectorization efforts for developers. We then briefly review the organization of the Tinker-HP code and identify the computational hotspots which require Intel AVX-512 optimization and we propose a general and optimal strategy to vectorize those particular parts of the code. We intended to present our optimization strategy in a pedagogical way so it could benefit to other researchers and students interested in gaining performances in their own software. Finally we present the performance enhancements obtained compared to the unoptimized code both sequentially and at the scaling limit in parallel for classical non-polarizable (CHARMM) and polarizable force fields (AMOEBA). This paper never ceases to be updated as we accumulate new data on the associated Github repository between new versions of this living paper.

Computation of the 100 quadrillionth hexadecimal digit of π on a cluster of Intel Xeon Phi processors

Abstract This paper presents the computation of a specific hexadecimal digit of π by using a Bailey–Borwein–Plouffe (BBP)-type formula on a cluster of Intel Xeon Phi processors. The BBP-type formula can be computed using modular exponentiation. We use Montgomery multiplication for the modular multiplication, which is the most time-consuming part of the modular exponentiation. We vectorize multiple modular exponentiations and multiple integer divisions by using Intel Advanced Vector Extensions 512 (Intel AVX-512) instructions. A parallel implementation of the BBP-type formula is presented. The 100 quadrillionth hexadecimal digit of π was computed on a 512-node cluster of Intel Xeon Phi processors with an elapsed time of 641 h 29 min that includes the time required for verification.

Utilizing Intel Advanced Vector Extensions for Monte Carlo Simulation based Value at Risk Computation

Value at Risk (VaR) is a statistical method of predicting market risk associated with financial portfolios. There are numerous statistical models which forecast VaR and out of those, Monte Carlo Simulation is a commonly used technique with a high accuracy though it is computationally intensive. Calculating VaR in real time is becoming a need of short term traders in current day markets and adapting Monte Carlo method of VaR computation for real time calculation poses a challenge due to the computational complexity involved with the simulation step of the Monte Carlo Simulation. The simulation process has an independent set of tasks. Hence a performance bottleneck occurs during the sequential execution of these independent tasks. By parallelizing these tasks, the time taken to calculate the VaR for a portfolio can be reduced significantly. In order to address this issue, we looked at utilizing the Advanced Vector Extensions (AVX) technology to parallelize the simulation process. We compared the performance of the AVX based solution against the sequential approach as well as against a multithreaded solution and a GPU based solution. The results showed that the AVX approach outperformed the GPU approach for up to an iteration count of 200000. Since such a number of iterations is generally not required to gain a sufficiently accurate VaR measure, it makes sense both computationally and economically to utilize AVX for Monte Carlo method of VaR computation.

Performance Evaluation of Matrix-Matrix Multiplications Using Intel's Advanced Vector Extensions (AVX)

Intel's Advanced Vector Extensions is known as single instruction multiple data streams (SIMD), and the instruction sets is introduced in the second-generation Intel Core processor family. This new technology is supported by new generations of Intel and AMD processors. The advanced vector extensions (AVX) exploits single instruction multiple data (SIMD) computing units for fine grained-parallelism. These instructions process multiple data elements simultaneously and independently. Many applications such as signal processing, recognition, visual processing, scientific and engineering numerical, physics and other areas of applications need for vector floating point performance supported by AVX. Matrix-Matrix multiplications is the core of many important algorithms such as signal processing, scientific and engineering numerical, so it is substantial to accelerate implementation of matrix-matrix multiplications. It is very important to use appropriate compilers that can optimally utilize the new features of the evolving processors. For this purpose, a clear vision on the performance of the compilers on performance characteristics of AVX is needed. In addition choosing the appropriate programming method is substantial to gain the best performance. In this paper, the performance evaluation of matrix-matrix multiplications in three forms (C=A. B, C=A. BT, and C=AT. B), using Intel's advanced vector extension (AVX) instruction sets has been reported. The obtained results are compared using inline assembly versus intrinsic functions for programming. A comparative study to indicate the effects of two widely used C++ compilers: Intel C++ compiler (ICC) in Intel Parallel Studio XE 2016 against Microsoft Visual Studio C++ compiler 2015 (MSVC++) has been investigated. The results are evaluated on Intel Core i7 processor on a Broadwell system for square matrices of different large sizes. The results demonstrate that the Intel compiler has better performance than MSVC++ compiler by 1.34, 1.32, and 1.22 using inline assembly language and by 1.36, 1.19, and 1.25 using intrinsic functions for C=A. B, C=A. BT, and C=AT. B, respectively. The performance of using intrinsic functions compared to the inline assembly demonstrates that the intrinsic functions has better performance than inline assembly by 2.1, 2.13, and 2.18 using Intel compiler and by 2.08, 2.49, and 2.11 using MSVC++ compiler for C=A. B, C=A. BT, and C=AT. B, respectively.