Integrated Schottky Barrier Diode Research Articles

A Novel 4H-SiC SGT MOSFET with Improved P+ Shielding Region and Integrated Schottky Barrier Diode.

A silicon carbide (SiC) SGT MOSFET featuring a ""-shaped P+ shielding region (PSR), named SPDT-MOS, is proposed in this article. The improved PSR is introduced as a replacement for the source trench to enhance the forward performance of the device. Its improvement consists of two parts. One is to optimize the electric field distribution of the device, and the other is to expand the current conduction path. Based on the improved PSR and grounded split gate (SG), the device remarkably improves the conduction characteristics, gate oxide reliability, and frequency response. Moreover, the integrated sidewall Schottky barrier diode (SBD) prevents the inherent body diode from being activated and improves the reverse recovery characteristics. As a result, the gate-drain capacitance, gate charge, and reverse recovery charge (Qrr) of the SPDT-MOS are 81.2%, 41.2%, and 90.71% lower than those of the DTMOS, respectively. Compared to the double shielding (DS-MOS), the SPDT-MOS exhibits a 20% reduction in on-resistance and an 8.1% increase in breakdown voltage.

Novel high-voltage GaN CAVET with high threshold voltage and low reverse conduction loss

A novel GaN current-aperture vertical electron transistor (CAVET) with an energy band pinning (EBP) structure (EBP-CAVET) is proposed and investigated by simulations. The EBP-CAVET is featured with hybrid contacts on the p-GaN layer, locally having Ohmic contact combined with Schottky gate metals in the longitudinal direction. The Ohmic contact is shorted to the source electrode and the Schottky gate metals are shorted to the gate electrode. The conduction band (Ec) in the gate region is modulated by the alternately arranged contacts. In the Ohmic contact region, Ec remains a fixed value, which acts as an energy band pinning and suppresses the variation of the Ec in the gate region. In the on-state (VGS > 0 V) and blocking-state with high VDS, the EBP structure inhibits the Ec shifting downwards in the gate region to achieve a high threshold voltage (Vth), a low leakage current density (Jdss), and a high breakdown voltage (BV). In the reverse conduction state (VDS < 0 V &VGS ≤ 0 V), the EBP structure suppresses the Ec shifting upwards to achieve a low and independent of gate bias reverse turn-on voltage (VRT). The proposed EBP-CAVET achieves a high Vth of 2.10 V, a VRT of 0.69 V, a low Jdss of 3.1 × 10−11 A/cm2 at VDS = 1000 V, a high BV of 1660 V. Compared with an integrated Schottky barrier diode or fin diode in a field effect transistor (FET), the EBP structure occupies a much smaller chip area. Thus, the EBP-CAVET achieves a low specific ON-resistance (Ron,sp) of 1.19 mΩ cm2 and an extremely high power-figure-of-merit (PFOM) up to 2.32 GW/cm2. Consequently, the proposed structure presents a new design concept and enhances the application potential for GaN CAVET with high Vth and low reverse conduction loss.

Ga₂O₃ Vertical FinFET With Integrated Schottky Barrier Diode for Low-Loss Conduction

Ga₂O₃ Vertical FinFET With Integrated Schottky Barrier Diode for Low-Loss Conduction

A novel SiC high-k superjunction power MOSFET integrated Schottky barrier diode with improved forward and reverse performance

A new SiC superjunction power MOSFET device using high-k insulator and p-type pillar with an integrated Schottky barrier diode (Hk-SJ-SBD MOSFET) is proposed, and has been compared with the SiC high-k MOSFET (Hk MOSFET), SiC superjuction MOSFET (SJ MOSFET) and the conventional SiC MOSFET in this article. In the proposed SiC Hk-SJ-SBD MOSFET, under the combined action of the p-type region and the Hk dielectric layer in the drift region, the concentration of the N-drift region and the current spreading layer can be increased to achieve an ultra-low specific on-resistance (R on,sp). The integrated Schottky barrier diode (SBD) also greatly improves the reverse recovery performance of the device. TCAD simulation results indicate that the R on,sp of the proposed SiC Hk-SJ-SBD MOSFET is 0.67 mΩ·cm2 with a 2240 V breakdown voltage (BV), which is more than 72.4%, 23%, 5.6% lower than that of the conventional SiC MOSFET, Hk SiC MOSFET and SJ SiC MOSFET with the 1950, 2220, and 2220 V BV, respectively. The reverse recovery time and reverse recovery charge of the proposed MOSFET is 16 ns and18 nC, which are greatly reduced by more than 74% and 94% in comparison with those of all the conventional SiC MOSFET, Hk SiC MOSFET and SJ SiC MOSFET, due to the integrated SBD in the proposed MOSFET. And the trade-off relationship between the R on,sp and the BV is also significantly improved compared with that of the conventional MOSFET, Hk MOSFET and SJ MOSFET as well as the MOSFETs in other previous literature, respectively. In addition, compared with conventional SJ SiC MOSFET, the proposed SiC MOSFET has better immunity to charge imbalance, which may bring great application prospects.

A comparative study of SiC MOSFETs with and without integrated SBD

A comparative study on SiC MOSFETs is carried out with an emphasis on the design of integrated Schottky barrier diode (SBD) with numerical simulations by Sentaurus TCAD. Compared with the conventional SiC MOSFET (C-MOS) and the conventional SBD-embedded SiC MOSFET (C-MOSBD), the MOSFET (M-MOSBD) features a hybrid doping mesa above the JFET region where a Schottky contact is formed, which exhibits a superior trade-off between the on-state resistance (Rdson) and the reverse transfer capacitance (Crss). Besides, the integrated diode in M-MOSBD renders a better trade-off between OFF-state junction field (ESmax) and forward voltage (VF) when compared to C-MOSBD and the conventional junction barrier Schottky diode (JBS), i.e., the external SBD of C-MOS. In the double pulse test simulation, C-MOS exhibited the largest switch loss followed by C-MOSBD, and M-MOSBD is the smallest. Therefore, in power switching applications where reverse conduction is required, M-MOSBD greatly reduces the chip area while presenting better characteristics.

High-Voltage Polarization-Superjunction GaN HEMT With Built-In SBD for Low Reverse Conduction Loss

A GaN Reverse-Conducting HEMT (RC-HEMT) is proposed and fabricated on the GaN/AlGaN/GaN platform. It features an integrated Schottky barrier diode (SBD) to realize reverse conduction and the double-heterojunction to enhance breakdown voltage (BV). Compared with the inherent reverse conduction capability of the conventional HEMT (Con. HEMT), the built-in SBD exhibits a low reverse turn-on voltage (VRT) and its VRT is independent of the threshold voltage and gate bias. At the off-state, the fixed positive and negative polarization charges form the polarization superjunction (PSJ). Therefore, the depletion region is extended and more uniform E-field distribution is obtained. Experimental results show that the RC-PSJ-HEMT achieves a low VRT of 0.68 V, which decreases 69.1% compared with that of the Con. HEMT. The BV of the RC-PSJ-HEMT (with 7.5 μm LGD) is increased to 723 V from 202 V of the Con. HEMT.

SiC Fin-Shaped Gate Trench MOSFET with Integrated Schottky Diode.

A silicon carbide (SiC) trench MOSFET featuring fin-shaped gate and integrated Schottky barrier diode under split P type shield (SPS) protection (FS-TMOS) is proposed by finite element modeling. The physical mechanism of FS-TMOS is studied comprehensively in terms of fundamental (blocking, conduction, and dynamic) performance and transient extreme stress reliability. The fin-shaped gate on the sidewall of the trench and integrated Schottky diode at the bottom of trench aim to the reduction of gate charge and improvement on the third quadrant performance, respectively. The SPS region is fully utilized to suppress excessive electric field both at trench oxide and Schottky contact when OFF-state. Compared with conventional trench MOSFET (C-TMOS), the gate charge, Miller charge, Von at third quadrant, Ron,sp·Qgd, and Ron,sp·Qg of FS-TMOS are significantly reduced by 34%, 20%, 65%, 0.1%, and 14%, respectively. Furthermore, short-circuit and avalanche capabilities are discussed, verifying the FS-TMOS is more robust than C-TMOS. It suggests that the proposed FS-TMOS is a promising candidate for next-generation high efficiency and high-power density applications.

A novel SiC trench MOSFET with integrated Schottky barrier diode for improved reverse recovery charge and switching loss

AbstractIn this paper, a novel silicon carbide (SiC) trench metal oxide semiconductor field effect transistor (MOSFET) with improved reverse recovery charge and switching energy loss is proposed and investigated utilising ISE‐TCAD simulations. The proposed structure features an integrated Schottky barrier diode on one side‐wall of the trench below the P‐base region, and an inserted thicker oxide layer between the polysilicon gate and source metal on one side‐wall of the trench. The simulation results show that compared with Infineon's CoolSiC™ Trench MOSFET, the proposed device decreases the gate charge Qg by 29.2%, leading to significantly improved figures of merit (Ron,sp × Qg). The reverse recovery charge Qrr and peak reverse recovery current (IRRM) are reduced by 64.1% and 66.0%, respectively. Meanwhile, the total switching energy loss decreases 36.7% for the dynamic performance.

Simulation Study of 4H-SiC High-k Pillar MOSFET With Integrated Schottky Barrier Diode

A SiC high-k (HK) split-gate (SG) MOSFET is proposed with a Schottky barrier diode (SBD) integrated between the split gates, and is investigated by numerical TCAD simulation. Results show that it has the same breakdown voltage as the SiC high-k (HK) MOSFET with an optimized and practical k value of 30 for its insulation pillar, which results in the highest breakdown voltage (1857 V). The forward voltage (VF) and reverse recovery charge (QRR) of the device are 0.9 V and 3.49 μC/cm2 respectively, much lower than those of the SiC HK MOSFET due to the SBD. Moreover, lower reverse transfer capacitance (CRSS), smaller gate charge (QG), and smaller gate-to-drain charge (QGD) are achieved for the proposed device because of the split-gates, leading to much lower switching power loss when compared with the SiC HK MOSFET. All these results indicate that the SiC HK SG-MOSFET has promising potential in future power electronics applications.

Demonstration of Superior Electrical Characteristics for 1.2 kV SiC Schottky Barrier Diode-Wall Integrated Trench MOSFET With Higher Schottky Barrier Height Metal

In this letter, the authors demonstrated superior electrical characteristics of a 1.2 kV SiC Schottky barrier diode-wall integrated trench MOSFET (SWITCH-MOS) with the higher Schottky barrier height of nickel. It was confirmed that a significant improvement in short-circuit capability was achieved with no sacrifice of on resistance, because the electron leakage current through the integrated Schottky barrier diode (SBD), caused by thermionic-field emission, could be successfully suppressed. Further, although the integrated SBD with nickel showed 0.25 V greater forward voltage drop than that with titanium, the on resistance and switching characteristics were similar in the two devices. The results of the study showed that the SWITCH-MOS with nickel can achieve 21.0% less power dissipation in high frequency pulse width modulation inverters, compared to standard SiC trench MOSFETs.

4H-SiC trench MOSFET with an integrated Schottky barrier diode and L-shaped P+ shielding region

A novel 4H-SiC trench MOSFET is presented and investigated by simulation in this paper. The device features an integrated Schottky barrier diode and an L-shaped P+ shielding region beneath the gate trench and aside one wall of the gate trench (S-TMOS). The integrated Schottky barrier diode works as a free-wheeling diode in reverse recovery and reverse conduction, which significantly reduces reverse recovery charge (Qrr) and reverse turn-on voltage (VF). The L-shaped P+ region effectively shields the coupling of gate and drain, resulting in a lower gate–drain capacitance (Cgd) and date–drain charge (Qgd). Compared with that of conventional SiC trench MOSFET (C-TMOS), the VF and Qrr of S-TMOS has reduced by 44% and 75%, respectively, with almost the same forward output current and reverse breakdown voltage. Moreover, the S-TMOS reduces Qgd and Cgd by 32% and 22%, respectively, in comparison with C-TMOS.

Silicon carbide split-trench-source VDMOSFET with integrated Schottky barrier diode and reduced cell pitch

A new silicon carbide (SiC) VDMOSFET with an integrated split trench Schottky barrier diode (SBD) between split sources is proposed, namely STS-VDMOSFET, and investigated by 2D simulation. Compared with the SiC VDMOSFET integrated with SBD between split sources (SS-VDMOSFET), the cell pitch of the proposed structure can be greatly reduced apart from suppressing the conduction of the intrinsic body diode. Consequently, the active area of the proposed structure is 23% lower than that of the SS-VDMOSFET with the same on-state resistance, leading to reducing the cost effectively and the switching loss lightly. In addition, the trench-source can be etched during alignment mask without lithographic process of P+ implantation. In a word, the proposed structure is a superior choice for the SBD integration scheme solution because of the simplified process, excellent performance of device and the reduced cost.

Analysis of the Fast-Switching LIGBT With Double Gates and Integrated Schottky Barrier Diode

A novel fast-switching lateral-insulated gate bipolar transistor (LIGBT) with double gates and integrated Schottky barrier diode (SBD) is proposed and studied in this paper by TCAD simulation. In order to reduce the turn-off time and maintain a low forward voltage drop, the proposed structure introduces an integrated SBD structure at the anode and an additional trench gate at the cathode. First, the integrated SBD provides an extra electron extraction path and the additional trench gate enhances the injection of the N+-cathode. Furthermore, the insulated oxide pillar between the N-buffer and integrated SBD further reduces the snapback voltage. Finally, the simulation results show that the turn-off time of the conventional LIGBT is 52.4% larger than that of trench/planar gate SBD (TP-SBD) LIGBT under the same forward voltage of 1.49 V. Moreover, the latch current density of TP-SBD LIGBT is increased by nearly 200% compared to that of the conventional LIGBT, while almost the same latch voltage is obtained, so the proposed TP-SBD LIGBT can improve the latch immunity.

High-Voltage Tolerant Digitally Aided DCM/PWM Multiphase DC-DC Boost Converter With Integrated Schottky Diodes in 0.13 µm 1.2 V Digital CMOS Process

This paper reports a high-frequency DC-DC boost converter capable of sustaining up to 4× the rated process voltage using high-voltage devices fabricated in standard 0.13 μm 1.2 V CMOS without additional masking steps. Integrated Schottky Barrier Diodes (SBD) and high-voltage stacked composite NMOS switches enable processing of large voltages in a 100 MHz digitally assisted four-phase switched inductor (SI) boost converter architecture. A high-frequency digital delay-locked loop (DDLL) is employed to automatically stagger and synchronize each phase to a primary current-mode pulsed-width modulator (PWM) controller, thus eliminating the need for multiple current sensing circuits. The converter operates in discontinuous conduction mode (DCM) and utilizes integrated Schottky diode output rectifier stages to eliminate dead-time controllers and power hungry high side drivers. The converter operates at 100 MHz with four external 22 nH inductors and achieves an output conversion range of 3 V to 5 V from a 1.2 V input supply. It can deliver 240 mW at 3 V and 200 mW at 5 V with an efficiency of 60%, and ~ 180 mW at 3 V with peak efficiency of 64%.