Integrated RMS Phase Error Research Articles

A ΔΣ fractional-N frequency synthesizer for FM tuner using low noise filter and quantization noise suppression technique

A ΔΣ fractional-N frequency synthesizer fabricated in a 130 nm CMOS technology is presented for the application of an FM tuner. A low noise filter, occupying a small die area and decreasing the output noise, is integrated on a chip. A quantization noise suppression technique, using a reduced step size of the frequency divider, is also adopted. The proposed synthesizer needs no off-chip components and occupies an area of 0.7 mm2. The in-band phase noise (from 10 to 100 kHz) below −108 dBc/Hz and out-of-band phase noise of −122.9 dBc/Hz (at 1 MHz offset) are measured with a loop bandwidth of 200 kHz. The quantization noise suppression technique reduces the in-band and out-of band phase noise by 15 dB and 7 dB respectively. The integrated RMS phase error is no more than 0.48°. The proposed synthesizer consumes a total power of 7.4 mW and the frequency resolution is less than 1 Hz.

Uncorrelated Phase Noise Analysis for Millimeter-Wave Radiometer Imager Frequency Synthesizer

In this paper, a nontrivial uncorrelated phase noise analysis is proposed for frequency synthesizer of a passive millimeter-wave Synthetic Aperture Interferometric Radiometer (SAIR) imager named BHU-2D-U designed for concealed weapon detections on human bodies with high imaging rates. This synthesizer provides local oscillators both for millimeter-wave front-ends and intermediate frequency IQ demodulators for the receivers. The influence of synthesizer uncorrelated phase noise in different offset frequency ranges on the visibility phase errors have been systematically investigated with phase noise mismatch requirements drawn. Integrated RMS phase error has been applied to establish uncorrelated phase noise requirements for visibility error control. Measurement results have proved that uncorrelated phase noise does exist among synthesizer output pairs, and the previously defined requirements are achieved with imaging results proposed. In conclusion, the uncorrelated phase noise effects on SAIR visibility errors have been concretized to phase noise design requirements, which have been realized by synthesizer design. DOI : http://dx.doi.org/10.11591/telkomnika.v12i2.3844

A 55 nm CMOS ΔΣ fractional-N frequency synthesizer for WLAN transceivers with low noise filters

A fully integrated ΔΣ fractional-N frequency synthesizer fabricated in a 55 nm CMOS technology is presented for the application of IEEE 802.11b/g wireless local area network (WLAN) transceivers. A low noise filter, occupying a small die area, whose power supply is given by a high PSRR and low noise LDO regulator, is integrated on chip. The proposed synthesizer needs no off-chip components and occupies an area of 0.72 mm2 excluding PAD. Measurement results show that in all channels, the phase noise of the synthesizer achieves −99 dBc/Hz and −119 dBc/Hz in band and out of band respectively with a reference frequency of 40 MHz and a loop bandwidth of 200 kHz. The integrated RMS phase error is no more than 0.6°. The proposed synthesizer consumes a total power of 15.6 mW.

A Phase Noise Analysis Method for Millimeter-Wave Passive Imager BHU-2D-U Frequency Synthesizer

A nontrivial phase noise analysis method is proposed for frequency synthesizer of a passive millimeter-wave synthetic aperture interferometric radiometer (SAIR) imager for concealed weapon detections on human bodies with high imaging rates. The frequency synthesizer provides local oscillator signals for both millimeter-wave front ends and intermediate frequency IQ demodulators for the SAIR system. The influence of synthesizer phase noise in different offset frequency ranges on the visibility phase errors has been systematically investigated with noise requirements drawn, and the integrated RMS phase error could represent uncorrelated phase noise effects in the most critical offset frequency range for visibility error control. An analytical phase noise simulation method is proposed to guide synthesizer design. To conclude, the phase noise effects on SAIR visibility errors have been concretized to noise design requirements, and good agreements have been observed between simulation and measurement results. The frequency synthesizer designed has been successfully in operation in BHU-2D-U system.

LOCAL OSCILLATOR UNCORRELATED PHASE NOISE ANALYSIS FOR MILLIMETER-WAVE PASSIVE IMAGER BHU-2D FREQUENCY SYNTHESIZER

In this paper, a nontrivial local oscillator uncorrelated phase noise analysis is proposed for frequency synthesizer of a pas- sive millimeter-wave Synthetic Aperture Interferometric Radiometer (SAIR) imager BHU-2D designed for concealed weapon detections on human bodies with high imaging rates. The frequency synthesizer pro- vides local oscillator signals for both millimeter-wave front-ends and intermediate frequency I/Q demodulators for the receivers. The in- ∞uence of local oscillator uncorrelated phase noise in difierent ofiset frequency ranges on the visibility phase errors have been systemati- cally investigated, and the corresponding system-level visibility speci- flcations are drawn. The integrated RMS phase error has been applied to set uncorrelated phase noise requirements in the most critical ofiset frequency range for visibility error control. The synthesizer design is given, and measurement results have proved that the visibility phase error requirement is achieved by the PN analysis method proposed with system-level visibility error tests performed. To conclude, the phase noise efiects on SAIR visibility phase errors are investigated by the- ory, and are properly limited by the PN requirement analysis method to ensure that the system-level visibility phase error speciflcation is satisfled.

A 0.13 μm CMOS ΔΣ fractional-N frequency synthesizer for WLAN transceivers

A fractional-N frequency synthesizer fabricated in a 0.13 μm CMOS technology is presented for the application of IEEE 802.11 b/g wireless local area network (WLAN) transceivers. A monolithic LC voltage controlled oscillator (VCO) is implemented with an on-chip symmetric inductor. The fractional-N frequency divider consists of a pulse swallow frequency divider and a 3rd-order multistage noise shaping (MASH) ΔΣ modulator with noise-shaped dithering techniques. Measurement results show that in all channels, phase noise of the synthesizer achieves −93 dBc/Hz and −118 dBc/Hz in band and out of band respectively with a phase-frequency detector (PFD) frequency of 20 MHz and a loop bandwidth of 100 kHz. The integrated RMS phase error is no more than 0.8°. The proposed synthesizer consumes 8.4 mW from a 1.2 V supply and occupies an area of 0.86 mm2.

A CMOS 1.6 GHz Dual-Loop PLL With Fourth-Harmonic Mixing

A 1.5-1.6 GHz dual-loop phase-locked loop in 0.18-μm CMOS locks in 40 μs and draws only 26 mA from 1.8 V. The proposed techniques include a fourth-harmonic mixer that relaxes the secondary PLL requirements, and an auxiliary charge pump that speeds acquisition without affecting steady-state operation. The integrated RMS phase error is 1.1° and the phase noise spectral density is -116.8 dBc/Hz at an offset frequency of 600 kHz. The largest in-band and reference spurs are -83 dBc and -105 dBc at frequency offsets of 500.5 kHz and 37.9 MHz, respectively.

A 1 mhz bandwidth, 6 ghz 0.18 μm cmos type-i Δ Σ fractional-n synthesizer for wimax applications

A 6 GHz Type-I fractional- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N</i> PLL with noise-cancelling DAC and discrete-time sample and hold loop-filter is presented. The 1 MHz bandwidth PLL utilizes an inherently linear PFD and noise-cancelling charge-pump DAC circuit to reduce quantization noise by more than 25 dB. The worst case near-integer in-band spur is measured at -61 dBc and the integrated RMS phase error is - 42 dBc. The measured in-band phase noise at 300 kHz offset from the 6.12 GHz carrier is -102 dBc/Hz and out-of-band phase noise at 3 MHz offset is -130 dBc/Hz. The PLL loop settling time for an accuracy of 0.01 ppm and a frequency step of 60 MHz is less than 11 ¿ s. The synthesizer is fabricated in a 0.18 ¿m CMOS technology with 6 metal layers and consumes 26 mA from a 1.8 V power supply.