Integrated Circuit Emphasis Model Research Articles

SPICE‐based modeling of a polarization‐independent active frequency selective surface based tunable absorber with high angular stability

AbstractNowadays, demand for active frequency‐selective surfaces (FSSs) is increasing due to their reconfigurable characteristics. Numerical simulations of reactive elements require a model that can replicate their physical realization. Traditionally, reactive elements are modeled as approximated lumped circuits during electromagnetic simulations. However, such lumped circuits might fail to replicate device characteristics at high frequencies, leading to approximate results. This paper presents an alternative method to model reactive elements using their simulation program with integrated circuit emphasis models (SPICE) in circuit co‐simulations. The proposed modeling method is investigated by realizing a varactor‐loaded active FSS‐based tunable absorber. Simulated results indicate that the proposed absorber provides tunability in a wide frequency range from 0.54 to 2.09 GHz under normal incidence when electrostatic bias varies from 0 to 28 V. Moreover, polarization‐independent and exhibits stable frequency response for oblique incidences up to 80° for dual‐polarizations. These characteristics make it a potential candidate for stealth applications.

Technology Computer-Aided Design-Based Simulation Program with Integrated Circuit Emphasis Model for Back-Channel-Etched Thin-Film Transistors with Floating Metal Components.

We report thin-film transistors (TFTs) with floating metal using a back-channel-etched (BCE) process. Since the BCE process reduces the active mask step compared to other processes, it has attracted attention as a back-plane process that could be used for mass production. To realize the long channel in the BCE process, a floating metal is required; this acts as a bridge in the middle of the channel. We used TCAD (Technology computer-aided design) simulations (Atlas 3D) to predict the characteristics of a-Si TFTs with various active layer thicknesses and numbers of floating metal components; simulation results were compared with real measurements. We explain why TFTs do not scale ideally when floating metals are used; this is related to the resistance and thickness of the active channel. If a thick and highly resistive active channel is used, a larger number of floating metals will require greater correction for ideal scaling. Additionally, considering the capacitance between the source metal and channel, the channel influence under the floating metal should be about 89%. We also suggest a new SPICE (Simulation Program with Integrated Circuit Emphasis) model for TFTs with floating metal based on TCAD simulations.

An Alternative Simulation Program with Integrated Circuit Emphasis Model of Tunneling Field Effect Transistor Considering Ambipolar Characteristics

An Alternative Simulation Program with Integrated Circuit Emphasis Model of Tunneling Field Effect Transistor Considering Ambipolar Characteristics

Parameter extraction method for universal amorphous silicon thin-film transistors simulation program with integrated circuit emphasis model

The universal simulation program with integrated circuit emphasis (SPICE) model for hydrogenated amorphous silicon thin-film transistor is largely used in circuit simulation. This model has more than 10 parameters to be extracted through experimental data, and the optimal method to determine them is still open to discussion. In this study, the authors propose a new method for the extraction of the main above-threshold regime parameters. This method can be used regardless of the resistance value between the channel and the source-drain. The parameters extracted with this method are less sensitive on experimental data selection than the ones obtained through conventional methods. In addition, these parameters successfully describe the experimental data.

Comparative Study on Energy-Efficiencies of Single-Electron Transistor-Based Binary Full Adders Including Nonideal Effects

Performances and energy efficiencies of various single-electron transistor-based (SET-based) binary full adders (FAs) are comparatively investigated with optimization of device parameters by means of simulation program with integrated circuit emphasis models including nonideal effects commonly observed in really implemented SETs. The proposed binary decision diagram (BDD) cell-based 1-bit FA is the most promising in terms of energy efficiency (τ=0.3 aJ/state), power dissipation (P = 1.2 nW), delay (τ=20 ps), and immunity to process variations (background charge noise ΔQ0 <; ±0.112q and control gate capacitance mismatch ΔCcg <; 0.5 × Ccg) at the expense of hardware burden, compared with majority gate-based SET FAs (3.988 aJ/state, P = 15.95nW, τ=52 ps, ΔQ0 <; ±0.0392q, ΔCcg <; 0.35 × Ccg) and SET threshold logic gate-based FAs (3.845 aJ/state, P=15.38nW, τ=107 ps, ΔQ0 <; ±0.028q, ΔCcg <; 0.2 × Ccg). It is also found that the SET itself dominates the power dissipation in SET-based FAs and the static dc power plays a significant role in power consumption in SET-based FAs, compared with the dynamic power, regardless of the FA type. In addition, SET-based BDD FAs are compared with their CMOS counterparts.

A NOVEL DESIGN METHODOLOGY FOR REDUCING SIMULTANEOUS SWITCHING NOISE EVALUATED BY A DIFFERENTIAL-IBIS STRUCTURE

Modern electronic products increasingly require high speed, high density, and low-voltage operation. In such designs, the power-delivery system could be affected by input noise to the point that it becomes unstable. Simultaneous switching noise (SSN) is a major factor that interferes with power integrity. Although decoupling capacitors cannot effectively alleviate the problem of SSN, they have been generally used in the HP Simulation Program with Integrated Circuit Emphasis model for reducing SSN. The differential I/O buffer information specification (D-IBIS) model uses equivalent circuits to describe the behavior of an integrated circuit. In this study, we propose a novel method for effectively reducing SSN evaluated by an enhanced D-IBIS model with decoupling capacitors and a high-frequency low-impendence circuit. We show that this new method reduces noise by about 40–64% compared to traditional design methodologies.

Using Model for Assessment of Complementary Metal Oxide Semiconductor Technology and Roadmaps as a Pre-Simulation Program with Integrated Circuit Emphasis Model Generator for Early Technology and Circuit Simulation

In this work, we show how to use the model for assessment of CMOS technology and roadmaps (MASTAR) in order to generate ready-to-use simple pre-simulation program with integrated circuit emphasis (pre-SPICE) data. Calibration of MASTAR on silicon data is shown, as well as prediction of device behaviour due to architectural changes. The generated pre-SPICE parameters are applied to small circuit simulations such as a 10-bit adder, and we show the impact of variability on static random access memory (SRAM) functionality.

Quantum Mechanical Corrected Simulation Program with Integrated Circuit Emphasis Model for Simulation of Ultrathin Oxide Metal-Oxide-Semiconductor Field Effect Transistor Gate Tunneling Current

In this paper we present a quantum mechanical corrected gate tunneling current model for simulating ultrathin oxide metal-oxide-semiconductor (MOS) devices. By approximating the physically based Esaki-Tsu tunneling formula and explicitly modeling the classical (CL) and quantum mechanical (QM) corrected surface potential, this model successfully predicts the gate tunneling current for ultrathin oxide MOS samples under different applied biases. Simply assuming all tunneling electrons have the same kinetic energy, the Esaki-Tsu tunneling formula is first simplified so that it can be solved without encountering numerical integral problems. Numerical solutions of the classical Poisson equation and Schrödinger-Poisson equations are then used to analytically express the CL and QM corrected surface potentials explicitly in terms of substrate doping, thickness of the gate oxide (Tox), and applied bias. The full explicit, physical-based, and QM corrected gate tunneling current model quantitatively shows good agreement with the technology computer-aided design (TCAD) simulation. Compared with the measured gate tunneling current from fabricated 0.12 µm n-type Metal-Oxide-Semiconductor Field Effect Transistors (NMOSFETs) with three different thicknesses of gate oxide, Tox=1, 1.2 and 1.5 nm, the QM corrected gate tunneling current model shows good accuracy for various ultrathin oxide samples under different biases. However, the gate tunneling current model with the CL surface potential results in one order of magnitude underestimation in comparison with the measured data. We implement the gate tunneling current model into the simulation program with integrated circuit emphasis (SPICE) simulator and perform a DC simulation. Simulated results preliminarily show the effect of the gate leakage current on the drain current without any numerical convergence problem.