Instruction Stream Research Articles

Energy-efficient instruction compression with programmable dictionaries

To improve the energy efficiency of computation, accelerators trade off performance and energy consumption for flexibility. Fixed-function accelerators reach high energy efficiency, but are inflexible. Adding programmability via an instruction set architecture (ISA) incurs an energy consumption overhead, as instructions are fetched and decoded. To reduce it, hardware-controlled instruction caches and software-controlled components, such as loop buffers and (programmable) dictionaries improve the energy efficiency of instruction streams in embedded processors. Reducing the instruction overhead with code compression is well established and dictionary compression has been an effective approach due to its simplicity. Compared to static dictionaries, adding programmability improves the effectiveness. However, run-time-programmable dictionary compression and its effect on energy consumption has not been thoroughly studied. We describe a scheme to target energy efficiency by using fine-grained programmable dictionaries in embedded compute devices. Guided by compile-time analysis, the dictionary contents are changed during execution. On CHStone and Embench suites, our method reduces energy consumption on average by 11.4% and 3.8% with negligible run-time overhead. The addition of a loop buffer further reduces the energy consumption by 19.8% and 4.5% in the two suites. Our results indicate that programmable dictionary compression allows further energy reductions over an already highly tuned instruction stream.

Ditching the Queue: Optimizing Coprocessor Utilization with Out-of-Order CPUs on Compact Systems on Chip

The growing demand for high-performance and energy-efficient processing in edge-oriented Systems-on-Chip is driving the adoption of dedicated integrated circuits that accelerate computationally intensive workloads. To minimize area and performance overhead, low-power, general-purpose CPUs are often tightly coupled with domain-specific coprocessors implementing custom instructions, thereby delivering higher throughput and reduced memory traffic. However, commonly used in-order CPUs are not optimized for instruction-level parallelism, leading to stalls in the instruction stream while waiting for long-latency coprocessor operations and under-utilization of the coprocessor while executing other instructions. This work investigates the benefits of replacing simple in-order cores with a more complex out-of-order architecture to dynamically schedule instructions for the main core and coprocessor, optimizing resource utilization and reducing execution time. To ensure generality, an in-depth analysis was carried out by offloading instructions to a custom dummy coprocessor capable of emulating iterative and pipelined operations with arbitrary latency. Various workloads simulating real-world applications were executed on two variants of an open-source microcontroller equipped with a recent out-of-order core and the state-of-the-art CV32E40X in-order core, respectively. Results from Register Transfer Level simulations show that the former configuration executes up to 60% more instructions per cycle, with a modest 12% system area overhead on a 65 nm CMOS technology node.

"The Golden Hoop" by B. Lyatoshynskyi in the Inheritance of Spiritual and Mythological Instructions of the Musical Theatre of Europe

The purpose of the research is to reveal the poetic and intonation uniqueness of B. Lyatoshynskyi's "The Golden Hoop" in the stream of spiritual and mythological instructions of the European musical theatre of the XIX-XX centuries. Research methodology. Interdisciplinary, historical-cultural, genre-stylistic approaches, which allow us to reveal the spiritual and mysterious foundations of the opera "The Golden Hoop" by B. Lyatoshynskyi and its literary primary source, were essential for this work. The scientific novelty of the article is determined by its analytical perspective, which reveals the spiritual and mysterious genesis of the opera "The Golden Hoop" by B. Lyatoshynskyi, imprinted not only by the poetics of the Ukrainian musical theatre and its spiritual and aesthetic guidelines, but also by the Christian and mythological foundations of the Western European opera of the Romantic era. Conclusions. “The Golden Hoop” by B. Lyatoshynskyi (1929) became an outstanding work of Ukrainian and European musical theatre in general in the first half of the 20th century. On the one hand, this opera arose at the intersection of the “social” ideas of I. Franko and their artistic embodiment in the story “Zakhar Berkut”, as well as the spiritual and ethical guidelines of the work of B. Lyatoshynskyi, formed against the background of the mysterious and mythological background of the Ukrainian “image of the world” and cultures. On the other hand, the spiritual and semantic specificity of the analysed opus with the obvious minimisation of the actual historical factor in it, the strengthening of the mythological beginning (the coexistence of three worlds – gods, heroes and people), the reinterpretation (in comparison with the literary original source) by the authors of the opera of its finale with an emphasis on its sacrificial-redemptive meaning – all this evokes certain analogies between “The Golden Hoop” and a wide range of themes and images of European culture of the past and present and its biblical and Christian mystical background.
 Keywords: “The Golden Hoop” by B. Lyatoshynskyi, “Zakhar Berkut” by I. Franko, mystery and opera, Ukrainian musical culture.

Vectorization Programming Based on HR DSP Using SIMD

Single instruction multiple data (SIMD) vector extension has become an essential feature of high-performance processors. Architectures such as x86, ARM, MIPS, and PowerPC have specific vector extension instruction sets and SIMD micro-architectures. Using SIMD vectorization programming can significantly improve the performance of application algorithms while keeping the hardware overhead low. In addition, other methods can enhance algorithm performance, such as selecting the best SIMD vectorization model for algorithms, ensuring sufficient instruction streams, implementing reasonable and effective cache data prefetching, and aligning data access and storage addresses according to instruction characteristics. The goal of this paper is three-fold. First, we introduce the basic structural characteristics of a general RISC processor, Hua Rui (HR) DSP, with a custom vector instruction set based on compatibility with an MIPS64 fixed-point and floating-point instruction set, as well as a Fei Teng (FT) processor compatible with an ARMv8 instruction set. Second, we summarize the fundamental principles of SIMD vectorization programming design for the HR DSP, which provides ideas for other scholars or engineering and technical personnel to study the algorithm performance using SIMD vectorization optimization. Third, we implement representative typical algorithms based on the HR and FT platforms and obtain experimental results that show improvement in algorithm SIMD vectorization optimization according to the vector programming design principles summarized in this article can improve the single-core performance of scalar implementation without vectorization, instruction streams, and cache data prefetching by 4–22 times for mean filter, accumulation, and matrix–matrix multiplication, which is significantly better than the performance improvement of 3–13 times for the FT platform. Moreover, the performance of matrix–matrix multiplication using the best vectorization model on the HR platform is about 84% higher than that of the common SIMD vectorization model.

A Fast Topological Parallel Algorithm for Traversing Large Datasets

This work presents a parallel implementation of a graph-generating algorithm designed to be straightforwardly adapted to traverse large datasets. This new approach has been validated in a correlated scenario known as the word ladder problem. The new parallel algorithm induces the same topological structure proposed by its serial version and also builds the shortest path between any pair of words to be connected by a ladder of words. The implemented parallelism paradigm is the Multiple Instruction Stream - Multiple Data Stream (MIMD) and the test suite embraces 23-word ladder instances whose intermediate words were extracted from a dictionary of 183,719 words (dataset). The word morph quality (the shortest path between two input words) and the word morph performance (CPU time) were evaluated against a serial implementation of the original algorithm. The proposed parallel algorithm generated the optimal solution for each pair of words tested, that is, the minimum word ladder connecting an initial word to a final word was found. Thus, there was no negative impact on the quality of the solutions comparing them with those obtained through the serial ANG algorithm. However, there was an outstanding improvement considering the CPU time required to build the word ladder solutions. In fact, the time improvement was up to 99.85%, and speedups greater than 2.0X were achieved with the parallel algorithm.

IMPROVING PARALLEL SOLUTIONS FOR METHOD OF LINES TO 1-D HEAT EQUATION BY USING FIVE POINT FINITE DIFFERENE

The aim of the study is to explain the numerical solutions of the one dimensional (1-D) of heat by using method of lines (MOLs). In the (MOLs) the derivative is firstly transformed to equivalent 5 point central finite differences methods (FDM) that is also transformed to the ordinary differential equations (ODEs). The produced (ODEs) systems are solved by the well-known techniques method of ODEs such as the 4th Runge - Kutta method and Runge - Kutta Fehlberg. And since of the conversion of the second derivative to the equivalent of the 5 points FDM which led to an increase in the size of the system equations ODEs, and thus increased we have improved the performance of these (MOLs) techniques by introduce parallel processing to speed up the solution of the produced ODE systems. The developed parallel technique, are suitable for running on MIMD (Multiple Instruction Stream, Multiple Data Stream) computers.

Specially-Designed Out-of-Order Processor Architecture for Microcontrollers

In very large-scale integration circuit (VLSI) systems, microcontrollers are often implanted to manage the whole system to complete the given computing tasks. They play an essential part as regulators, which should allocate resources steadily and issue instructions promptly to drive functional units. However, most of the recent research focuses on the operation at the software level or the scheduling at the SoC level, ignoring the impact of the microarchitecture and the features of controlled sub-modules. This paper analyzes the requirements of microcontrollers in the VLSI system with various constraints and conditions that should be considered in the hardware implementation of such microarchitecture. Furthermore, this paper takes an open-source design using RISC-V ISA as the prototype to implement hardware microarchitecture. This design integrates the techniques of out-of-order processing, which are usually used on superscalar processors. As a result, the design quadruples the number of pipelined instructions, greatly alleviating the stalling of the instruction stream with a maximum extra look up table utilization of 18.37% in FPGA implementation.

The Forward Slice Core: A High-Performance, Yet Low-Complexity Microarchitecture

Superscalar out-of-order cores deliver high performance at the cost of increased complexity and power budget. In-order cores, in contrast, are less complex and have a smaller power budget, but offer low performance. A processor architecture should ideally provide high performance in a power- and cost-efficient manner. Recently proposed slice-out-of-order (sOoO) cores identify backward slices of memory operations which they execute out-of-order with respect to the rest of the dynamic instruction stream for increased instruction-level and memory-hierarchy parallelism. Unfortunately, constructing backward slices is imprecise and hardware-inefficient, leaving performance on the table. In this article, we propose Forward Slice Core (FSC ), a novel core microarchitecture that builds on a stall-on-use in-order core and extracts more instruction-level and memory-hierarchy parallelism than slice-out-of-order cores. FSC does so by identifying and steering forward slices (rather than backward slices) to dedicated in-order FIFO queues. Moreover, FSC puts load-consumers that depend on L1 D-cache misses on the side to enable younger independent load-consumers to execute faster. Finally, FSC eliminates the need for dynamic memory disambiguation by replicating store-address instructions across queues. Considering 3-wide pipeline configurations, we find that FSC improves performance by 27.1%, 21.1%, and 14.6% on average compared to Freeway, the state-of-the-art sOoO core, across SPEC CPU2017, GAP, and DaCapo, respectively, while at the same time incurring reduced hardware complexity. Compared to an OoO core, FSC reduces power consumption by 61.3% and chip area by 47%, providing a microarchitecture with high performance at low complexity.

On the Satisfiability and Model Checking for one Parameterized Extension of Linear-time Temporal Logic

Sequential reactive systems are computer programs or hardware devices which process the flows of input data or control signals and output the streams of instructions or responses. When designing such systems one needs formal specification languages capable of expressing the relationships between the input and output flows. Previously, we introduced a family of such specification languages based on temporal logics $LTL$, $CTL$ and $CTL^*$ combined with regular languages. A characteristic feature of these new extensions of conventional temporal logics is that temporal operators and basic predicates are parameterized by regular languages. In our early papers, we estimated the expressive power of the new temporal logic $Reg$-$LTL$ and introduced a model checking algorithm for $Reg$-$LTL$, $Reg$-$CTL$, and $Reg$-$CTL^*$. The main issue which still remains unclear is the complexity of decision problems for these logics. In the paper, we give a complete solution to satisfiability checking and model checking problems for $Reg$-$LTL$ and prove that both problems are Pspace-complete. The computational hardness of the problems under consideration is easily proved by reducing to them the intersection emptyness problem for the families of regular languages. The main result of the paper is an algorithm for reducing the satisfiability of checking $Reg$-$LTL$ formulas to the emptiness problem for Buchi automata of relatively small size and a description of a technique that allows one to check the emptiness of the obtained automata within space polynomial of the size of input formulas.

Real-time detection of hardware trojan attacks on General-Purpose Registers in a RISC-V processor

Hardware trojans(HT) is one of the main threats for hardware security, especially attacks on General-Purpose Registers(GPRs) of processors. This paper presented a novel method to detect HT induced attacks by comparing the states of GPRs with an embedded reference model in real time. Firstly, the instruction sequence was realigned with four principles. Secondly, based on the realigned instruction stream, a reference model for GPRs was built. Finally, HT induced attacks on GPRs can be detected by comparing the expected GPRs’ state from the reference model with the sampled GPRs’ state from processors. We integrated this method into a RISC-V core of PULpino and investigated the feasibility with different programs. The experimental results showed that all the randomly inserted HT attacks can be detected in real time with the latency of two clock cycles.

Dynamic issue queue capping for simultaneous multithreaded processors

A simultaneous multithreaded (SMT) processor mixes multiple instruction streams in its superscalar out-of-order execution core for higher throughput. To achieve this, a superscalar processor is modified in such a way that someof its resources are duplicated and the rest is shared among multiple threads. The issue queue (IQ), which holds allwaiting instructions until they become ready and scheduled for execution, is among these shared resources. A baselineunmanaged IQ can give an unexpectedly low performance since a hungry thread can tie up most of the IQ entries.This type of scenario is also worse in terms of the fairness metric since some of the threads may experience starvation.Earlier studies propose both static and a limited type of dynamic capping of the IQ entries for regulating IQ traffic andproviding better SMT throughput and fairness. In this study, we propose an e?iciency-based dynamic capping (EDC)algorithm that calculates an efficiency metric for each thread and allocates the IQ entries for maximizing the throughputand the fairness metrics. EDC gives 3.6% better throughput and 3.9% better fairness results compared to the currentstate-of-the-art algorithms, on the average.

Nonlinear Code-Based Low-Overhead Fine-Grained Control Flow Checking

A hardware-based control flow monitoring technique enables the detection of errors in both the control flow and the instruction stream executed on a processor. However, as shown in recent publications, these techniques fail to detect malicious carefully-tuned manipulations of the instruction stream in a basic block. This article presents a non-linear encoder and checker that can cope with this weakness. It is a MAC based control flow checker that has the advantage of working with basic blocks of variable length, can detect every error, and performs the computation in real-time. The architecture can easily be modified to support different signature size and error masking probabilities.

Parallel discontinuous Galerkin finite element method for computing hyperbolic conservation law on unstructured meshes

PurposeThe discontinuous Galerkin finite element method (DGFEM) is very suited for realizing high order resolution approximations on unstructured grids for calculating the hyperbolic conservation law. However, it requires a significant amount of computing resources. Therefore, this paper aims to investigate how to solve the Euler equations in parallel systems and improve the parallel performance.Design/methodology/approachDiscontinuous Galerkin discretization is used for the compressible inviscid Euler equations. The multi-level domain decomposition strategy was used to deal with the computational grids and ensure the calculation load balancing. The total variation diminishing (TVD) Runge–Kutta (RK) scheme coupled with the multigrid strategy was employed to further improve parallel efficiency. Moreover, the Newton Block Gauss–Seidel (GS) method was adopted to accelerate convergence and improve the iteration efficiency.FindingsNumerical experiments were implemented for the compressible inviscid flow problems around NACA0012 airfoil, over M6 wing and DLR-F6 configuration. The parallel acceleration is near to a linear convergence. The results indicate that the present parallel algorithm can reduce computational time significantly and allocate memory reasonably, which has high parallel efficiency and speedup, and it is well-suited to large-scale scientific computational problems on multiple instruction stream multiple data stream model.Originality/valueThe parallel DGFEM coupled with TVD RK and the Newton Block GS methods was presented for hyperbolic conservation law on unstructured meshes.

Micro-architectural analysis of OLAP

Understanding micro-architectural behavior is important for efficiently using hardware resources. Recent work has shown that in-memory online transaction processing (OLTP) systems severely underutilize their core micro-architecture resources [29]. Whereas, online analytical processing (OLAP) workloads exhibit a completely different computing pattern. OLAP workloads are read-only, bandwidth-intensive, and include various data access patterns. With the rise of column-stores, they run on high-performance engines that are tightly optimized for modern hardware. Consequently, micro-architectural behavior of modern OLAP systems remains unclear. This work presents a micro-architectural analysis of a set of OLAP systems. The results show that traditional commercial OLAP systems suffer from their long instruction footprint, which results in high response times. High-performance columnstores execute tight instruction streams; however, they spend 25 to 82% of their CPU cycles on stalls both for sequential- and random-access-heavy workloads. Concurrent query execution can improve the utilization, but it creates interference in the shared resources, which results in sub-optimal performance.

A Kind of Static Software Birthmark Based on Control Flow

In traditional static k-gram birthmark algorithm, the result of plagiarism detection is inaccurate. It is a new method for plagiarism detection that using the software birthmark based on program control flow in this paper. First, it is used to the result of static that analysis of the Java program as meta information, analyze meta information to get byte stream instruction in method. Then, a byte instruction stream in the method to get the control flow structure of the program has been analyzed, and replaced the external references with external control flow structures, using this control flow structure as a software birthmark. Finally, it is calculated that the similarity between two birthmarks by VF2 algorithm, thus determining whether there is plagiarism between the two programs. It is shows that birthmark which presented in this paper are more credible than traditional SKB birthmarks in experimental results.

Sampled Simulation of Task-Based Programs

Sampled simulation is a mature technique for reducing simulation time of single-threaded programs. Nevertheless, current sampling techniques do not take advantage of other execution models, like task-based execution, to provide both more accurate and faster simulation. Recent multi-threaded sampling techniques assume that the workload assigned to each thread does not change across multiple executions of a program. This assumption does not hold for dynamically scheduled task-based programming models. Task-based programming models allow the programmer to specify program segments as tasks which are instantiated many times and scheduled dynamically to available threads. Due to variation in scheduling decisions, two consecutive executions on the same machine typically result in different instruction streams processed by each thread. In this paper, we propose TaskPoint, a sampled simulation technique for dynamically scheduled task-based programs. We leverage task instances as sampling units and simulate only a fraction of all task instances in detail. Between detailed simulation intervals, we employ a novel fast-forwarding mechanism for dynamically scheduled programs. We evaluate different automatic techniques for clustering task instances and show that DBSCAN clustering combined with analytical performance modeling provides the best trade-off of simulation speed and accuracy. TaskPoint is the first technique combining sampled simulation and analytical modeling and provides a new way to trade off simulation speed and accuracy. Compared to detailed simulation, TaskPoint accelerates architectural simulation with 8 simulated threads by an average factor of 220x at an average error of 0.5 percent and a maximum error of 7.9 percent.

On the Prediction of Properties of Benzene using MP4 Method Executed on High Performance Computing with Heterogeneous Platform

High computational complexity problem, high computational cost and deal with a big data are the motivation to study the physical and chemical properties of benzene. Based on the limitation of memory system, processor speed and huge time step computation, we propose the implementation of parallel Gaussian suites of program, particularly the program dealing with high order Moller–Plesset perturbation theory, on high performance homogeneous computing platform (HPC) for predicting the physical and chemical properties of small to medium size molecules, such as benzene, the subject of the present work. Besides high accuracy of the geometrical parameters that can be offered by MP4 simulation, orbital shapes, HOMO-LUMO energy gaps and spectral properties of the molecule are among the properties that can be obtained with accurate prediction. In order to achieve high performance indicators, we need to execute the program in multiple instruction and data stream (MIMD) paradigm using homogenous processors architecture. At the end of this paper, it is shown that Parallel algorithm of Gaussian program using the Linda software can be executed and is well suited in both homogenous and heterogeneous processors. The performance evaluation is essentially based on run time, temporal performance, effectiveness, efficiency, and speedup.

IBM z14: Processor Characterization and Power Management for High-Reliability Mainframe Systems

The IBM z14 is the latest update in the storied history of IBM mainframes. Reliability, availability, security, and scalability are the foundation of the IBM mainframe line. System reliability and availability targets are in excess of 10 years, requiring rigorous chip characterization processes. In this paper, we discuss some of the many processes used to ensure that lifetime. An additional part of this reliability is power management (PM). The 5.2-GHz high-power design of the central processor chip requires advanced on-die PM capabilities to adapt to power intensive instruction streams. We also discuss a number of improvements to the critical path monitoring design used to manage power supply voltage droops, reducing response time and the impact on system performance. Finally, we compare a set of simulations and hardware results to validate our power fluctuation models.

Accelerating finite-rate chemical kinetics with coprocessors: Comparing vectorization methods on GPUs, MICs, and CPUs

Accurate and efficient methods for solving stiff ordinary differential equations (ODEs) are a critical component of turbulent combustion simulations with finite-rate chemistry. The ODEs governing the chemical kinetics at each mesh point are decoupled by operator-splitting allowing each to be solved concurrently. An efficient ODE solver must then take into account the available thread and instruction-level parallelism of the underlying hardware, especially on many-core coprocessors, as well as the numerical efficiency. A stiff Rosenbrock and a nonstiff Runge–Kutta ODE solver are both implemented using the single instruction, multiple thread (SIMT) and single instruction, multiple data (SIMD) paradigms within OpenCL. Both methods solve multiple ODEs concurrently within the same instruction stream. The performance of these parallel implementations was measured on three chemical kinetic models of increasing size across several multicore and many-core platforms. Two separate benchmarks were conducted to clearly determine any performance advantage offered by either method. The first benchmark measured the run-time of evaluating the right-hand-side source terms in parallel and the second benchmark integrated a series of constant-pressure, homogeneous reactors using the Rosenbrock and Runge–Kutta solvers. The right-hand-side evaluations with SIMD parallelism on the host multicore Xeon CPU and many-core Xeon Phi co-processor performed approximately three times faster than the baseline multithreaded C++ code. The SIMT parallel model on the host and Phi was 13%–35% slower than the baseline while the SIMT model on the NVIDIA Kepler GPU provided approximately the same performance as the SIMD model on the Phi. The runtimes for both ODE solvers decreased significantly with the SIMD implementations on the host CPU (2.5–2.7×) and Xeon Phi coprocessor (4.7–4.9×) compared to the baseline parallel code. The SIMT implementations on the GPU ran 1.5–1.6 times faster than the baseline multithreaded CPU code; however, this was significantly slower than the SIMD versions on the host CPU or the Xeon Phi. The performance difference between the three platforms was attributed to thread divergence caused by the adaptive step-sizes within the ODE integrators. Analysis showed that the wider vector width of the GPU incurs a higher level of divergence than the narrower Sandy Bridge or Xeon Phi. The significant performance improvement provided by the SIMD parallel strategy motivates further research into more ODE solver methods that are both SIMD-friendly and computationally efficient.

Modeling Superscalar Processor Memory-Level Parallelism

This paper proposes an analytical model to predict Memory-Level Parallelism (MLP) in a superscalar processor. We profile the workload once and measure a set of distributions to characterize the workload’s inherent memory behavior. We subsequently generate a virtual instruction stream, over which we then process an abstract MLP model to predict MLP for a particular micro-architecture with a given ROB size, LLC size, MSHR size and stride-based prefetcher. Experimental evaluation reports an improvement in modeling error from 16.9 percent for previous work to 3.6 percent on average for the proposed model.