Instruction Granularity Research Articles

Precise Cache Profiling for Studying Radiation Effects

Increased access to space has led to an increase in the usage of commodity processors in radiation environments. These processors are vulnerable to transient faults such as single event upsets that may cause bit-flips in processor components. Caches in particular are vulnerable due to their relatively large area, yet are often omitted from fault injection testing because many processors do not provide direct access to cache contents and they are often not fully modeled by simulators. The performance benefits of caches make disabling them undesirable, and the presence of error correcting codes is insufficient to correct for increasingly common multiple bit upsets. This work explores building a program’s cache profile by collecting cache usage information at an instruction granularity via commonly available on-chip debugging interfaces. The profile provides a tighter bound than cache utilization for cache vulnerability estimates (50% for several benchmarks). This can be applied to reduce the number of fault injections required to characterize behavior by at least two-thirds for the benchmarks we examine. The profile enables future work in hardware fault injection for caches that avoids the biases of existing techniques.

Fine-grained Code Coverage Measurement in Automated Black-box Android Testing

Today, there are millions of third-party Android applications. Some of them are buggy or even malicious. To identify such applications, novel frameworks for automated black-box testing and dynamic analysis are being developed by the Android community. Code coverage is one of the most common metrics for evaluating effectiveness of these frameworks. Furthermore, code coverage is used as a fitness function for guiding evolutionary and fuzzy testing techniques. However, there are no reliable tools for measuring fine-grained code coverage in black-box Android app testing. We present the Android Code coVerage Tool, ACVTool for short, that instruments Android apps and measures code coverage in the black-box setting at class, method and instruction granularity. ACVTool has successfully instrumented 96.9% of apps in our experiments. It introduces a negligible instrumentation time overhead, and its runtime overhead is acceptable for automated testing tools. We demonstrate practical value of ACVTool in a large-scale experiment with Sapienz, a state-of-the-art automated testing tool. Using ACVTool on the same cohort of apps, we have compared different coverage granularities applied by Sapienz in terms of the found amount of crashes. Our results show that none of the applied coverage granularities clearly outperforms others in this aspect.

Simultaneous harvest-and-transmit ambient backscatter communications under Rayleigh fading

Ambient backscatter communications is an emerging paradigm and a key enabler for pervasive connectivity of low-powered wireless devices. It is primarily beneficial in the Internet of things (IoT) and the situations where computing and connectivity capabilities expand to sensors and miniature devices that exchange data on a low power budget. The premise of the ambient backscatter communication is to build a network of devices capable of operating in a battery-free manner by means of smart networking, radio frequency (RF) energy harvesting, and power management at the granularity of individual bits and instructions. Due to this innovation in communication methods, it is essential to investigate the performance of these devices under practical constraints. To do so, this article formulates a model for wireless-powered ambient backscatter devices and derives a closed-form expression of outage probability under Rayleigh fading. Based on this expression, the article provides the power-splitting factor that balances the tradeoff between energy harvesting and achievable data rate. Our results also shed light on the complex interplay of a power-splitting factor, amount of harvested energy, and the achievable data rates.

Template-Based Parameterized Synthesis of Uniform Instruction-Level Abstractions for SoC Verification

Modern system-on-chip (SoC) designs comprise programmable cores, application-specific accelerators, and I/O devices. Accelerators are controlled by software/firmware and functionality is implemented by this combination of programmable cores, firmware, and accelerators. Verification of such SoCs is challenging, especially for system-level properties maintained by a combination of firmware and hardware. Attempting to formally verify the full SoC design with both firmware and hardware is not scalable, while separate verification can miss bugs. A general technique for scalable system-level verification is to construct an abstraction of SoC hardware and verify firmware/software using it. There are two challenges in applying this technique in practice. Constructing the abstraction to capture required details and interactions is error-prone and time-consuming. The second is ensuring abstraction correctness so that properties proven with it are valid. This paper introduces a methodology for SoC design and verification based on the synthesis of instruction-level abstractions (ILAs). The ILA is an abstraction of SoC hardware which models updates to firmware-visible state at the granularity of instructions. For hardware accelerators, the ILA is analogous to the instruction-set architecture definition for programmable processors and enables scalable verification of firmware interacting with hardware accelerators. To alleviate the disadvantages of manual construction of abstractions, we introduce two algorithms for synthesis of ILAs from partial description called templates. We then show how the ILA can be verified to be correct. We evaluate the methodology using a small SoC design consisting of the 8051 microcontroller and two cryptographic accelerators. The methodology uncovered 15 bugs.

A dynamic block-level execution profiler

We introduce a hardware-based mechanism to dynamically profile application blocks.Profiling information is used to prioritize critical memory loads during execution.Our mechanism yields better accuracy and performance gains than previous proposals.We extensively analyze how our mechanism improves performance.Results show that it alleviates prefetch inter-core interference. Most performance enhancing mechanisms in current processors, such as branch predictors or prefetchers, rely on program characteristics monitored at the granularity of single instructions. However, many of these characteristics can be obtained at the basic block-level instead. The coarser granularity allows a larger portion of the code to be examined, enabling a more accurate profiling and a detailed analysis of the different types of instructions executed within a block. Therefore, block-level analysis can be advantageous for performance enhancing mechanisms, as it allows us to look at how the instructions influence each other, and thus detect complex behavior patterns.In this paper, we present the Dynamic Block-Level Execution Profiler (DBLEP), a basic block level online mechanism that profiles micro-architectural bottlenecks, such as delinquent memory loads, hard-to-predict branches and contention for functional units. DBLEP operates at the basic block level and provides information that can be used to reduce the impact of these bottlenecks. A prefetch dropping scheme and a memory controller policy were developed to use the code profiling information provided by DBLEP. By taking advantage of the high profiling accuracy, these mechanisms are able to improve the processor's performance by up to 18.6% (5.3% on average). We show that our mechanism's performance is comparable to mechanisms that work on single instruction granularity, using less hardware.

Investigation of age-differentiated spatial semantic elaboration strategies for communicating route instructions

This paper investigates the effect of spatial semantic elaboration strategies on young and older participants' performance and preferences in a route drawing task where participants read route instructions and then drew the route on a map. In particular, an elaborated form of spatial perspective that communicated the route instruction in both egocentric and allocentric perspectives was compared against just the egocentric or allocentric perspective instructions individually. Additionally, route instruction granularity was varied to compare elaborated hierarchical instructions that communicated goal and landmark information with flat instructions. The results of the experiment showed that older participants performed best with least confusion in the allocentric perspective with flat granularity, but that they benefited from semantic elaboration when less optimal spatial strategies were used, unlike young participants who performed best with the mixed (i.e. elaborated) perspective and flat granularity. The experiment showed that older participants actually suffered from what might be information overload when excess semantic elaboration was provided, as was likely the case with the use of the mixed perspective, which confused them considerably. In addition, hierarchical granularity was only beneficial in confusing spatial perspectives, while it detracted from older participants' performance in their optimal perspective, showing that there is a fine balance to be struck between beneficial semantic elaboration and information overload.

Flexible Hardware Acceleration for Instruction-Grain Lifeguards

Instruction-grain lifeguards monitor executing programs at the granularity of individual instructions to quickly detect bugs and security attacks, but their fine-grain nature incurs high monitoring overheads. This article identifies three common sources of these overheads and proposes three techniques that together constitute a general-purpose hardware acceleration framework for lifeguards.

Flexible Hardware Acceleration for Instruction-Grain Program Monitoring

Instruction-grain program monitoring tools, which check and analyze executing programs at the granularity of individual instructions, are invaluable for quickly detecting bugs and security attacks and then limiting their damage (via containment and/or recovery). Unfortunately, their fine-grain nature implies very high monitoring overheads for software-only tools, which are typically based on dynamic binary instrumentation. Previous hardware proposals either focus on mechanisms that target specific bugs or address only the cost of binary instrumentation. In this paper, we propose a flexible hardware solution for accelerating a wide range of instruction-grain monitoring tools. By examining a number of diverse tools (for memory checking, security tracking, and data race detection), we identify three significant common sources of overheads and then propose three novel hardware techniques for addressing these overheads: Inheritance Tracking, Idempotent Filters, and Metadata-TLBs. Together, these constitute a general-purpose hardware acceleration framework. Experimental results show our framework reduces overheads by 2-3X over the previous state-of-the-art, while supporting the needed flexibility.

A HYBRID SHARED MEMORY EXECUTION MODEL FOR A DATA PARALLEL LANGUAGE WITH I/O

We propose a novel execution model for the implicitly parallel execution of data parallel programs in the presence of general I/O operations. This model is called hybrid because it combines the advantages of the standard execution models fork/join and SPMD. Based on program analysis the hybrid model adapts itself to one or the other on the granularity of individual instructions. We outline compilation techniques that systematically derive the organization of parallel code from data flow characteristics aiming at the reduction of execution mode switches in general and synchronization/communication requirements in particular. Experiments based on a prototype implementation show the effectiveness of the hybrid execution model for reducing parallel overhead.

Location-Based Service Provisioning for Next Generation Wireless Networks

We study how the wireless network infrastructure can support location-based services (LBSs). We assume that each mobile is equipped with self-geolocation capability. The wireless network can provide geolocation information of mobiles to an application services provider (ASP) so that the ASP can customize services based on the geolocation of the users. The main challenge in wireless networking is to keep track of the geolocation of mobile users such that the application service can maintain a certain quality of service (QoS). In general, the quality of service depends on how often mobiles update their geolocation. Because geolocation updates require battery power, radio resources, and signaling in the wired network, optimization of the geolocation update frequency is critical. In this paper, we present geolocation update schemes in which we can minimize the update frequency while satisfying the QoS of application service. For case study, we consider location-based traffic report service (LBS-TR) and location-based navigation service (LBS-NS). In LBS-TR, each mobile user about to enter a heavily jammed highway is informed in a timely manner so that the user can avoid traffic congestion. In LBS-NS, a mobile user is given navigation instructions custom-tailored to the geolocation of the user. The granularity of navigation instructions changes as the user moves from highway to local street and from local street to building complex.

Computer vision algorithms on reconfigurable logic arrays

Computer vision algorithms are natural candidates for high performance computing systems. Algorithms in computer vision are characterized by complex and repetitive operations on large amounts of data involving a variety of data interactions (e.g., point operations, neighborhood operations, global operations). In this paper, we describe the use of the custom computing approach to meet the computation and communication needs of computer vision algorithms. By customizing hardware architecture at the instruction level for every application, the optimal grain size needed for the problem at hand and the instruction granularity can be matched. A custom computing approach can also reuse the same hardware by reconfiguring at the software level for different levels of the computer vision application. We demonstrate the advantages of our approach using Splash 2-a Xilinx 4010-based custom computer.

A Quantitative Analysis of Dataflow Program Execution - Preliminaries to a Hybrid Design

While the dataflow execution model can potentially uncover all forms and levels of parallelism in a program, in its traditional fine grain form it does not exploit any form of locality. Recent evidence indicates that the exploitation of locality in dataflow programs could have a dramatic impact on performance. The current trend in the design of dataflow processors suggests a synthesis of traditional nonstrict fine grain instruction execution and strict coarse grain execution in order to exploit locality. While an increase in instruction granularity favors the exploitation of locality within a single execution thread, the resulting grain size may increase latency among execution threads. We define fine grain intrathread locality as a dynamic measure of instruction level locality and quantify it using a set of numeric and nonnumeric benchmarks. The results point to a very large degree of intrathread locality and a remarkable uniformity and consistency of the distribution of thread locality across a wide variety of benchmarks. As the execution is moved to a coarser granularity it can result in an increase of the input latency of operands that would have a detrimental effect on performance. We evaluate the resulting latency incurred through the partitioning of fine grain instructions into coarser grain threads. We define the concept of a cluster of fine grain instructions to quantify coarse grain input and output latencies. The results of our experiments offer compelling evidence that a coarse grain execution outperforms a fine grain grain one on a significant number of numeric codes. These results suggest that the effects of increased instruction granularity on latency is minimal for a high percentage of the measured codes, and in large part is offset by available intrathread locality. Furthermore, simulation results indicate that strict or nonstrict data structure access does not change the basic cluster characteristics.

An analysis of loop latency in dataflow execution

Recent evidence indicates that the exploitation of locality in dataflow programs could have a dramatic impact on performance. The current trend in the design of dataflow processors suggest a synthesis of traditional non-strict fine grain instruction execution and a strict coarse grain execution in order to exploit locality. While an increase in instruction granularity will favor the exploitation of locality within a single execution thread, the resulting grain size may increase latency among execution threads. In this paper, the resulting latency incurred through the partitioning of fine grain instructions to quantify coarse grain input and output latencies using a set of numeric benchmarks. The results offer compelling evidence that the inner loops of a significant number of numeric codes would benefit from coarse grain execution. Based on cluster execution times, more than 60% of the measured benchmarks favor a coarse grain execution. IN 64% of the cases the input latency to the cluster is the same in coarse or fine grain execution modes. The results suggest that the effects of increased instruction granularity on latency is minimal for a high percentage of the measured codes, and in large part is offset by available intra-thread locality. Furthermore, simulation results indicate that strict or non-strict data structure access does not change the basic cluster characteristics.