Input Vector Control Research Articles

A meta-heuristic search-based input vector control approach to co-optimize NBTI effect, PBTI effect, and leakage power simultaneously

As technology advances, Bias temperature instability (BTI) has become a severe aging challenge that affects the reliability of a device. Previously, NBTI was the most significant aging issue, but with the development of the high-k metal-gate technology, the impact of PBTI can no longer be overlooked. Similarly, in deep submicron technology, leakage power also remains a serious concern. So, minimizing the consequence of the BTI effect and leakage power is the key design goal in today’s technology. As the leakage power and the BTI effects have a strong dependency on the input patterns of the circuit, the input vector control (IVC) technique can be employed to mitigate both of these effects. Previously, IVC techniques have been used to co-optimize the NBTI degradation and the leakage power. In this work, the NBTI effect, PBTI effect, and leakage power are considered simultaneously. Here, a Genetic Algorithm-based (GA) multi-objective meta-heuristic approach is proposed to select the optimum input vector for simultaneous co-optimization of NBTI effect, PBTI effect, and standby leakage power. The proposed approach shows a maximum improvement of NBTI, PBTI, and leakage power by 39.89%, 40.62%, and 37.32%, respectively, with respect to the worst-case solutions of each effect.

Lookup table‐based negative‐bias temperature instability effect and leakage power co‐optimization using genetic algorithm approach

SummaryAs a result of continuous scaling of transistors, negative bias temperature instability (NBTI) has become a serious reliability concern which causes the device to degrade over its lifetime. Similarly, leakage power also remains a key issue in deep submicron technologies. Both NBTI‐related delay degradation and standby time leakage power depend strongly on the circuit's input patterns. The input vector control (IVC) technique can be used for mitigating both NBTI‐related delay degradation and leakage power. However, the input vectors with the least NBTI‐induced degradation may not be the same ones with the least leakage power in any circuit; therefore, co‐optimization is needed to minimize leakage and NBTI‐induced degradation. In this paper, a genetic algorithm (GA)‐based approach is presented to co‐optimize both NBTI‐related performance degradation and also leakage power. We are also presenting a trade‐off analysis by giving different weightage to the NBTI effect and leakage power. Simulation results applied on ISCAS'85 benchmark circuits illustrate that on average our proposed technique saves up to 21.85% and 17.68% circuit performance degradation and the leakage power, respectively.

Interval Arithmetic and Self-Similarity Based RTL Input Vector Control for Datapath Leakage Minimization

With technology scaling, subthreshold leakage has dominated the overall power consumption in a design. Input vector control is an effective technique to minimize subthreshold leakage. Low leakage input vector determination is not often possible due to large design space and simulation time. Similarly, applying an appropriate minimum leakage vector (MLV) to each Register Transfer Level (RTL) module instance in a design often results in a low leakage state with significant area overhead. In this work, we propose a top-down and bottom-up approach for propagating the input vector interval to identify low leakage input vector at primary inputs of an RTL datapath. For each module, via Monte Carlo simulation, we identify a set of MLV intervals such that maximum leakage is within (say) 10% of the lowest leakage points. As the module bit width increases, exhaustive simulation to find the low leakage vector is not feasible. Further, we need to uniformly search the entire input space to obtain as many low leakage intervals as possible. Based on empirical observations, we observe self-similarity in the subthreshold leakage distribution of adder/multiplier modules with highly regular bit-slice architectures when input space is partitioned into smaller cells. This property enables the uniform search of low leakage vectors in the entire input space where the time taken for characterization increases linearly with the module size. We further process the reduced interval set with simulated annealing to arrive at the best low-leakage vector at the primary inputs. We also propose to reduce area overhead (in some cases to 0%) by choosing Primary Input (PI) MLVs such that resultant inputs to internal nodes are also MLVs. Compared to existing work, experimental results for DSP filters simulated in 16nm technology demonstrated leakage savings of 93.6% and 89.2% for top-down and bottom-up approaches with no area overhead.

Gate Level NBTI and Leakage Co-Optimization in Combinational Circuits with Input Vector Cycling

Negative Bias Temperature Instability (NBTI) effect occurs in a PMOS transistor when turned ON leading to threshold voltage degradation. As sub-threshold leakage is significant in nanoscale CMOS circuits, input vector control can be employed wherein a Minimum Leakage Vector (MLV) is applied to the circuit during idle periods. In such a case, the ON PMOS transistors on the critical path are subject to NBTI stress for prolonged periods. Transistors can recover from stress when turned OFF. Based on this observation, we propose a vector cycling based leakage/NBTI co-optimization: a pair of MLVs are identified such that when applied alternately, on the critical path, PMOS transistors activated by one vector are turned OFF by the other vector. We employ Simulated Annealing (SA) for stochastic search of the first vector followed by back tracking to identify the second vector. Experimental results for a subset of ISCAS85 benchmarks implemented in 45 nm technology demonstrate the feasibility of vector cycling approach. When compared to leakage-only optimization, NBTI-only optimization, and co-optimization, on average, vector cycling yields 11, 3, and 6 percent NBTI improvements with 18, -9, and 4 percent leakage overheads respectively. The average area and dynamic power overheads are 13.78 and 0.15 percent respectively.

Leakage Power Minimization using IVC based GSA

The power management has become the major constraint while designing VLSI circuits as parameters like Area, Speed, etc. are critical to be optimized. In this work, a low power 16-bit ALU is designed to perform all arithmetic and logic operations. The present day super computers, mobile gadgets, calculators etc. are using low power ALU systems to perform their tasks. Especially, leakage power occupies major portion of power consumption in the CMOS circuits, as the process technology progresses. The objective of the research work is to reduce leakage power in maximum extent to run the ALU with low power. The proposed model has used IVC based leakage power reduction technique in standby mode by using Gravitational Search Algorithm (GSA). Input Vector Control (IVC) technique is found to be a better alternative in achieving low leakage as it is based on the effect of transistor stacking and it is highly preferred because of its independency over other technological parameters without performance overhead. The GSA locates MLV (Minimum Leakage Vector) in vector combinations of input test circuits of ALU. And then IVC forces the other vector combinations into MLV mode of a test circuit to reduce leakage power. The comparison study has been carried out with Genetic Algorithm (GA) and Particle Swarm Optimization (PSO) algorithm with various test circuits. Power analysis is conducted with GSA to ascertain better leakage reduction and also it locates MLV in less number of iterations. GSA takes only 13 iterations to reach its global space, whereas, PSO takes 62 iterations and GA takes 96 iterations to reach their global space. The simulations are carried out using the Xilinx platform with Verilog coding using PSPICE and MATLAB tools.

NBTI and Power Reduction Using an Input Vector Control and Supply Voltage Assignment Method

As technology scales, negative bias temperature instability (NBTI) becomes one of the primary failure mechanisms for Very Large Scale Integration (VLSI) circuits. Meanwhile, the leakage power increases dramatically as the supply/threshold voltage continues to scale down. These two issues pose severe reliability problems for complementary metal oxide semiconductor (CMOS) devices. Because both the NBTI and leakage are dependent on the input vector of the circuit, we present an input vector control (IVC) method based on a linear programming algorithm, which can co-optimize circuit aging and power dissipation simultaneously. In addition, our proposed IVC method is combined with the supply voltage assignment technique to further reduce delay degradation and leakage power. Experimental results on various circuits show the effectiveness of the proposed combination method.

NBTI and Leakage Reduction Using an Integer Linear Programming Approach

As technology scales, negative bias temperature instability (NBTI) becomes one of the primary failure mechanisms for VLSI circuits. Meanwhile, the leakage power increases dramatically as the supply/threshold voltage continues to scale down. These two issues pose severe reliability problems for CMOS devices. Because both the NBTI and leakage are dependent on input vector of the circuit, we present an input vector control (IVC) method based on an integer linear programming (ILP) approach. A novel NBTI and leakage reduction criterion function as well as an ILP formulation are presented to simultaneously minimize the delay degradation and leakage power. Our proposed ILP formulation can be generated adaptively for different circuits that can help the designers find the optimal input vector conveniently. In addition, the proposed method is combined with the supply voltage assignment technique to further reduce delay degradation and leakage power. Experimental results on various circuits show the effectiveness of the proposed method.

Particle Swarm Optimization Algorithm for Leakage Power Reduction in VLSI Circuits

Abstract Leakage power is the dominant source of power dissipation in nanometer technology. As per the International Technology Roadmap for Semiconductors (ITRS) static power dominates dynamic power with the advancement in technology. One of the well-known techniques used for leakage reduction is Input Vector Control (IVC). Due to stacking effect in IVC, it gives less leakage for the Minimum Leakage Vector (MLV) applied at inputs of test circuit. This paper introduces Particle Swarm Optimization (PSO) algorithm to the field of VLSI to find minimum leakage vector. Another optimization algorithm called Genetic algorithm (GA) is also implemented to search MLV and compared with PSO in terms of number of iterations. The proposed approach is validated by simulating few test circuits. Both GA and PSO algorithms are implemented in Verilog HDL and the simulations are carried out using Xilinx 9.2i. From the simulation results it is found that PSO based approach is best in finding MLV compared to Genetic based implementation as PSO technique uses less runtime compared to GA. To the best of the author’s knowledge PSO algorithm is used in IVC technique to optimize power for the first time and it is quite successful in searching MLV.

NBTI-aware adaptive minimum leakage vector selection using a linear programming approach

Due to the circuit aging effect, the minimum leakage vector (MLV) found by the traditional input vector control method may not obtain the optimal leakage power reduction result when the circuit begins to degrade. To solve this problem, we present an adaptive MLV selection strategy based on a linear programming approach. The method divides the total lifetime of the circuit into a succession of time intervals, and the MLV used in each interval is periodically updated according to the transistor׳s threshold voltage degradation so that the best overall power reduction result can be achieved. Experimental results on various benchmark circuits show the effectiveness of our method.

Gate replacement with PMOS stacking for leakage reduction in VLSI circuits

SummaryScaling down the circuits of complementary metal oxide semiconductor increases the leakage current. Input vector control is an extremely popular method for controlling leakage without using any technological modification. However, it is less effective for larger logic depth circuits.Our study proposes a Worst Leakage State (WLS) free‐node algorithm based on gate replacement technique, in which, when the logic gate of a given circuit goes into WLS, it is replaced by a suitable variant of the gate which in turn reduces the leakage current in an idle mode of the circuit at the same input vector. These variants minimize leakage under WLS conditions. For replacement purpose, four variants (V1–V4) of a two‐input NAND gate are proposed. This technique is applied on different circuits and some benchmark circuits such as ISCAS'85 (C17) and ITC'99 (B01, B02 and B06) (total of 10 circuits), according to the proposed algorithm with variants V1–V4. The average total power is reduced to 15.04%, 15.04%, 35.7% and 31.5%, and the leakage current is reduced to 42.96%, 42.96%, 84.25% and 84.52%, respectively, for variants V1–V4. The average delay is decreased by 16.03% in V1 and V2 variants and increased by 7.74% and 13.16% for variants V3 and V4, respectively, as compared with the results of conventional circuits at 45‐nm Berkeley Predictive Technology Model technology. Copyright © 2015 John Wiley & Sons, Ltd.

A fast input vector control approach for sub-threshold leakage current reduction at nanoscale transistors

This paper presents an efficient algorithm to control and reduce the sub-threshold leakage current at nanoscale transistor level. The proposed algorithm called fast input vector algorithm (FIVA) is based on input vector control (IVC) technique. Simulation results showed that the proposed algorithm is faster than other algorithms implemented using the same technique. The speed of the algorithm increases by increasing the number of transistors comparing with other algorithms having the same target, as well as by increasing the number of input vectors in the circuit. The proposed algorithm showed it is capable to save more power dissipation than other algorithms by reducing and controlling the sub-threshold leakage current when the transistor is in the off state. These results and other comparison results in the rest of the paper validate the efficiency of the proposed algorithm.

Layout-oriented look up table-based dual threshold approach to reduce leakage

As VLSI process technology is advancing with time, the complexity of the circuitry in a single chip is also increasing. Leakage power has now become a major factor in the power equations of a circuit. This paper deals with the reduction of standby leakage power in a technology specific manner. The proposed approach is based on the parameters obtained in post layout condition, which yields more practical results compared to pre layout analysis. Techniques that are used to reduce the leakage power are input vector control, cell replacement, cell upsizing. Capacitance, delay and leakage values of individual gates are calculated by post layout simulation at 45 nm TSMC technology in CADENCE layout tool.

CSAM: A clock skew-aware aging mitigation technique

In this work, we propose a clock skew-aware aging mitigation (CSAM) technique which considers the effect of asymmetric aging both on logic path and clock tree together. Simultaneous consideration of both parts in the design optimization problem enables us to reduce the area overhead while increasing the lifetime. For the aging mitigation of the logic path, we make use of both internal node control (INC) and input vector control (IVC) techniques while, for the clock tree circuits, a proper choice between NAND or NOR based integrated clock gating (ICG) cell is made. The optimization may be performed based on two objective functions of maximizing lifetime or minimizing the area overhead for a predetermined clock frequency and lifetime. To assess the efficacy of the proposed technique, we compared the lifetimes and area overheads for a set of circuits from ISCAS89 and ITC99 benchmark suites when CSAM and conventional techniques are used. The results, obtained using SPICE simulations for the circuits in a 45-nm technology, reveals that an average lifetime improvement of 34% and an average area overhead reduction of 25.7% for the two objective functions, respectively.

A Combined Approach of IVC and GR for Leakage Power Reduction in CMOS VLSI Digital Circuit

In Deep Sub-Micron (DSM) technology, leakage power dissipation consumes the substantial percentage of the total power dissipation and rises exponentially according to the International Technology Roadmap for Semiconductor (ITRS). Leakage power decreases battery life for the entire portable battery operated device such as mobile phones, laptop and cam coder etc. VLSI design constraints are always area, power and delay. To reduce the leakage power losses several techniques has been proposed that proficiently reduces leakage power dissipation Leakage power in CMOS VLSI circuits can be controlled at the circuit level. This paper has considered two run time leakage reduction mechanics i.e. Input Vector Control (IVC) and Gate Replacement (GR). When the first technique is applied on the CMOS circuit, 30% average leakage power reduction is achieved where as 46% of average leakage power is reduces due to GR technique. The Maximum leakage reduction is achieved of 41.2% and 73% due to IVC and GR techniques respectively. These techniques have been applied on ISCAS benchmark circuit C17 using TSMC0.18um technology file on HSPICE simulator.

An Algorithm for Leakage Power Reduction through IVC in CMOS VLSI Digital Circuits

current in CMOS circuits can be controlled at the circuit level and at the device level as well. One of the circuit level control techniques is the Input Vector Control (IVC). By using IVC, leakage power consumption of a circuit can be reduced in the sleep state. In this paper, an algorithm has been given to determine the optimum input vector that can be applied to the circuit in the sleep state for getting low leakage power. This algorithm uses the concept of controllability of the nodes in the circuit and the dependency of a gate on the remaining gates in the circuit to determine the optimum input vector. The proposed algorithm has been applied on an ISCAS benchmark circuit C17, the results showed that the algorithm gives a vector having a leakage nearer to the vector obtained using exhaustive search in CADENCE that gives low leakage value with less execution time as well. Keywordscurrent control, Low leakage vector, VLSI digital circuits, Low leakage power, CMOS combinational circuits.

Reduction of Dynamic Power in Hazards for low voltage CMOS Architectures

Today, there is a large demand for portable electronics for computing and communication. In order to satisfy these requirements, we are focusing on low voltage design techniques. If we reduce the Supply voltage, we also have to reduce the Threshold voltage to maintain the performance. If we reduce the Threshold voltage to lower values, the leakage current cannot be neglected. The leakage power is dependent on the input vector control. This leakage power will get dissipated even when the gates are in ideal condition. We propose a Novel technique. This technique uses a integer linear programming(ILP) model. By using ILP model we are minimizing the leakage power in a dual-threshold static cmos circuit. We also reducing the glitch power by using the smallest number of delay elements. Experimental results show about 96% reduction of leakage power in the 70nm BPTM CMOS technology.

Coignof vantage of Transistor Stack and Input Vector Control Method in Leakage Current Reduction

Coignof vantage of Transistor Stack and Input Vector Control Method in Leakage Current Reduction

Power-Aware Minimum NBTI Vector Selection Using a Linear Programming Approach

Transistor aging is a major reliability concern for nanoscale CMOS technology that can significantly reduce the operation lifetime of very large-scale integration chips. Negative bias temperature instability (NBTI) is a major contributor to transistor aging that affects pMOS transistors. On the other hand, leakage power is becoming a dominant factor of the total power with successive technology scaling. Since the input combinations applied to a logic core have a significant impact on both NBTI and leakage power, input vector control can be used to optimize both phenomena during idle cycles. In this paper, we present an efficient input vector selection technique based on linear programming for cooptimizing the NBTI-induced delay degradation and leakage power consumption during standby mode. Since the NBTI-induced delay degradation and leakage power are not affected by the input vector in the same direction, we provide a pareto curve based on both phenomena. A suitable point from such a pareto curve is chosen based on circuit conditions and requirements during runtime.

M-IVC: Applying multiple input vectors to co-optimize aging and leakage

With technology scaling, aging effect and leakage pose significant challenge on the reliability of integrated circuits. Existing techniques on co-optimizing circuit aging and leakage either implement in an intrusive way or rely on input vector control (IVC) method. However, intrusive schemes increase the design complexity and induce extra delay and area overheads. IVC method becomes ineffective as the circuit scale increasing. In this paper, a non-intrusive scheme exploiting multiple input vectors (M-IVC) is proposed to co-optimize NBTI-induced degradation and leakage when the circuit steps into standby mode. M-IVC grounds on a new co-optimization model which formulates both the NBTI-induced delay degradation and the average standby leakage as the function of duty cycle. This co-optimization model facilitates to identify a set of optimal duty cycles which result in minimum NBTI-induced degradation and leakage simultaneously. To achieve the optimal duty cycles, an ATPG-like algorithm is proposed to generate multiple input vectors and determine the applying time for each vector. Experimental results demonstrate that with only a small number of vectors, M-IVC can effectively optimize NBTI-induced delay degradation and leakage together and keep the effectiveness as the time of standby period increasing.

Temperature-Aware NBTI Modeling and the Impact of Standby Leakage Reduction Techniques on Circuit Performance Degradation

As technology scales, Negative Bias Temperature Instability (NBTI), which causes temporal performance degradation in digital circuits by affecting PMOS threshold voltage, is emerging as one of the major circuit reliability concerns. In this paper, we first investigate the impact of NBTI on PMOS devices and propose a temporal performance degradation model that considers the temperature variation between active and standby mode. We then discuss the resemblance between NBTI and leakage mechanisms, and find out that the impact of input vector and internal node on leakage and NBTI is different; hence, leakage and NBTI should be optimized simultaneously. Based on this, we study the impact of standby leakage reduction techniques (including input vector control and sleep transistor insertion) on circuit performance degradation considering active and standby temperature differences. We demonstrate the potential mitigation of the circuit performance degradation by these techniques.