Input/output Buffer Information Specification Research Articles

Signal and Power Integrity IO Buffer Modeling Under Separate Power and Ground Supply Voltage Variation of the Input and Output Stages

This work presents an improved input–output (IO) buffer model for signal and power integrity simulation, including power/ground supply voltage (PGSV) variations for the buffer’s input and output stages. Both stages are mathematically modeled from a formulation that is derived from nonlinear electrical circuit analysis, an important aspect that grants these models a good level of generality and, simultaneously, high accuracy. The proposed IO buffer model is linear in the parameters and, therefore, extractable through the linear least-squares technique from the signals acquired in an IO buffer characterization setup. Several validation scenarios, supported on two CMOS driver’s transistor technologies, are performed to evaluate the accuracy of the proposed model. In addition, a comparative analysis is provided, confronting the proposed model’s performance against that of the input/output buffer information specification (IBIS) model, evidencing an outstanding modeling improvement provided by the proposed model.

IBIS MODEL OUTPUT IMPEDANCE CORRECTION APPROACH USING CCCS

With the CMOS technology size scaling aggressively and the transmitter (TX) outp¬u¬t resistance becoming smaller and smaller, it becomes necessary to have a good impedance correlation between TX and receiver (RX). The mismatch between the impedances can cause a noise and a response which will dramatically decrease the efficiency of the circuit. Nowadays, those mismatches are being tested using IBIS (Input/output Buffer Information Specification) models owing to low cost and testing speed. A method is proposed to use a current-controlled current source (CCCS) which will decrease the mismatch and make it less than 1%. The proposed method can be implemented for all types of TX drivers and IBIS models.

Analysis of Pre-Driver and Last-Stage Power-Ground-Induced Jitter at Different PVT Corners.

This paper presents the study of power/ground (P/G) supply-induced jitter (PGSIJ) on a cascaded inverter output buffer. The PGSIJ analysis covers the IO buffer transient simulation under P/G supply voltage variation at three process, voltage, and temperature (PVT) corners defined at different working temperatures and distinct DC supply voltages at the pre-driver (i.e., /) and last stage (i.e., ). Firstly, the induced jitter contributions by the pre-driver, as well as the last, stage are compared and studied. Secondly, the shared and decoupled P/G supply topologies are investigated. The outcomes of these simulation analyses with respect to worst case jitter corners are determined, while highlighting the importance of modeling the pre-driver circuit behavior to include the induced jitter in the input–output buffer information specification (IBIS)-like model. Accordingly, the measured PGSIJ depends on the corners to be analyzed and, therefore, the designer needs to explore the worst-case corner for the driver’s technology node and the most supply voltage noise affecting the jitter output for signal and power integrity (SiPI) simulations. Finally, the jitter transfer function sensitivity to the amplitude and frequency/phase variations of the separate and combined impacts of the pre-driver and last stage are explored, while discussing the superposition of the power supply induced jitter (PSIJ) induced by both the driver’s IO stages under small signal and large signal supply voltage variations. The linear superposition of the separate PSIJ effects by the pre-driver and last stage depends on the amplitude of the variation of the supply voltage that can drive the transistor to their nonlinear working regions.

Neural-Network Based Modeling of I/O Buffer Predriver under Power/Ground Supply Voltage Variations.

This paper presents a neural-network based nonlinear behavioral modelling of I/O buffer that accounts for timing distortion introduced by nonlinear switching behavior of the predriver electrical circuit under power and ground supply voltage (PGSV) variations. Model structure and I/O device characterization along with extraction procedure were described. The last stage of the I/O buffer is modelled as nonlinear current-voltage (I-V) and capacitance voltage (C-V) functions capturing the nonlinear dynamic impedances of the pull-up and pull-down transistors. The mathematical model structure of the predriver was derived from the analysis of the large-signal electrical circuit switching behavior. Accordingly, a generic and surrogate multilayer neural network (NN) structure was considered in this work. Timing series data which reflects the nonlinear switching behavior of the multistage predriver’s circuit PGSV variations, were used to train the NN model. The proposed model was implemented in the time-domain solver and validated against the reference transistor level (TL) model and the state-of-the-art input-output buffer information specification (IBIS) behavioral model under different scenarios. The analysis of jitter was performed using the eye diagrams plotted at different metrics values.

Wireless Power Transfer and In-Vehicle Networking Integration for Energy-Efficient Electric Vehicles

This paper presents the wireless power transfer (WPT) technology based on inductive coupling and the design challenges of a hybrid energy harvester (EH) circuit as a promising solution to promote the energy efficiency of the electric vehicles (EVs). The design methodologies of ultra-low power (ULP) electronic module based on low leakage conditioning and processing device are detailed based on nanoscale transistor technology so that the WPT and hybrid EH can be implemented for self-powered devices in EVs. Moreover, in-vehicle network design verification based on a new power-aware behavioral model formulation and extraction for high-speed and ULP transceivers that enables the transient prediction of power and ground currents and voltages when multiple drivers are simultaneously switching for signal-power integrity evaluation. The derivation of the proposed model is based on the analysis and extension of the input/output buffer information specification (IBIS). The analysis of the previous IBIS and Mpilog modeling approaches is followed by a new model formulation along with a well-designed characterization and parametric extraction procedure.

Reduced-Order Parametric Behavioral Model for Digital Buffers/Drivers With Physical Support

In this paper, we present a new behavioral model for high-speed digital output buffers/drivers. In the conceived model, the output current's relationship with the output voltage is expressed as a summation of a static nonlinearity plus linear dynamics. This separation in the model format is supported by the measurements as well as the physical structure of a general driver circuit. This approach merges the features of equivalent circuit and parametric approaches to build a reduced-order parametric behavioral model which, compared to other published models, is more adequate to describe the device's electrical behavior from transient input-output data. A simple single-step identification procedure is conceived to extract a model that proved to be stable and capable of significantly improving the simulation speed and accuracy of prediction. Finally, the resulting model is validated in a realistic signal integrity simulation setup, and is compared to transistor-level models and to the state-of-the-art input-output buffer information specification model.

Improving Behavioral IO Buffer Modeling Based on IBIS

High level behavioral modeling is widely used in lieu of low level transistor models to ascertain the behavior of input/output (IO) drivers and receivers. The input output buffer information specification (IBIS) is one of the most widely used methodologies to model IO drivers as it satisfies the basic requirements of a behavioral model such as IP protection, simple structure, fast simulation time, and reasonable accuracy. As driver technology gets increasingly complicated and rise time of input signal gets increasingly smaller, important considerations such as simultaneous switching noise (SSN) becomes a major consideration when simulating multiple IO drivers in the integrated circuit. Unfortunately, IBIS falls short of becoming a complete IO behavioral model when simulating for SSN. This paper addresses the problem by assessing what is missing in IBIS. A method is presented for compensating for the missing information by complimenting the IBIS model with a black box that is simulator independent, without compromising with the speed that IBIS enjoys over the transistor models.

A Modified IBIS Model Aimed at Signal Integrity Analysis of Systems in Package

Input-output buffer information specification BIS (IBIS) models are descriptions of the output buffers, used by the printed circuit board (PCB) designer to evaluate the integrity and the quality of the signals. The extension of the use of IBIS models to the system in package (SiP) world is considered. It is found that IBIS models demonstrate some limits for this application, mainly due to the poor stabilization of the supply voltage rails. An example highlighting the IBIS model limits is given. A simple hand analysis of the phenomenon is performed, from which we derive a simple solution to the problem, consisting in an improvement of the structure of the IBIS model. Simulations run making use of the improved models show a much better accuracy of the signal shapes, within 5% of the simulations run with a state-of-the-art transistor level description of the buffers.

IBIS and ICEM interaction

This paper provides an introductory overview of recent developments from two standards-producing committees that will lead to electrical component models suitable for electromagnetic compliance simulation. One committee has produced the Input/Output Buffer Information Specification (IBIS) Version 3.2, and the other, the pending Integrated Circuit Electromagnetic Model (ICEM) document. Currently the ICEM document provides a core power supply model in terms of an IBIS-like syntax. However, the IBIS committee is working on a multi-lingual syntax extension to leverage existing languages (SPICE, VHDL-AMS, and Verilog-AMS) for an upcoming Version 4.1 release. The IBIS extension will enable faster adoption and usage of ICEM circuit constructs. This paper discusses aspects of multi-lingual tool evolution and ICEM model application.