Input Clock Signal Research Articles

Process-Resilient Fault-Tolerant Delay-Locked Loop Using TMR With Dynamic Timing Correction

A delay-locked loop (DLL) circuit is often useful for the clock synchronization in a chip incorporating multiple functional dies. In this work, we present a process-resilient fault-tolerant DLL design. We will first show that a naïve triple-module redundancy (TMR) technique cannot work well unless with a simple yet powerful static timing correction scheme to nullify the adversary effect caused by the voter circuit’s delay. Furthermore, we enhance it with a dynamic scheme so that the overall performance is immune to process variation. Through the proposed schemes, the maximum phase error over 1000 clock cycles between the DLL’s input and output clock signals after locking, which is often considered as the most important performance metric, can be reduced tremendously from 130 ps using only naïve TMR to 20 ps using static timing correction, and then further down to 11 ps using the dynamic timing correction.

Online Safety Checking for Delay Locked Loops via Embedded Phase Error Monitor

In today's automotive ICs, online safety checking is often required in order to achieve a high Automotive Safety Integrity Level (ASIL). For a Delay-Locked Loop (DLL), the most important safety (or health) indicator is the “phase error between the input clock signal and the output clock signal”. In this paper, we present a phase error monitoring scheme for DLLs, using circuits made of only standard cells. The proposed scheme can monitor the phase error continuously to record its worst-case values during a designated monitoring session. As a result, hazardous phase error glitches can be exposed and an alarm can be raised. We have implemented this monitoring scheme for a Delay Lock Loop in a 90 nm CMOS process and post-layout simulation is conducted to verify its effectiveness. Experimental results show that it can help expose hazards induced by dynamic power glitches that occurs within 1ns.

On-chip debugging for microprocessor design

This article proposes a closer-to-metal approach of RTL inspection in microprocessor design for use in education, engineering, and research. Signals of interest are tapped throughout the microprocessor hierarchical design and are then output to the top-level entity and finally displayed to a VGA monitor. Input clock signal can be fed as slow as one wish to trace or debug the microprocessor being designed. An FPGA development board, along with its accompanying software package, is used as the design and test platform. The use of VHDL commands ’type’ and ’record’ in the hierarchy provides key ingredients in the overall design, since this allows simple, clean, and tractable code. The method is tested on MIPS single-cycle microprocessor blueprint. The result shows that the technique produces more consistent display of the true contents of registers, ALU input/output signals, and other wires – compared to the standard, widely-used simulation method. This approach is expected to increase confidence in students and designers since the reported signals’ values are the true values. Its use is not limited to the development of microprocessors; every FPGAbased digital design can benefit from it.

A DUAL MODULATION PULSE POSITION MODULATION APPROACH IN 130NM CMOS TECHNOLOGY FOR TIME BASED SERIAL COMMUNICATION LINKS

A time-based serial data link architecture that involves dual modulation Pulse Position Modulation approach (DMPPM) is presented in this paper. In the proposed approach, both the rising and falling edges of the input clock signal are modulated independently. Using the proposed approach allows increasing the total number of transmitted bits without significantly affecting the modulated signal bandwidth. A 6-bit 4.8 Gb/s DMPPM link design example has been designed and simulated based on the proposed approach in 130nm CMOS technology. An 800MHz has been used as an input clock signal. The simulation results and a comparison between the proposed link and other serial links are presented. The power consumption of the transmitter and the receiver circuits are less than 100mW.

Adaptive timing correction technique for pulse-amplitude and pulse-position modulation interface

ABSTRACTA timing correction approach is proposed in this article to improve the performance of high-speed serial data link involving pulse position modulation (PPM) and pulse amplitude modulation (PAM) techniques. The proposed technique corrects the timing error that arises from combining the PAM approach with the PPM approach, which allows transmitting more bits and hence achieving higher data rate for the designed serial link. The proposed technique uses the recovered AM bits to adapt the reference voltage of the comparator circuit at the receiver side in order to correct the jitter results from combining the time modulation with the amplitude modulation. A 5-bit 4-Gb/s serial data link that involves PAM and PPM has been designed and simulated using the proposed technique in 130 nm CMOS technology using 800 MHz as an input clock signal. The simulation results indicate that when combining AM and PPM techniques, the total number of the transmitted bits can be increased using the proposed technique. The total power consumption of the proposed link is less than 84 mW. A performance comparison between the proposed link and other serial links has been carried out that indicates an improved performance for serial links involving the proposed technique.

Effect of PVT variations on differential-time signaling data link architecture

In this paper, the effect of process, voltage and temperature (PVT) variation on the differential-time signaling (DTS) serial link architecture has been studied. An example of 65 nm CMOS 4-bit 6 Gb/s DTS serial link has been designed and simulated using 1.5 GHz as an input clock signal in order to study the effect of PVT variation on DTS architectures. Mont-Carlo simulations have been carried out for the designed link. The simulated link has been tested under different operating temperatures from 0 to 120 °C, the link achieves correct transmission for the temperature range from 0 to 80 °C without calibrating the delay lines against the temperature change. The voltage supply has been varied from 0.95 to 1.05 V in order to study the effect of the voltage supply variation. The simulated link achieves correct transmission for a voltage supply variation within ± 2.5% of the nominal value without calibrating the delay lines against the voltage supply change. Using the DTS architecture as a serial link tolerate an adequate amount of PVT variation as well as relaxes the design constrains of the calibration technique, which is required for the delay lines to ensure correct transmission.

Pulse amplitude-modulated time-based interface for off-chip interconnect

ABSTRACTAn increased number of bits pulse amplitude-modulated differential-time signalling interface for off-chip interconnect is introduced in this article by combining the differential time signalling (DTS) technique with the pulse amplitude-modulation (PAM) approach. Applying the PAM to the DTS-transmitted signal increases the total number of the transmitted bits per symbol while maintaining the transmitted signal bandwidth. 4-bit 6 Gb/s DTS serial link has been designed and simulated using 65 nm CMOS mixed signal technology. 5-bit 7.5 Gb/s and 6-bit 9 Gb/s amplitude-modulated DTS serial links have been designed, simulated and compared to the 6 Gb/s DTS serial link. The three serial links use 1.5 Gb/s as input clock signal. In the amplitude-modulated DTS-transmitted signal, the rising and falling edges of the input clock signal are modulated in time as well as the transmitted signal amplitude is modulated. A reference clock pulse is generated from the input clock signal and embedded on the transmitted signal to be used as reference timing at the receiver circuit. The design details of the designed links are presented in the article. The 9 Gb/s link uses a 60 cm 4003C Rogers substrate as a transmission channel. The transmitted signal spectrum is presented and compared for the three designed links. The total power consumption of the 9 Gb/s amplitude-modulated DTS interface is less than 25 mW.

Single event upset induced by single event double transient and its well-structure dependency in 65-nm bulk CMOS technology

Single event upset (SEU) is one of the most important origins of soft errors in aerospace applications. As technology scales down persistently, charge sharing is playing a more and more significant effect on SEU of flip-flop. Charge sharing can often bring about multi-node charge collection in storage nodes and non-storage nodes in a flip-flop. In this paper, multi-node charge collection in flip-flop data input and flip-flop clock signal is investigated by 3D TCAD mixed-mode simulations, and the simulate results indicate that single event double transient (SEDT) in flip-flop data input and flip-flop clock signal can also cause a SEU in flip-flop. This novel mechanism is called the SEDT-induced SEU, and it is also verified by heavy-ion experiment in 65 nm twin-well process. The simulation results also indicate that this mechanism is closely related with the well-structure, and the triple-well structure is more effective to increase the SEU threshold of this mechanism than twin-well structure.

Analysis of Jitter-Induced Voltage Noise in Clock Channels

Effects of transmit jitter on lossy clock channel are analyzed analytically by treating the 1010 input clock signal as a sinusoidal wave with a phase modulation that represents jitter. Jitter-to-amplitude-modulation transfer functions are derived for sinusoidal jitter, duty-cycle distortion (DCD), and random jitter (RJ) in terms of the signal transfer function or S-parameters. Input jitter is shown to induce amplitude modulation in the output signal as a result of channel dispersion, leading to voltage noise at the channel output. DCD- and RJ-induced voltage noises are found to scale uniquely with channel loss. To verify the theory, numerical simulations are performed on channels with different losses and at various data rates. The input clock signal is represented with a square wave, and the output signal is calculated by linear superposition of the channel step response. Theoretical and simulation results are found to be in excellent agreement.

RESCUE - reduction of MR-SNR-degradation by using an MR-synchronous low interfering PET acquisition technique.

The combination of PET and MRI is a challenging task, since both imaging modalities might influence each other. For unaffected imaging performance, PET detectors need to be untouched by the MR operation (MR-compatible) and RF-silent. The latter requirement is demanding, as the digital Data Acquisition and Control Architecture (DACA) produce noise in the MRI receive chain and thus deteriorate the Signal-to-Noise Ratio (SNR). To reduce these MRI-SNR degradations, we propose “RESCUE”, a MR-synchronously gated PET data acquisition technique. By controlling the PET-modules’ digital data acquisition in terms of interrupting the digital SiPM (dSiPM) operation during the MR signal receive phases, potential RF interferences can be reduced. The concept and design of RESCUE are based on the DACA of Hyperion-IID using 960 dSiPMs from Philips which are spread over 10 PET modules, every module containing 6 detector stacks. 16 dSiPMs are populated on one detector stack and a local FPGA per stack is used to clock and configure the dSiPMs and acquire data from them. To interrupt the PET data acquisition when the MRI is in receive-mode, an MRI trigger signal is sent via the backbone of the PET insert to all PET modules. In the stacks, the dSiPM-operation is interrupted by gating the dSiPMs’ input clock signals. This clock switch-off needs to be performed at a point in time when no dSiPM cell recharge takes place, as sensor-damage might otherwise occur. We implemented FPGA firmware to stop the above described dSiPM operation and to restart it upon release of the gating. PET-data was acquired using gating-sequences and analysis of sensor data acquired before and after interruption showed that the sensors were working properly after reapplying their clock signals. More details and MRI SNR-measurement results to demonstrate the interference reduction obtained with RESCUE will be presented at the conference.

35.4: Programmable Pulse Width LTPS TFT Shift Register for High Resolution and High Frame Rate Active Matrix Flat Panel Displays

AbstractThis paper proposes a programmable pulse width LTPS TFT shift register where an output pulse width is programmed only by adjusting a start pulse width without any additional clock signals and reconfiguration. Since an overlap interval of the output pulses is easily controlled in the shift register which operates with precharging scheme, the proposed shift register can be applied to high resolution and high frame rate display without the problem of insufficient line time. The performance of this circuit is verified by SMART SPICE at low‐temperature poly silicon (LTPS) thin film transistor (TFT) process. The pulse width is changed by the step size of two line time with only two input clock signals which leads to small area for circuit implementation and simulated power consumption is similar to that of the conventional shift register.

A radiation-hard PLL for frequency multiplication with programmable input clock and phase-selectable output signals in 130 nm CMOS

A PLL (ePLL) is presented that is intended to be used as a frequency multiplier. The ePLL accepts 40, 80, 160 or 320MHz as a reference and generates clocks at the same frequencies, regardless of the input clock. Moreover, the outputs are available with a phase resolution of 90° for the 40, 80 and 160MHz output and 22.5° for the 320MHz output. The radiation-hard design, integrated in a 130nm CMOS technology, is able to operate at a supply voltage between 1.2V and 1.5V.

All Printed Edge-Triggered Register Using Single Walled Carbon Nanotube-Based Thin Film Transistor

We have studied the fabrication of Single Walled Carbon Nanotube (SWNT)-based Thin Film Transistors (TFTs) using Roll-to-Roll (R2R) gravure printer and inkjet printer on PET foils to show the possibility of printed electronics in point of mass production and low cost. In this paper, for realization of all printed multi-bits digital circuit, all printed positive-edge triggered master-slave D flip-flop (DFF) was fabricated on PET foil using printed SWNT TFTs. The printed DFF, consists of 8 NAND gates and 4 inverters, exhibit propagation delay of 75 ms at the input clock signal of 5 Hz.

Simple implementation of control gate signals for the interleaved LLC resonant converter for high current application

AbstractA novel method of the gate signal generation for the interleaved LLC converter is proposed, which is based on the relationship between the output signal of a toggle flip‐flop having the double period of the input clock signal and the output gate signal of the LLC controller having almost half‐duty cycle. The gate signals for the master and slave converters are generated using the rising and falling edge instants from the original control gate signal of the controller, respectively. Therefore, the required 90° phase difference between two signals can be always kept at any instant and at any output load condition. Copyright © 2010 John Wiley & Sons, Ltd.

Clock buffer with duty cycle corrector

A clock buffer with duty cycle corrector circuit is presented. The proposed circuit can generate either 50% duty cycle or conserve the duty cycle as input clock. It corrects the input duty cycle of 10–90% for generated 50% duty cycle of output clock with error less than 0.9%. Moreover, it enhances the input clock signal driving ability and keeps the same duty cycle as input clock within range from 20% to 80% with a maximum duty error of 0.5%. The proposed circuit operation frequency range is from 100MHz to 1GHz. The proposed circuit has been fabricated in a 0.18μm CMOS technology.

Optical control of period doubling in a gain-switched Fabry–Perot laser diode and its application in all-optical clock division

Optical injection is shown to be an effective means to suppress or to enhance period doubling of a gain-switched laser diode. The role that the injection plays depends on whether the laser resonance frequency is larger or smaller than half the modulation frequency. Reversible control of period doubling has been demonstrated experimentally using a modulated injection source. An injection power as low as 0.03 mW has been used to control the output pulse repetition frequency of the slave laser. The response time is measured to be shorter than 100 ps. The phenomenon has been applied successfully for use in all-optical clock frequency division. Replacing the electrical modulation with an input clock signal at 19.6 GHz, a frequency-halved output clock with a remarkable low-level phase noise (−87.7 dBc/Hz at 10 kHz offset frequency) has been obtained. The change in the phase noise level is observed to be smaller than 1 dB over a frequency detuning range of 400 MHz.