Injection-locked Ring Oscillator Research Articles

An Energy-Efficient and High-Data-Rate IR-UWB Transmitter for Intracortical Neural Sensing Interfaces.

This paper presents an implantable impulse-radio ultra-wideband (IR-UWB) wireless telemetry system for intracortical neural sensing interfaces. A 3-dimensional (3-D) hybrid impulse modulation that comprises phase shift keying (PSK), pulse position modulation (PPM) and pulse amplitude modulation (PAM) is proposed to increase modulation order without significantly increasing the demodulation requirement, thus leading to a high data rate of 1.66 Gbps and an increased air-transmission range. Operating in 6 - 9 GHz UWB band, the presented transmitter (TX) supports the proposed hybrid modulation with a high energy efficiency of 5.8 pJ/bit and modulation quality (EVM< -21 dB). A low-noise injection-locked ring oscillator supports 8-PSK with a phase error of 2.6°. A calibration free delay generator realizes a 4-PPM with only 115 μW and avoids potential cross-modulation between PPM and PSK. A switch-cap power amplifier with an asynchronous pulse-shaping performs 4-PAM with high energy efficiency and linearity. The TX is implemented in 28 nm CMOS technology, occupying 0.155mm2 core area. The wireless module including a printed monopole antenna has a module area of only 1.05 cm2. The transmitter consumes in total 9.7 mW when transmitting -41.3 dBm/MHz output power. The wireless telemetry module has been validated ex-vivo with a 15-mm multi-layer porcine tissue, and achieves a communication (air) distance up to 15 cm, leading to at least 16× improvement in distance-moralized energy efficiency of 45 pJ/bit/meter compared to state-of-the-art.

Analysis of Injection-Locked Ring Oscillators for Quadrature Clock Generation in Wireline or Optical Transceivers

Injection-locked ring oscillators (ILROs) are widely used for quadrature clock generators (QCG) in multi-lane wireline or optical transceivers because of their low power, low area, and technology scalability. However, locking a four-stage I/Q oscillator with a two-phase injection signal generates imbalances in amplitude and phase, resulting in I/Q phase errors and degraded jitter performance. This paper proposes a modified frequency-domain analysis with amplitude constraint for even-phase ILROs. Combining theoretical derivations with simulation results in 28nm CMOS technology, the behaviors of ring oscillators with partial injection and ILRO-based QCG are discussed and concluded.

Multi-Phase Clock Generation for Phase Interpolation With a Multi-Phase, Injection-Locked Ring Oscillator and a Quadrature DLL

We present a high-accuracy, low-jitter, multi-phase clock generator (MPCG) based on a multi-phase, injection-locked ring oscillator (MPIL-ROSC) with a quadrature delay-locked loop (QDLL). The QDLL tunes the ring oscillator (ROSC) self-oscillation frequency ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${f}_{{0}}$ </tex-math></inline-formula> ) and provides it with multi-phase injection signals. The proposed architecture breaks the intrinsic tradeoff between jitter and phase accuracy in two-phase injection-locked ROSCs. The MPCG’s eight-phase output clock drives a 7-bit phase interpolator (PI) for phase and frequency deskew. A 1.2-V 65-nm CMOS MPCG prototype chip has a better-than-1° eight-phase accuracy and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$58.8~\mathrm {fs}_{\mathrm {rms}}$ </tex-math></inline-formula> jitter (integrated from 100 kHz to 1 GHz), while consuming 15.6 mW at 7 GHz, yielding a −252.7-dB figure of merit ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mathrm {FOM}_{\mathrm {jitter}}$ </tex-math></inline-formula> ). The peak-to-peak integral nonlinearity (INL) and the peak-to-peak differential nonlinearity (DNL) of the PI are less than 1.9 and 1.2 LSB, respectively, across a frequency range from 5 to 8 GHz.

An IR-UWB IEEE 802.15.4z Compatible Coherent Asynchronous Polar Transmitter in 28-nm CMOS

A low-power IEEE 802.15.4z high-rate PHY (HRP) compatible coherent transmitter is described. The proposed transmitter uses a digital polar architecture with fixed amplitude steps in the power amplifier and asynchronous time-discrete pulse shaping. The pulse-shaping unit consists of a finite-impulse response (FIR) filter using current-starved inverter-based delay taps that can be calibrated on-chip. An injection-locked ring oscillator (ILRO)-based frequency synthesis enables wideband operation from 3- to 10-GHz frequency bands. The ILRO also allows for duty-cycled coherent mode operation with 2–4-ns phase locking time and binary phase modulation is applied directly on the oscillator. The on-chip digital front end enables duty cycling (DC) of analog front-end modules with a granularity of 2 ns. Implemented in 28-nm CMOS process, this chip is measured to consume 4.9-mW power in nominal mode with IEEE 802.15.4z high pulse repetition frequency (HPRF) compatible data rate of 6.81 Mb/s compliant with major spectrum mask regulations for channels 5 and 9. With DC of the oscillator enabled in the energy-efficient mode, a power consumption of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$430~\mu \text{W}$ </tex-math></inline-formula> is achieved for packets compatible with legacy pulse-position-modulated IEEE 802.15.4a standard with a data rate of 27.2 Mb/s.

An Energy-Efficient UWB Transmitter with Wireless Injection Locking for RF Energy-Harvesting Sensors.

An ultralow-power ultrawideband (UWB) transmitter with an energy-efficient injection-locked radio frequency (RF) clock harvester that generates a carrier from an RF signal is proposed for RF energy-harvesting Internet-of-Things (IoT) sensor applications. The energy-efficient RF clock harvester based on the injection-locked ring oscillator (ILRO) is proposed to achieve optimal locking range and minimum input sensitivity to obtain an injection-locked 450 MHz clock in ultralow-power operation. A current-starved inverter-based delay stage is adopted that allows delay adjustment by bias voltage to minimize dynamic current consumption while maintaining a constant delay regardless of changes in process, supply voltage, and temperature (PVT). To minimize static current consumption, a UWB transmitter based on a digital-based UWB pulse generator and a pulse-driven switching drive amplifier is proposed. The proposed injection-locked RF clock harvester achieves the best RF input sensitivity of −34 dBm at a power consumption of 2.03 μW, enabling energy-efficient clock harvesting from low RF input power. In ultralow-power operation, a 23.8% locking range is achieved at the RF injection power of −15 dBm to cope with frequency changes due to PVT variations. The proposed UWB transmitter with RF clock harvester achieves the lowest energy consumption per pulse with an average power consumption of 97.03 μW and an energy consumption of 19.41 pJ/pulse, enabling operation with the energy available in RF energy-harvesting applications.

A Low-Spur and Intrinsically Aligned IL-PLL With Self-Feedback Injection Locked RO and Pseudo-Random Injection Locked Technique

A novel injection-locked phase locked loop (IL-PLL) with low spur and low phase noise is presented in this paper, in which self-feedback injection locked ring oscillator (SFIL-RO) and pseudo-random injection locked technique (PRILT) are presented. SFIL-RO, of which the oscillation signal is feedback to the input of the pulse generator to generate injection pulse, is proposed to achieve inherently aligned injection timing to decrease the injection spur. Meanwhile, it avoids the risk of suffering from pseudo-locking phenomenon, enhancing the immunity to the PVT variation. The periodicity of conventional injection behavior is broken in proposed PRILT, which essentially reduces the spur. The actual output of the IL-PLL with PRILT is the pseudo-random edge combination of two SFIL-ROs. Thus, the equivalent injection pulse is aperiodic. Calibration circuit is included to cope with the mismatch between two SFIL-ROs. To demonstrate the effectiveness of the proposed SFIL-RO and PRILT on optimizing spur, an IL-PLL was fabricated in SMIC 180 nm CMOS process. Measurement results show the best spur of −67.2 dBc and the RMS jitter of 124 fs are achieved when SFIL-RO and PRILT are activated. The core area was 0.142 mm2 and the power consumption is 6.1 mW from 1.8 V supply voltage.

A 1.0 V, 5.4 pJ/bit GFSK Demodulator Based on an Injection Locked Ring Oscillator for Low-IF Receivers

This paper presents an ultra-low power, low cost demodulator for gaussian frequency shift keying (GFSK) receivers that use low intermediate frequencies (IF). The demodulator employs a direct IF to digital data conversion scheme by using an injection-locked ring oscillator (ILRO) with a 1-bit flip-flop. It consumes $2.7~\mu \text{W}$ from a 1.0 V supply at a data rate of 500 kbps achieving an energy efficiency of 5.4 pJ/bit which is 30 times better than that of the recently presented works. The demodulator also achieves 17.5 dB SNR at 0.1 % BER while operating at the same date rate. The demodulator is implemented in a $0.18~\mu \text{m}$ standard CMOS process and occupies an active area of 0.012 mm2.

A 12 Gb/s 1.59 mW/Gb/s Input-Data-Jitter-Tolerant Injection-Type CDR With Super-Harmonic Injection-Locking in 65-nm CMOS

This brief presents an input-data-jitter-tolerant injection-type clock and data recovery (CDR) circuit with a super-harmonic injection-locked ring oscillator (SH-ILRO). Unlike prior injection-type CDRs that utilize a power-hungry CML-type data injection path or for which the data rate is limited to the process-defined CMOS logic bandwidth, the proposed injection-type CDR achieves energy-efficient data edge injection. The proposed wide-bandwidth source follower-based edge detector extracts the input data edge energy efficiently. The proposed SH-ILRO enables quarter-rate injection-locking without high-speed injection selection logic. Fabricated in 65-nm CMOS, the prototype injection-type CDR consumes 19.08 mW at 12 Gb/s with 87-MHz jitter transfer bandwidth and more than 1.0 UIpp jitter tolerance at 20 MHz.

A 39-GHz Frequency Tripler With &gt;40-dBc Harmonic Rejection for 5G Communication Systems in 28-nm Bulk CMOS

The generation of the carrier signal with a very low spur level is a key challenge in all the communication systems, especially those operating at mm-waves, where a frequency multiplier is typically used to break the tradeoff between high frequency of operation and low phase noise. This letter describes a frequency tripler tailored to cover the fifth generation new radio 39-GHz frequency range. By embracing the edge-combining concept, together with the combination of a single-stage polyphase filter and a multipoint injection-locked ring oscillator, the proposed frequency multiplier is able to offer robust and consistent high harmonic rejection ratio over a large fractional bandwidth. Fabricated in 28-nm bulk CMOS technology, the measured frequency multiplier features >40-dBc harmonic rejection over an outstanding 35% fractional bandwidth, while consuming 25 mW only from 0.9-V supply. To the best of our knowledge, the proposed multiplier achieves the highest harmonic rejection among the state-of-the-art multipliers in CMOS and BiCMOS technologies, while having 60% smaller area.

A General Theory of Injection Locking and Pulling in Electrical Oscillators—Part II: Amplitude Modulation in $LC$ Oscillators, Transient Behavior, and Frequency Division

A number of specialized topics within the theory of injection locking and pulling are addressed. The material builds on our impulse sensitivity function (ISF)-based, time-synchronous model of electrical oscillators under the influence of a periodic injection. First, we show how the accuracy of this model for $LC$ oscillators under large injection is greatly enhanced by accounting for the injection’s effect on the oscillation amplitude. In doing so, we capture the asymmetry of the lock range as well as the distinct behaviors exhibited by different $LC$ oscillator topologies. Existing $LC$ oscillator injection locking and pulling theories in the literature are subsumed as special cases. Next, a transient analysis of the dynamics of injection pulling is carried out, both within and outside of the lock range. Finally, we show how our existing framework naturally accommodates locking onto superharmonic and subharmonic injections, leading to several design considerations for injection-locked frequency dividers (ILFDs) and the implementation of a low-power dual-modulus prescaler from an injection-locked ring oscillator. Our theoretical conclusions are supported by simulations and experimental data from a variety of $LC$ , ring, and relaxation oscillators.

VCO-Based ADC With Built-In Supply Noise Immunity Using Injection-Locked Ring Oscillators

Analog-to-digital converters (ADCs) based on voltage-controlled oscillators (VCOs) demonstrate superior hardware efficiency. They benefit from the technology scaling; however, they exhibit inferior performance against supply noise. The objective of this brief is, therefore, to present a VCO-based ADC architecture with built-in immunity against supply noise. The proposed technique exploits the dynamics of injection locking oscillation in multiphase ring topology. It provides a system-level cancelling of power supply noise, independent of the VCO architecture used in the time-mode ADC. The design functionality has been demonstrated using behavioral and transistor-level simulations using 65 nm technology. Under a 10% mismatch of VCO gain and a 128 MS/s data rate, the reported power supply noise rejection improvement is 25 dB, as compared with a typical VCO-based ADC.

A Low-Noise Digital-to-Frequency Converter Based on Injection-Locked Ring Oscillator and Rotated Phase Selection for Fractional-$N$ Frequency Synthesis

This paper proposes a low-noise digital-to-frequency converter (DFC) for fractional- $N$ frequency synthesis. The DFC first employs a subharmonic injection-locked ring oscillator (ILRO) to generate low phase noise, high-frequency fixed reference from a crystal oscillator (XO). $\Delta \Sigma $ modulator ( $\Delta \Sigma \text{M}$ ) and accumulator are then applied to perform phase randomization and rotation around the multiphase outputs of the ILRO. This modulates the output frequency, while the rotation ensuring the range and linearity of the DFC. Meanwhile, clocking the $\Delta \Sigma \text{M}$ at high frequency greatly suppresses the quantization noise, enabling a wide loop bandwidth for the subsequent phase-locked loop stage. Implemented in UMC CMOS 65-nm technology, the proposed DFC occupies an area of 0.257 mm2, and is capable of generating frequencies from 390 to 640 MHz with resolution finer than 0.3 kHz. The in-band phase noise is lower than −120 dBc/Hz at 100 kHz, tracking well with the noise performance of the XO. The shaped high-frequency quantization noise only appears beyond 20-MHz frequency offset.

Time of arrival measurement for indoor distance monitoring in 130-nm CMOS

A new architecture for Vernier-based frequency-to-voltage/digital converter (VFVDC) is proposed for time difference of arrival (TDOA) measurement using a frequency domain approach. The VFVDC is employed for indoor distance monitoring using an RFID front end. The proposed architecture employs an injection-locked ring oscillator (ILR) as the clock source. The proposed ILR oscillator does not need the complex calibration procedures, usually required by Phase Locked Loop (PLL) based oscillators in Vernier-based time-to-digital converters. The oscillator consumes 14.4 μW and 1.15 mW from 0.4 V and 1.2 V supplies. The total power consumption of the entire chip is only 0.65 mW and 7.6 mW from 0.4 V and 1.2 V supplies while operating at 1.615 MHz and 22.55 MHz, respectively. The design was implemented in 130-nm CMOS process and has a core area of 0.1 mm2, one of the lowest in reported literature. The proposed VFVDC is reconfigurable and achieves a large detectable range of 1–300 mm, with a fine distance resolution of 3 mm/kHz in a small die size while consuming low power with FoM of 5.78 fA-s/m.

A Low Noise Sub-Gigahertz Fractional-N Frequency Generator with Cascaded FIR

This paper proposes a low sub-gigahertz frequency generator with fine frequency resolution. An injection-locked ring oscillator (ILRO) is firstly adopted to obtain multiphase output at integer multiple times crystal oscillator (XO) frequency. Following that, a multiplexer (MUX) selects the output phase according to the output of a delta-sigma modulator ([Formula: see text]M) to achieve high frequency, low in-band noise fractional output. A hybrid type finite impulse response (FIR) filter, which is composed of some MUXs, flip-flops (FFs), digitally-controlled delay units (DCDUs), and a linear multiphase combiner (MPC), is employed in cascading to suppress the quantization noise (Q-noise) at high-frequency offset. An auto-calibration scheme for calibrating the DCDU’s delay has been proposed as well. Simulated in 65[Formula: see text]nm CMOS, the proposed fractional-N frequency generator exhibits a phase noise performance that is well below [Formula: see text]118[Formula: see text]dBc/Hz from 100[Formula: see text]kHz to 100[Formula: see text]MHz offset. The simulation also shows that the power consumption and die area is 10.6[Formula: see text]mW and 0.3[Formula: see text]mm2, respectively, with the FIR filter consuming 4.3[Formula: see text]mW and 0.041[Formula: see text]mm2.

Analysis and design of two-stage ring oscillators with dual-input injection at millimeter waves

In this paper, a new analytic approach is proposed for injection-locked ring oscillators (ILROs) design at millimeter waves (mm-waves). Using time and transfer constants (TTC) analysis, a two-pole model of the delay stage is applied into the injection-locking behavior model for an N-stage ring oscillator, and analytic expressions of the self-resonance frequency (SOF) and the locking range are derived. These expressions are concise and based solely on device-level circuit parameters, enabling fast and exact ILRO design through DC and AC simulations. In addition, a dual-input injection technique is investigated and a layout optimization technique is presented. Using a 0.13-μm SiGe BiCMOS process, a two-stage ring oscillator with dual-input injection is implemented for verification. The fabricated divider achieves a wide locking range from 16 to 67 GHz at −10-dBm input power. The divider core consumes a current of 3.9 mA from 3.3 V supply with an area of 45 × 60 μm2. The measured results agree well with theoretical analyses and simulated results.

Ultra‐low power frequency‐shift keying demodulator based on injection‐locking ring oscillator without using phase locked loop for wireless body area networks

An ultra-low power frequency-shift keying (FSK) demodulator based on injection-locking ring oscillator for wireless body area networks is presented. The proposed system uses the power-efficient injection-locking ring oscillator (ILRO) to replace the LC oscillator which occupies much more area on chip with higher power consumption. In addition, through the ILRO, the frequency modulated input signal is converted to a full swing rectangular signal, which can be directly demodulated by a chain of down-conversion passive mixers, lowpass filters and a comparator. Power efficiency and simplicity of the proposed structure eliminate conventional FSK demodulator based on power-hungry phase locked loops, which needs to be calibrated by auto-frequency calibrator to periodically compensate the free running frequency deviations due to temperature variations and charge pump leakage current. The proposed FSK demodulator is designed and simulated in 180 nm CMOS technology while consuming only 23.37 µW from a 0.7 V supply.

A 2–11 GHz 7-Bit High-Linearity Phase Rotator Based on Wideband Injection-Locking Multi-Phase Generation for High-Speed Serial Links in 28-nm CMOS FDSOI

Pushed by the ever-increasing demand of internet traffic, high-speed serial interfaces are expected to reach 400-Gb/s aggregate data rates in near future. At receiver (RX) side, phase rotators (PRs) are key blocks to align the phase of the local clock to the transitions of the incoming data and to sample the eye in the optimal position. Small phase step and high linearity are paramount in preserving the horizontal time margin, tightened by the reduced symbol duration at 25 Gb/s and beyond. Interpolation of $\pi $ /4-spaced signals is a viable means of improving linearity at high resolution, provided multi-phase signals with low phase error are available. An injection-locked ring oscillator (ILRO) with a mixed analog and digital calibration loop is proposed for high accuracy multi-phase generation over a wide frequency range and against large voltage and temperature variations. A phase detector (PD) based on two passive mixers measures the quadrature error and continuously tunes the oscillator to achieve low phase error. Concurrently, a window comparator monitors the PD output and drives digital coarse calibration in background. Two test chips have been fabricated in 28-nm CMOS fully depleted silicon on insulator technology. The stand-alone ILRO demonstrates 0.2–11.7 GHz frequency range with better than 1.5° quadrature phase error over ±20% supply and −40 °C to +120 °C temperature variations. Power consumption is scalable from 3 to 15 mW. When the ILRO drives the 7-bit PR, it demonstrates differential and integral non-linearity within 0.5 and 1.1 LSB, respectively, across the 2–11 GHz frequency range with 18.6-mW maximum power dissipation. Measured performances compare favorably against the state of the art and meet the requirements of >25 Gb/s multi-standard I/O RXs.

A 370-pJ/b Multichannel BFSK/QPSK Transmitter Using Injection-Locked Fractional-N Synthesizer for Wireless Biotelemetry Devices

This paper presents a 401-428-MHz BFSK/QPSK transmitter (TX) with two types of fractional-injection-locking techniques for multichannel transmission capabilities. A ΔΣbased injection-locked ring oscillator is proposed to achieve fine frequency tuning with a frequency resolution of 1.3 kHz. The proposed method facilitates multichannel BFSK modulation. For high data rate wideband QPSK modulation, frequency tuning is achieved through sequential injection locking. The TX performs 550 Kb/s for BFSK and 11 Mb/s for band-shaped QPSK with EVM of 4.4% and 4.9%, respectively. It also achieves a settling time of less than 0.8 μs. This helps to save operating power of the wireless medical devices with duty-cycling protocol employed in the TX. Fabricated in 130-nm process technology, the TX achieves an energy efficiency of 370 pJ/b while delivering -13 dBm of output power with 1-V supply.

1–2 GHz 2 mW injection‐locked ring oscillator based phase shifter in 0.18 µm CMOS technology

A new phase shifter based on injection-locked ring oscillator is proposed. By using a multi-stage phase generator with voltage-controlled injection locking technique, the proposed phase shifter is able to generate a flexible combination of coarse and fine-tuned phase delays over a wide range of operating frequencies while a small silicon area is maintained. Fabricated in a 0.18 µm RF CMOS process which only occupies 50 × 40 µm, a proposed three-stage phase shifter achieves flexible phase delays and a measured operating frequency up to 2 GHz with a maximum power consumption of 2 mW from a 1.8 V supply.

A Wideband Injection Locked Quadrature Clock Generation and Distribution Technique for an Energy-Proportional 16–32 Gb/s Optical Receiver in 28 nm FDSOI CMOS

We present a novel frequency tracking method that exploits the dynamics of injection locking in a quadrature ring oscillator to increase the effective locking range from 5% (7–7.4 GHz) to 90% (4–11 GHz). The quadrature phase error between I and Q phases of an injection locked ring oscillator is derived and shown to contain frequency error information, both inside and outside the locking range. This error is utilized to form a first-order frequency tracking quadrature locked loop (QLL). This loop generates accurate clock phases for a 4-channel parallel optical receiver using a forwarded clock at quarter-rate. The QLL drives an ILO at each channel without any repeaters for local quadrature clock generation. Each local ILO has deskew capability for phase alignment. The receiver maintains a constant energy-per-bit consumption across 16–32 Gb/s by adaptive body biasing in a 28 nm FDSOI technology.