Individual Processors Research Articles

Large-Eddy Simulation of Supersonic Cavity Flowfields Including Flow Control

Large-eddy simulations of supersonic cavity flowfields are performed using a high-order numerical method. Spatial derivatives are represented by a fourth-order compact approximation that is used in conjunction with a sixth-order nondispersive filter. The scheme employs a time-implicit approximately factored finite difference algorithm, and applies Newton-like subiterations to achieve second-order temporal and fourth-order spatial accuracy. The Smagorinsky dynamic subgrid-scale model is incorporated in the simulations to account for the spatially underresolved stresses. Computations at a freestream Mach number of 1.19 are carried out for a rectangular cavity having a length-to-depth ratio of 5:1. The computational domain is described by 2.06×10 7 grid points and has been partitioned into 254 zones, which were distributed on individual processors of a massively parallel computing platform. Active flow control is applied through pulsed mass injection at a very high frequency, thereby suppressing resonant acoustic oscillatory modes

Next generation computing challenges for pre-stack depth migration and reservoir simulation

Bill Bartling, senior director, energy and sciences, Silicon Graphics provides an analysis of the shortcomings of today’s computer systems and discusses where the future lies for computer-intensive operations in the E&P business. Oil and gas computational challenges, especially in seismic processing and reservoir simulation, have consistently outstripped the capabilities of even the most powerful computers. Continuing that trend, these same computational problems are now growing at a rate faster than Moore’s Doubling Law. In truth, the very large problems we are trying to solve today have always been around. Adapting to our surroundings, we have scaled them back to match the limited abilities of our machines hoping that engineering breakthroughs would eventually compensate for those limitations. Many breakthroughs have indeed come to pass, especially in microprocessor speed, power, pricing and form factor. But these revolutions exposed new limitations that in many cases cancelled out some or all of the benefits. Scientists and engineers have rushed to consume the promises of blazing fast gigahertz CPUs at highly competitive prices, only to find that I/O, bus speed, storage systems and code design prevented them from realizing their full potential. Idle cycles became the theme of the day. The goal in working with the complexity of seismic and reservoir simulation data, is throughput: speed is merely a way to get there. The concept of using speed to deliver breakthrough throughput, and thus to deliver significantly faster computational times for much larger data models, continues to drive research both in computer and software design. The answer must lie in balanced systems, with each component optimized to do its part in delivering the revolution. The past few years have ushered in a new computational paradigm: the cluster. This model is based on one of the most tantalizing promises of the Internet – a globally inter-connected computational grid of inexpensive systems that, together, can potentially combine to create the most powerful supercomputer ever built. The SETI Grid (http://setiathome. ssl.berkeley.edu/) is an excellent example of such a system, but, of course, with inter-connects running at 28.8kb/sec in too many places, SETI@home highlights the importance of appropriate and adequate back plane bandwidth. At the other end of the spectrum are supercomputers, which, in truth, are highly compact computational grids with extraordinarily fast interconnects. In spite of their slower clock speed microprocessors, from their introduction they outran the fastest PCs due to efficient, stable and proven parallel operating systems and related optimizations that focused on the throughput of many joined processors, not just individual processor speed. Of course, the price point that comes with this sort of machine, while once easily justified, has come under increasing scrutiny from data processors, IT executives and P/L managers. Key components to the success of supercomputers, in addition to their interconnect speeds, have been effective I/O and data delivery systems to keep the processors fed and working, the lack of which has been a striking shortcoming of PC architectures applied to computationally intensive tasks. Direct attached storage with fibre-channel connections has been the preferred solution to keep the data flowing to processors. New storage and delivery systems crush that paradigm, offering breakthroughs in data delivery via Storage Area Networks.

Parallel computing with load balancing on heterogeneous distributed systems

In the present work, the parallelization of the solution of a system of linear equations, in the framework of finite element computational analyses, is dealt with. As the substructuring method is used, the basic idea refers to a way of decomposing the considered spatial domain, discretized by the finite elements, into a finite set of non-overlapping subdomains, each assigned to an individual processor and computationally analysed in parallel. Considering the fact that Personal Computers and Work Stations are still the most frequently used computers, a parallel computational platform can be built by connecting the available computers into a computer network. The incorporated computers being usually of different computational power and memory size, the efficiency of parallel computations on such a heterogeneous distributed system depends mainly on proper load balance. To cope the balance problem, an algorithm for the efficient load balance for structured and free 2D quadrilateral finite element meshes based on the rearrangement of elements among respective sub-domains, has been developed.

Transparent recovery from intermittent faults in time-triggered distributed systems

The time-triggered model, with tasks scheduled in static (off line) fashion, provides a high degree of timing predictability in safety-critical distributed systems. Such systems must also tolerate transient and intermittent failures which occur far more frequently than permanent ones. Software-based recovery methods using temporal redundancy, such as task reexecution and primary/backup, while incurring performance overhead, are cost-effective methods of handling these failures. We present a constructive approach to integrating runtime recovery policies in a time-triggered distributed system. Furthermore, the method provides transparent failure recovery in that a processor recovering from task failures does not disrupt the operation of other processors. Given a general task graph with precedence and timing constraints and a specific fault model, the proposed method constructs the corresponding fault-tolerant (FT) schedule with sufficient slack to accommodate recovery. We introduce the cluster-based failure recovery concept which determines the best placement of slack within the FT schedule so as to minimize the resulting time overhead. Contingency schedules, also generated offline, revise this FT schedule to mask task failures on individual processors while preserving precedence and timing constraints. We present simulation results which show that, for small-scale embedded systems having task graphs of moderate complexity, the proposed approach generates FT schedules which incur about 30-40 percent performance overhead when compared to corresponding non-fault-tolerant ones.

Communication Delay in Wormhole-Switched Tori Networks under Bursty Workloads

Workloads generated by the real-world parallel applications that are executed on a multicomputer have a strong effect on the performance of its interconnection network—the hardware fabric supporting communication among individual processors. Existing multicomputer networks have been primarily designed and analysed under the assumption that the workload follows the non-bursty Poisson arrival process. As a step towards obtaining a clear understanding of network performance under various workloads, this paper presents a new analytical model for computing message latency in wormhole switched torus networks in the presence of bursty traffic, based on the well-known Markov-Modulated Poisson Process (MMPP). In order to derive the model, the approach for accurately capturing the properties of the composite MMPPs is applied to characterize traffic on network channels. Moreover, a general method has been proposed for calculating the probability of virtual channel occupancy when the traffic on network channels follows a multi-state MMPP process. Simulation experiments reveal that the model exhibits a good degree of accuracy.

Parallelizing the Data Cube

This paper presents a general methodology for the efficient parallelization of existing data cube construction algorithms. We describe two different partitioning strategies, one for top-down and one for bottom-up cube algorithms. Both partitioning strategies assign subcubes to individual processors in such a way that the loads assigned to the processors are balanced. Our methods reduce inter processor communication overhead by partitioning the load in advance instead of computing each individual group-by in parallel. Our partitioning strategies create a small number of coarse tasks. This allows for sharing of prefixes and sort orders between different group-by computations. Our methods enable code reuse by permitting the use of existing sequential (external memory) data cube algorithms for the subcube computations on each processor. This supports the transfer of optimized sequential data cube code to a parallel setting. The bottom-up partitioning strategy balances the number of single attribute external memory sorts made by each processor. The top-down strategy partitions a weighted tree in which weights reflect algorithm specific cost measures like estimated group-by sizes. Both partitioning approaches can be implemented on any shared disk type parallel machine composed of p processors connected via an interconnection fabric and with access to a shared parallel disk array. We have implemented our parallel top-down data cube construction method in C++ with the MPI message passing library for communication and the LEDA library for the required graph algorithms. We tested our code on an eight processor cluster, using a variety of different data sets with a range of sizes, dimensions, density, and skew. Comparison tests were performed on a SunFire 6800. The tests show that our partitioning strategies generate a close to optimal load balance between processors. The actual run times observed show an optimal speedup of p.

Combining Shared and Distributed Memory Programming Models on Clusters of Symmetric Multiprocessors: Some Basic Promising Experiments

This note presents some experiments on different clusters of SMPs, where both distributed and shared memory parallel programming paradigms can be naturally combined. Although the platforms exhibit the same macroscopic memory organization, it appears that their individual overall performance is closely dependent on the ability of their hardware to efficiently exploit the local shared memory within the nodes. In that context, cache blocking strategy appears to be very important not only to get good performance out of each individual processor but mainly good performance out of the overall computing node since sharing memory locally might become a severe bottleneck. On a very simple benchmark, representative of many large simulation codes, we show through numerical experiments that mixing the two programming models enables us to get attractive speed-ups that compete with a pure distributed memory approach. This opens promising perspectives for smoothly moving large industrial codes developed on distributed vector computers with a moderate number of processors on these emerging platforms for intensive scientific computing that are the clusters of SMPs.

Food safety and assurance: the role of information technology

The dairy industry is under pressure to improve product security, implement efficient risk management and rapid response capabilities, and manage quality ‘from trough to table’ to achieve full, verifiable traceability. In order to invest proactively in the future of the industry, individual processors must reassess their handling of quality and traceability data for strategic and competitive success, make appropriate physical configuration and operational adjustments, and deploy readily available technological tools to meet legislative and consumer demands, enhance product quality and increase operational efficiency and profits.

Parallel Computing Adaptive Simulated Annealing Scheme for Fuel Assembly Loading Pattern Optimization in PWRs

An adaptive control scheme of simulated annealing (SA) parameters derived from the polynomial-time cooling schedule is presented in terms of the efficiency enhancement of the SA algorithm. The parallel computing adaptive SA optimization scheme, which incorporates the optimization-layer-by-layer (OLL) neutronics evaluation model is then applied to determining the optimum fuel assembly (FA) loading pattern (LP) in the Korea Nuclear Unit 2 pressurized water reactor (PWR) using seven Pentium personal computers (three 266-MHz Pentium II and four 200-MHz Pentium Pro computers). It is shown that the parallel scheme enhances the efficiency of the SA optimization computation significantly but that it can get trapped in local optimum LPs more frequently than the single-processor SA scheme unless one takes preventive steps. As a way to prevent trapping of the parallel scheme in local optima, using multiple seed LPs is proposed instead of a single LP with which the individual processors start each stage, and how to determine the multiple seed LPs is discussed. Because of the high efficiency of the parallel scheme, the acceptability of a hybrid neutronics evaluation model, which is slower but more accurate than the OLL model, in the parallel optimization calculation is examined from the standpoint of computing time. By demonstrating that the FA LP optimization calculation for the equilibrium cycle core of the KNU-2 PWR can be completed in <1 h on seven Pentiums, we justify the routine utilization of the hybrid model in the parallel SA optimization scheme.

Local versus global lookahead in conservative parallel simulations

This paper presents an algorithm, which we refer to as SGTNE, to efficiently obtain lookahead information from a cluster of processors in a parallel simulation in order to unblock (logical) processes (LP) in a given processor. The SGTNE algorithm is based on a TNE conservative synchronization scheme that relies on an independent execution of a shortest path algorithm in individual processors in order to provide lookahead to the resident LPs. Because TNE is executed on individual processors, it is susceptible to inter-processor deadlocks, which must be detected and broken at some cost. SGTNE (Semi-Global TNE) avoids these deadlocks by executing a shortest path algorithm over a snapshot of the LPs in a cluster of processors. An experimental study of SGTNE was conducted on an Intel Paragon A4. The study compared SGTNE to TNE and to an optimized version of Chandy–Misra (CM) null message algorithms. We also investigated several scheduling algorithms for SGTNE and determined factors influencing its performance, most notably the influence of partitioning. Our results indicate that SGTNE provides good speedup relative to the fastest sequential algorithm and that it out-performs TNE for the population level examined, SGTNE was 3–5 times as fast as the CM-algorithm.

Designing Enterprise Client/Server Systems

B. Gold-Bernstein and D. Marca Prentice Hall, Upper Saddle River, NJ, 1998, 360 pp. ISBN 0-13-890195-3, $45.00 Client/servers systems represent the vast majority of enterprise software. Yet over 80% of these projects fail. This book presents a concrete design method that provides for reliable design and implementation of multi-tier client/server systems. This book is organized into five basic parts: Context for Understanding Distributed Client/Server Systems Business Components—The Essential Model Software Components—The Implementation Model Organizational Enablers Case Study In Part 1, Chapter 1 answers the question: Why build client/server systems? by giving a general context roadmap, discussing why businesses are under pressure to change, how legacy systems inhibit change, why client/server systems enable change. What is new and not new in client/server systems, and the importance of good design and modeling are also presented. Chapter 2 discusses all aspects of models and modeling in general, including a definition of the basic structure of a model. Chapter 3 presents the Illumisys Design Method, a specific event- and object-based method for developing distributed client/server systems. In Part 2, the first stage of the Illumisys Design Method, the business requirements, are covered. Chapter 4 provides an overview on a rigorous and formal model for business requirements, termed the Essential Model. Chapter 5 discusses the Environmental Aspect—how a system interacts with the outside world and how boundaries are defined. The organization of the rules which drive the business are encompassed in the Information Aspect and are discussed in Chapter 6. This chapter is careful to note the differences between the Information Aspect and a Database Model. Chapter 7 describes the Bridge Aspect, which is a consistency component that insures that the Environmental Aspect and the Information Aspect are describing a single system. The Behavioral Aspect, as described in Chapter 8, brings together further all previously defined aspects and provides detailed descriptions of responses to specific events. Chapter 9 discusses the Event Distribution Aspect, which describes the geographical distribution of the business events—where business events actually occur. However, there are additional factors that can affect system partitioning, such as performance goals and processing volumes. Chapter 10 describes the Component Measurement Aspect, which encapsulates the natural rhythms and cycles of the business. In Part 3, the design of the distributed architecture implementation is described. Chapter 11 presents an overview of the Implementation Model, which maps the business events and responses defined in the Essential Model to the distributed architecture. A Statement of Design Metrics, which determines design tradeoffs and is used to partition the essential requirements across the distributed processor architecture, is discussed in Chapter 12. The Multi-Tier Partitioning Aspect is described in Chapter 13. Multi-tier partitioning enables: data encapsulation, granular business rules, component application architecture, and scalability. Selecting the appropriate technology, such as processors and tools, is a critical aspect of distributed architecture design. Chapter 14 defines five steps of the Technical Architecture Design that is appropriate for enterprise architecture planning. The Processor Distribution Aspect, as described in Chapter 15, provides the specifications of the software granules that will operate on each processor, and these specifications are used to build the software components. Having defined the processing and data distribution design, Chapter 16 describes the Geographical Distribution Aspect, which maps processors to geographical location. Chapter 17 defines Traffic Analysis, which measures the message traffic between processors as well as the contention on individual processors. In Part 4, an overall plan to enable change to the system is described. Organizational enablers are used and include: organizational architecture, process management, and organizational transformation. Chapter 18 describes an Organizational Architecture that easily adapts to changes in the business environment. Designing client/server systems requires a strategy for identifying and managing concurrent activities. Process Management, as described in Chapter 19, synchronizes all concurrent activities and ensures that the system delivers the required functionality. The last aspect of the Organizational enablers deals with the transformation required by business. Chapter 20 deals with Organizational Transformation—a process required to enable business change. In Part 5, all of the models are brought together to show, from beginning to end, how the Illumisys Design Method is applied to a specific business situation. This is accomplished via a case study (Fleury Market). Chapter 21 provides necessary background for the case study. Chapters 22 and 23 contain, respectively, all components for the Essential Model and the Implementation Model for the case study. Overall, the book is well written and easy to understand. This book would be an important addition for anyone interested in designing and implementing a client/server system in a business environment. This book would also be appropriate for an advanced database or special topics course. James P. Buckley Department of Computer Science University of Dayton

Letter to the Editor: NEUROCOMPUTERS: A DEAD END?

The last decade saw a proliferation of research into the design of neurocomputers. Although such work still continues, much of it is never beyond the prototype-machine stage. In this paper, we argue that, on the whole, neurocomputers are no longer viable; like, say, database computers before them, their time has passed before they became a common reality. We consider the implementation of hardware neural networks, from the level of arithmetic to complete individual processors and parallel processors and show that currents trends in computer architecture and implementation are not supportive of a case for custom neurocomputers. We argue that in the future, neural-network processing ought to be mostly restricted to general-purpose processors or to processors that have been designed for other widely-used applications. There are just one or two, rather narrow, exceptions to this.

Automated tuning of parallel I/O systems: an approach to portable I/O performance for scientific applications

Parallel I/O systems typically consist of individual processors, communication networks, and a large number of disks. Managing and utilizing these resources to meet performance, portability, and usability goals of high performance scientific applications has become a significant challenge. For scientists, the problem is exacerbated by the need to retune the I/O portion of their code for each supercomputer platform where they obtain access. We believe that a parallel I/O system that automatically selects efficient I/O plans for user applications is a solution to this problem. The authors present such an approach for scientific applications performing collective I/O requests on multidimensional arrays. Under our approach, an optimization engine in a parallel I/O system selects high quality I/O plans without human intervention, based on a description of the application I/O requests and the system configuration. To validate our hypothesis, we have built an optimizer that uses rule based and randomized search based algorithms to tune parameter settings in Panda, a parallel I/O library for multidimensional arrays. Our performance results obtained from an IBM SP using an out-of-core matrix multiplication application show that the Panda optimizer is able to select high quality I/O plans and deliver high performance under a variety of system configurations with a small total optimization overhead.

Point-centered domain decomposition for parallel molecular dynamics simulation

A new algorithm for molecular dynamics simulations of biological macromolecules on parallel computers, point-centered domain decomposition, is introduced. The molecular system is divided into clusters that are assigned to individual processors. Each cluster is characterized by a center point and comprises all atoms that are closer to its center point than to the center point of any other cluster. The point-centered domain decomposition algorithm is implemented in the new program Opalp using a standard message passing library, so that it runs on both shared memory and massively parallel distributed memory computers. Benchmarks show that the program makes efficient use of up to 100 and more processors for realistic systems of a protein in water comprising 10000 to 20000 atoms.

Analysis of convergence of parallelized pfi for coupled large-scale nonlinear systems

Analysis of convergence of parallelized PFI (Perturbed Functional Iteration) for coupled large-scale nonlinear systems has been studied in this article. It has been found that with regard to each individual parallel processor, the rate of convergence is quadratic. However, when we view the synchronism with regard to all processors, then quadratic convergence is reduced to a linear rate of convergence mathematically.

Linear QR Architecture for a Single Chip Adaptive Beamformer

This paper presents the design of a novel single chip adaptive beamformer capable of performing 50 Gflops, (Giga-floating-point operations/second). The core processor is a QR array implemented on a fully efficient linear systolic architecture, derived using a mapping that allows individual processors for boundary and internal cell operations. In addition, the paper highlights a number of rapid design techniques that have been used to realise this system. These include an architecture synthesis tool for quickly developing the circuit architecture and the utilisation of a library of parameterisable silicon intellectual property (IP) cores, to rapidly develop detailed silicon designs.

A New Paradigm for Parallel Adaptive Meshing Algorithms

We present a new approach to the use of parallel computers with adaptive finite element methods. This approach addresses the load balancing problem in a new way, requiring far less communication than current approaches. It also allows existing sequential adaptive PDE codes such as PLTMG and MC to run in a parallel environment without a large investment in recoding. In this new approach, the load balancing problem is reduced to the numerical solution of a small elliptic problem on a single processor, using a sequential adaptive solver, without requiring any modifications to the sequential solver. The small elliptic problem is used to produce a posteriori error estimates to predict future element densities in the mesh, which are then used in a weighted recursive spectral bisection of the initial mesh. The bulk of the calculation then takes place independently on each processor, with no communication, using possibly the same sequential adaptive solver. Each processor adapts its region of the mesh independently, and a nearly load-balanced mesh distribution is usually obtained as a result of the initial weighted spectral bisection. Only the initial fan-out of the mesh decomposition to the processors requires communication. Two additional steps requiring boundary exchange communication may be employed after the individual processors reach an adapted solution, namely, the construction of a global conforming mesh from the independent subproblems, followed by a final smoothing phase using the subdomain solutions as an initial guess. We present a series of convincing numerical experiments which illustrate the effectiveness of this approach. The justification of the initial refinement prediction step, as well as the justification of skipping the two communication-intensive steps, is supported by some recent [J. Xu and A. Zhou, Math. Comp., to appear] and not so recent [J. A. Nitsche and A. H. Schatz, Math. Comp., 28 (1974), pp. 937--958; A. H. Schatz and L. B. Wahlbin, Math. Comp., 31 (1977), pp. 414--442; A. H. Schatz and L. B. Wahlbin, Math. Comp., 64 (1995), pp. 907--928] results on local a priori and a posteriori error estimation.

Using knowledge to optimally achieve coordination in distributed systems

A distributed computing system consists of a set of individual processors that communicate through some medium. Coordinating the actions of such processors is essential in distributed computing. Researchers have long endeavored to find efficient solutions to a variety of coordination problems. Recently, processor knowledge has been used to characterize such solutions and to derive more efficient ones. Most of this work has concentrated on the relationship between common knowledge and simultaneous coordination. This paper considers non-simultaneous coordination problems. The results of this paper add to our understanding of the relationship between knowledge and the different requirements of coordination problems. This paper considers the ideas of optimal and optimum solutions to a coordination problem and precisely characterizes the problems for which optimum solutions exist. This characterization is based on combinations of eventual common knowledge and continual common knowledge. The paper then considers more general problems, for which optimal, but no optimum, solutions exist. It defines a new form of knowledge, called extended knowledge, which combines eventual and continual knowledge, and shows how extended knowledge can be used to both characterize and construct optimal protocols for coordination.

Processor array design with FPGA area constraint

Digital signal processing algorithms with multiple shift-invariant dependence graphs (DGs) can be mapped to field programmable gate array hardware in many different types of systolic processor arrays. Because of the finite amount of hardware resources, the problem is to use a "right" amount of hardware in a specific configuration so to maximize the processing speed. In this paper, the problem of finding the right processor array configuration is formulated as a constrained optimization problem where the cost function includes not only the cost of individual processor arrays but also the cost of interfacing circuits. Three heuristic algorithms are presented for the optimization problem. Among them, both the Lth axial neighbor algorithm and the simulated annealing algorithm produce good results on a test case. Simulation results on the test case also indicate that the initial configuration is important in getting a good configuration for both algorithms. The Lth axial neighbor algorithm has the extra advantage of requiring less amount of performance tuning.

Optimisation of irregular multiprocessor computer architectures using genetic algorithms

Many problems today need the computing power that is only available by using large‐scaleparallel processing. For a significant number of these problems, the density of theglobal communications between the individual processors dominates the performance ofthe whole parallel implementation on a distributed memory multiprocessor system. In thesecases, the design of the interconnection network for the processors is known to play asignificant part in the efficient implementation of real problems. Important criteria to optimisethe efficiency of a configuration are the maximum and average distance a message hasto travel between processors. Minimum path systems are irregular multiprocessor computerarchitectures which optimise these criteria. These architectures provide an efficient alternativeto the more common regular topologies for solving real applications in parallel. Thispaper presents new results for two combinatorial problems that occur during the generationof these optimal irregular configurations. These are: (1) The design of the optimum interconnection network between the processors for configurationscontaining up to 128 processors. (2) The design of the routing tables to provide the optimal routing of messages withinthese irregular networks. The paper shows how these combinatorial problems have been solved, using genetic algorithmsfor the first problem and a random local search procedure for the second. It alsoincludes a comparison with the results obtained for regular topologies, for example: hypercubes,tori, and rings.