Indium Zinc Oxide Channel Research Articles

Proton-Gated Synaptic Transistors, Based on an Electron-Beam Patterned Nafion Electrolyte.

Neuromorphic processors using artificial neural networks are the center of attention for energy-efficient analog computing. Artificial synapses act as building blocks in such neural networks for parallel information processing and data storage. Herein we describe the fabrication of a proton-gated synaptic transistor using a Nafion electrolyte thin film, which is patterned by electron-beam lithography (EBL). The device has an active channel of indium-zinc-oxide (IZO) between the source and drain electrodes, which shows Ohmic behavior with a conductance level on the order of 100 μS. Under voltage applications to the gate electrode, the channel conductance is changed due to the injection and extraction of protons between the IZO channel and the Nafion electrolyte, emulating various synaptic functions with short-term and long-term plasticity. When positive (negative) gate voltage pulses are consecutively applied, the device exhibits long-term potentiation (depression) at the same number of steps as the number of input pulses. Based on these characteristics, an artificial neural network using this transistor shows ∼84% image recognition accuracy for handwritten digits. The subject transistor also successfully mimics paired-pulse facilitation and depression, Hebbian spike-timing-dependent plasticity, and Pavlovian associative learning followed by extinction activities. Finally, dynamical pattern image memorization is demonstrated in a 5 × 5 array of these synaptic transistors. The results indicate that EBL patternable Nafion electrolytes have great potential for use in the fabrication and circuit-level integration of synaptic devices for neuromorphic computing applications.

Nonvolatile memory characteristics associated with oxygen ion exchange in thin-film transistors with indium-zinc oxide channel and HfO2-x gate oxide

Non-charge-storage-based nonvolatile memory characteristics associated with oxygen ion exchange are demonstrated in a thin-film transistor (TFT) composed of an indium-zinc oxide (IZO) channel and an oxygen-deficient HfO2–x gate oxide. A nonvolatile increase in drain current and a reduced threshold voltage are obtained upon application of positive gate voltage, with the opposite characteristics upon application of negative voltage. The device shows nonvolatile retention properties and suitable endurance properties after repeated operations. Modulation of channel conductance occurs as a results of oxygen ion exchange between the HfO2–x gate oxide and the IZO channel, which consequently alters the oxygen vacancy concentration in the IZO channel; these vacancies act as n-type dopants. For comparison, a device with a thin SiO2 layer inserted between the HfO2–x gate oxide and the IZO channel to prevent oxygen ion exchange shows only the increased threshold voltage upon application of a positive gate voltage as a result of electron charging. These results verify the conductance modulation mechanism associated with oxygen ion exchange at the interface of the HfO2–x gate oxide and the IZO channel. In addition, the nonvolatile memory characteristics of the device are indicative of its potential for non-charge-storage-based nonvolatile memory application.

PH-dependent plasticity regulation in proton/electron hybrid oxide-based synaptic transistors

In bio-neural systems, ionic fluxes dominate the regulation of neuroplasticity. Inspired by such biological strategies, indium-zinc-oxide (IZO) transistors gated by nanogranular SiO2 electrolyte films were proposed for synaptic behavior emulations. Due to the strong proton/electron coupling effect, the carrier density of IZO channel layer can be effectively tuned by a pH buffer solution on the SiO2 electrolyte dielectrics. The pH-dependent synaptic responses, such as excitatory postsynaptic current (EPSC) and paired pulse facilitation (PPF), were discussed in detail based on the surface charging effect. Most importantly, an enhanced pH sensitivity in terms of the relative gain of EPSC amplitude between pH = 4 and pH = 10 was demonstrated by multi-spike trains. Such IZO-based synaptic transistors are promising for low-power neuromorphic sensing systems.

Low-Voltage Oxide-Based Synaptic Transistors for Spiking Humidity Detection

In order to obtain higher humidity sensitivity, shorter response/recover time, and lower energy consumption, we investigate the dynamic humidity sensing characteristics of indium–zinc-oxide (IZO)-based synaptic transistors with graphene oxide/chitosan composite electrolyte films as the gate dielectrics. Here, the short-term synaptic plasticity parameters, such as excitatory post-synaptic current, paired-pulse facilitation index, and high-pass filtering coefficient, were used for quantitative characterization of the relative humidity. The spiking humidity response time and energy consumption of such synaptic transistors are estimated to be 30 ms and 2.2 nJ, respectively. At the same time, a model based on the humidity-dependent proton gating and the adsorption of water molecules at the IZO channel surface is proposed.

A Hybrid Phototransistor Neuromorphic Synapse

In this paper, a synaptic transistor based on the indium zinc oxide (IZO)–hafnium oxide (HfO2) thin film structure was demonstrated. Blue light pulses (470 nm) were used as the presynaptic stimulus, the IZO channel was used as the postsynaptic membrane, and the HfO2 electrolyte film was regarded as the synaptic cleft. The synaptic transistor exhibited the behavior of paired-pulse facilitation. With different light power densities, the channel current of the transistor can be regulated to different levels, corresponding to different synaptic weights. In addition, the transistor showed the brain’s memory behaviors including the short-term memory and the transition from the short to the long term memory. The synaptic behaviors of the transistor can be explained by the trapping and releasing processes of the photo-generated carriers.

Inhibitory synapses mimicking in flexible protonic/electronic hybrid rectifying devices gating by chitosan electrolyte

Flexible protonic/electronic hybrid rectifying devices gating by chitosan electrolyte were fabricated on polyethylene terephthalate (PET) substrate. indium zinc oxide (IZO) source/drain electrodes with a self-assembled IZO channel were prepared by RF sputtering with a nickel shadow mask. The IZO channel was modified by protonic/electronic coupling and drain current (I D) exhibited rectifying characteristics by short connecting source electrode with bottom indium tin oxide (ITO) film. Such devices were used to mimic inhibitory synapses. Synaptic behaviours, like paired-pulse depression and long-term depression were successfully mimicked in flexible artificial inhibitory synapses. Such inhibitory synaptic devices have potential application for serving as a building brick for future brain-inspired computation systems.

Temporal and voltage stress stability of high performance indium-zinc-oxide thin film transistors

Thin film transistors (TFTs) based on transparent oxide semiconductors, such as indium zinc oxide (IZO), are of interest due to their improved characteristics compared to traditional a-Si TFTs. Previously, we reported on top-gated IZO TFTs with an in-situ formed HfO2 gate insulator and IZO active channel, showing high performance: on/off ratio of ∼107, threshold voltage VT near zero, extracted low-field mobility µ0=95cm2/V·s, and near-perfect subthreshold slope at 62mV/decade. Since device stability is essential for technological applications, in this paper we report on the temporal and voltage stress stability of IZO TFTs. Our devices exhibit a small negative VT shift as they age, consistent with an increasing carrier density resulting from an increasing oxygen vacancy concentration in the channel. Under gate bias stress, freshly annealed TFTs show a negative VT shift during negative VG gate bias stress, while aged (>1week) TFTs show a positive VT shift during negative VG stress. This indicates two competing mechanisms, which we identify as the field-enhanced generation of oxygen vacancies and the field-assisted migration of oxygen vacancies, respectively. A simplified kinetic model of the vacancy concentration evolution in the IZO channel under electrical stress is provided.

Electronic transport parameters of indium zinc oxide thin films after Al2O3/HfO2 top-dielectric formation annealing

Oxide-based dielectrics can be formed on indium zinc oxide (IZO) through oxidation of deposited metallic layer such as Al and Ti. The metal/IZO reactions necessary for dielectric oxidization tend to consume oxygen from the IZO channel and thus lead to the formation of oxygen-deficiency defects in the IZO layer. However, if the formation of such defects is significant at room temperature, it may adversely impact the long-term reliability of IZO devices. This work presents results of a study of electronic transport in IZO insulator/semiconductor structures measured immediately after the oxidizing anneal and 1 year thereafter. The sample measured 1 year after annealing exhibited a nearly one order of magnitude increase in electron concentration, indicating that donor-like defects are formed under ambient room temperature conditions. Furthermore, and in contrast to the isotropic nature of electron transport in the sample measured immediately after annealing, significant anisotropy in transport parameters was found in the sample measured 1 year after annealing.

High performance top-gated indium–zinc–oxide thin film transistors with in-situ formed HfO2 gate insulator

We report on top-gated indium–zinc–oxide (IZO) thin film transistors (TFTs) with an in-situ formed HfO2 gate dielectric insulator. Building on our previous demonstration of high-performance IZO TFTs with Al2O3/HfO2 gate dielectric, we now report on a one-step process, in which Hf is evaporated onto the 20nm thick IZO channel, forming a partially oxidized HfOx layer, without any additional insulator in-between. After annealing in air at 300°C, the in-situ reaction between partially oxidized Hf and IZO forms a high quality HfO2 gate insulator with a low interface trapped charge density NTC~2.3×1011cm−2 and acceptably low gate leakage <3×10−7A/cm2 at gate voltage VG=1V. The annealed TFTs with gate length LG=50μm have high mobility ~95cm2/V∙s (determined via the Y-function technique), high on/off ratio~107, near-zero threshold voltage VT=−0.02V, and a subthreshold swing of 0.062V/decade, near the theoretical limit. The on-current of our proof-of-concept TFTs is relatively low, but can be improved by reducing LG, indicating that high-performance top-gated HfO2-isolated IZO TFTs can be fabricated using a single-step in-situ dielectric formation approach.

Electrostatically transparent graphene quantum-dot trap layers for efficient nonvolatile memory

In this study, we have demonstrated nonvolatile memory devices using graphene quantum-dots (GQDs) trap layers with indium zinc oxide (IZO) semiconductor channel. The Fermi-level of GQD was effectively modulated by tunneling electrons near the Dirac point because of limited density of states and weak electrostatic screening in monolayer graphene. As a result, large gate modulation was driven in IZO channel to achieve a subthreshold swing of 5.21 V/dec (300 nm SiO2 gate insulator), while Au quantum-dots memory shows 15.52 V/dec because of strong electrostatic screening in metal quantum-dots. Together, discrete charge traps of GQDs enable stable performance in the endurance test beyond 800 cycles of programming and erasing. Our study suggests the exciting potential of GQD trap layers to be used for a highly promising material in non-volatile memory devices.

Top-Gated Indium–Zinc–Oxide Thin-Film Transistors With In Situ Al2O3/HfO2 Gate Oxide

We report on top-gated indium-zinc-oxide (IZO) thin-film transistors (TFTs) with a 3-nm layer of aluminum between the IZO active layer and high-k HfO 2 gate insulator. A series of anneals at 300°C was used to convert the Al metal into Al 2 O 3 , resulting in high-performance top-gated TFTs. The 8-h-annealed TFT with Al layer has a threshold voltage |V T | <; 0.5 V, an ON/OFF ratio of 1 × 10 7 , a subthreshold slope (SS) of 0.14 V/decade, and a saturation mobility μs ~115 cm 2/ V · s in devices with L G = 50μm gate length. For smaller devices with L G = 5 μm, the threshold voltage and SS are similar, but the ON/OFF ratio and mobility are lower. Cross-sectional TEM images and C-V G characteristics with little hysteresis confirm that the thin Al layer, converted in situ into Al 2 O 3 , can protect the IZO channel during processing and produce a good high-k gate-stack.

Solution-processable LaZrOx/SiO2 gate dielectric at low temperature of 180 °C for high-performance metal oxide field-effect transistors.

Although solution-processable high-k inorganic dielectrics have been implemented as a gate insulator for high-performance, low-cost transition metal oxide field-effect transistors (FETs), the high-temperature annealing (>300 °C) required to achieve acceptable insulating properties still limits the facile realization of flexible electronics. This study reports that the addition of a 2-dimetylamino-1-propanol (DMAPO) catalyst to a perhydropolysilazane (PHPS) solution enables a significant reduction of the curing temperature for the resulting SiO2 dielectrics to as low as 180 °C. The hydrolysis and condensation of the as-spun PHPS film under humidity conditions were enhanced greatly by the presence of DMAPO, even at extremely low curing temperatures, which allowed a smooth surface (roughness of 0.31 nm) and acceptable leakage characteristics (1.8 × 10(-6) A/cm(2) at an electric field of 1MV/cm) of the resulting SiO2 dielectric films. Although the resulting indium zinc oxide (IZO) FETs exhibited an apparent high mobility of 261.6 cm(2)/(V s), they suffered from a low on/off current (ION/OFF) ratio and large hysteresis due to the hygroscopic property of silazane-derived SiO2 film. The ION/OFF value and hysteresis instability of IZO FETs was improved by capping the high-k LaZrOx dielectric on a solution-processed SiO2 film via sol-gel processing at a low temperature of 180 °C while maintaining a high mobility of 24.8 cm(2)/(V s). This superior performance of the IZO FETs with a spin-coated LaZrOx/SiO2 bilayer gate insulator can be attributed to the efficient intercalation of the 5s orbital of In(3+) ion in the IZO channel, the good interface matching of IZO/LaZrOx and the carrier blocking ability of PHPS-derived SiO2 dielectric film. Therefore, the solution-processable LaZrOx/SiO2 stack can be a promising candidate as a gate dielectric for low-temperature, high-performance, and low-cost flexible metal oxide FETs.

Modification of a polymer gate insulator by zirconium oxide doping for low temperature, high performance indium zinc oxide transistors

Indium zinc oxide (IZO) thin film transistors (TFTs) with poly(4-vinylphenol-co-methylmethacrylate) (PVP-co-PMMA) gate insulators were fabricated at a low temperature (250 °C). The bottom gate IZO TFTs with a PVP-co-PMMA gate electric film exhibited inferior device performance to the top gate IZO TFTs, which was attributed to sputtering damage of the underlying polymer gate dielectric film during IZO channel formation. The charge carrier transport and interface properties of the IZO TFTs could be further improved by introducing a ZrO2 precursor to the polymer gate insulator. The ZrO2 molecules were well dispersed in the polymer film. The resulting hybrid dielectric film showed a higher capacitance and a smoother morphology than the PVP-co-PMMA dielectric film. The hybrid dielectric-gated IZO TFT had a high mobility of 28.4 cm2 V−1 s−1, low subthreshold gate swing of 0.70 V per decade, and a high Ion/off ratio of 4.0 × 107.

Contact resistance improvement using interfacial silver nanoparticles in amorphous indium-zinc-oxide thin film transistors

We describe an approach to reduce the contact resistance at compositional conducting/semiconducting indium-zinc-oxide (IZO) homojunctions used for contacts in thin film transistors (TFTs). By introducing silver nanoparticles (Ag NPs) at the homojunction interface between the conducting IZO electrodes and the amorphous IZO channel, we reduce the specific contact resistance, obtained by transmission line model measurements, down to ∼10−2 Ω cm2, ∼3 orders of magnitude lower than either NP-free homojunction contacts or solid Ag metal contacts. The resulting back-gated TFTs with Ag NP contacts exhibit good field effect mobility of ∼27 cm2/V s and an on/off ratio &amp;gt;107. We attribute the improved contact resistance to electric field concentration by the Ag NPs.

Classical Conditioning Mimicked in Junctionless IZO Electric-Double-Layer Thin-Film Transistors

Classical conditioning, a fundamental property in associative learning, has aroused a wide range of interests in neuromorphic engineering. Here, junctionless indium-zinc-oxide (IZO)-based electric-double-layer transistors gated by nanogranular SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> proton conducting electrolyte films are proposed to mimic such behavior. Proton-related electrochemical doping can result in evident oxygen vacancy in IZO channel layer, which is demonstrated by X-ray photoelectron spectroscopy measurements. After such electrochemical forming in half part of the IZO channel, conditioning response can be observed by gate-pulse training process.

Low-voltage protonic/electronic hybrid indium zinc oxide synaptic transistors on paper substrates

Low-voltage (1.5 V) indium zinc oxide (IZO)-based electric-double-layer (EDL) thin-film transistors (TFTs) gated by nanogranular proton conducting SiO2 electrolyte films are fabricated on paper substrates. Both enhancement-mode and depletion-mode operation are obtained by tuning the thickness of the IZO channel layer. Furthermore, such flexible IZO protonic/electronic hybrid EDL TFTs can be used as artificial synapses, and synaptic stimulation response and short-term synaptic plasticity function are demonstrated. The protonic/electronic hybrid EDL TFTs on paper substrates proposed here are promising for low-power flexible paper electronics, artificial synapses and bioelectronics.

Solution-Processed Chitosan-Gated IZO-Based Transistors for Mimicking Synaptic Plasticity

Indium-zinc-oxide (IZO)-based electric double layer (EDL) transistors gated by solution-processed chitosan electrolyte films are fabricated on glass substrates and used for mimicking synaptic plasticity. The conductance of the self-assembled IZO channel tuned by the proton electrostatic modulation and electrochemical doping is regarded as the synaptic weight. Synaptic behaviors like paired-pulse facilitation and long-term potentiation are mimicked in the chitosan-gated IZO-based EDL transistor. Our results suggest that gate pulse amplitude and number have great influence on the synaptic plasticity transition.

Effects of Etching Residue on Positive Shift of Threshold Voltage in Amorphous Indium–Zinc-Oxide Thin-Film Transistors Based on Back-Channel-Etch Structure

The electronic properties of amorphous indium-zinc-oxide (IZO) thin film transistors (TFTs) with back-channel-etch (BCE) structure was investigated. In the cyclic-transfer characteristics test, the initial transfer curve of BCE-type transistors exhibited a significant hysteresis phenomenon under a high-gate bias (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GS</sub> ). However, in the following cycles of the transfer curves, the hysteresis was significantly reduced, and the curves nearly overlapped the reverse sweeping of the initial transfer characteristics. Additionally, the threshold voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> ) shift in the initial hysteresis loops increased with the increase of the V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GS</sub> . Those phenomena may be attributed to the molybdenum oxide (MoO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> ) residue generated during the patterning of the source/drain electrodes using hydrogen peroxide (H <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> )-based etchants. It is believed that etching residue acts as the acceptor-like states trapping electrons into the back interface between the channel and the residual layer. To eliminate the V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> shift in BCE-TFTs, SF <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">6</sub> plasma is applied to the back surface of the IZO channel layer. The modified devices show a more stable V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> .

Short-Term Memory to Long-Term Memory Transition Mimicked in IZO Homojunction Synaptic Transistors

Short-term memory (STM) is a temporary potentiation of neural connections, and it can be transformed to long-term memory (LTM) through the process of rehearsal and meaningful association. Here, indium-zinc oxide (IZO)-based synaptic transistors gated by SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> -based proton conducting electrolyte films were fabricated. STM behavior is demonstrated by paired-pulse facilitation experiment. STM to LTM transition is realized by increasing the pulse amplitude or pulse number. Interfacial electrostatic modulation and electrochemical doping of IZO channel by mobile proton play an important role for such memory behavior and memory transition.

Performance improvement of oxide thin-film transistors with a two-step-annealing method

In this paper, a thin-film transistor (TFT) with indium zinc oxide (IZO) channel layer was fabricated using a two-step-annealing method in which the IZO film experienced annealing steps before the etch-stopper-layer formation and after the whole device completion. The device showed better uniformity and better stability under positive bias stress, negative bias illumination stress, and temperature stress, compared to those with only one post annealing step. The calculated falling rate of the Fermi lever of the IZO channel for the two-step annealing device was as high as 0.593eV/V, compared to 0.213eV/V for the only-post-annealing-step one. And the corresponding density of subgap state was 4.4×1015 and 1.6×1016eV−1cm−3 for the device with two annealing steps and with only one post annealing step, respectively.