Indium Phosphide Heterojunction Bipolar Transistor Research Articles

Model Parameters and Degradation Mechanism Analysis of Indium Phosphide Hetero-Junction Bipolar Transistors Exposed to Proton Irradiation

The degradation properties of Indium phosphide hetero-junction bipolar transistors (InP HBTs) under proton irradiation are studied and modelled using a compact model for pre-irradiation, post-irradiation, and post-annealing. The variation rates of the model parameters, such as the base–emitter saturation current (ISE) and ideality factor in the ideal region (NE) in the forward Gummel characteristics, the zero-biased capacitance (Cje) and the grading factor (Mjer) in the BE junction capacitance, and the transit time parameter in the base region (Tfb), are analysed to delve into the degradation mechanism induced by proton irradiation. The displacement damage, induced by proton irradiation in the space charge region of the base–emitter junction and in the quasi-neutral bulk base region, is found to be responsible for the decrease in current gain and cut-off frequency. After annealing, the variation rates of the parameters decrease significantly compared to post-irradiation. This suggests that the recombination of unstable defects leads to a slight recovery in the degradation characteristics of InP HBTs after a period of annealing.

An analytic method for parameter extraction of InP HBTs small-signal model

PurposeHigh-speed Indium Phosphide (InP) HBTs have been widely used to design high-speed analog, digital and mixed-signal integrated circuits. The purpose of this study is to propose a new parameter extraction procedure for determining an improved T-topology small-signal equivalent circuit of InP heterojunction bipolar transistors (HBTs).Design/methodology/approachThe alternating current crowding effect is considered through adding the intrinsic base capacitance in the small-signal equivalent circuit. All of the circuit parameters are extracted directly without using any approximation.FindingsThe extraction technique is more easily understood and clearer than other extraction methods, as the equations are derived from the S-parameters by peeling peripheral elements from small-signal models to get reduced ones and extracting each equivalent-circuit parameter using each equation.Originality/valueTo validate the presented parameter extraction technology, an n-p-n emitter-up InP HBT was analyzed adopting the method. Excellent agreement between measured and modeled S-parameters is obtained up to 40 GHz.

Gamma-Induced Degradation Effect of InP HBTs Studied by Keysight Model

The gamma irradiation effect in indium phosphide (InP) heterojunction bipolar transistors (HBTs) is studied in this paper. The direct-current (DC) and alternating-current (AC) characteristics are investigated before and after an irradiation dose of 10 Mrad(Si). The main effects of gamma irradiation for InP HBTs are the following: increase of forward Gummel base current at low bias regime, decrease of common emitter collector current, increase of junction capacitances, and decrease of cutoff frequency. The Keysight model is adopted to describe behaviors of InP HBTs including DC and AC behaviors. The Keysight model parameter values are extracted before and after irradiation, in turn to study the physical mechanisms responsible for irradiation-induced degradation in InP HBTs.

The impact of laser energy, bias and irradiation positions on single event transients of InP HBT

The mechanism of single event transients in indium phosphide heterojunction bipolar transistors are studied with different laser energy, collector and irradiation positions based on a pulsed laser experiment. The area of the depletion region neutralized by the laser track determines the area of the funnel region, and affects the total charges collected by collector QTotal. The total charge collection consists of the charge collected in the depletion region, the charges collected in funnel region, and the diffusion charges. The larger the area of the neutralized depletion region, the larger the area of the funnel region, thus, the more electron–hole pairs would be collected. The influence of laser energy, collector bias and irradiation positions on total charge collection is studied and discussed in detail.

Electrical spectrum synthesis technique using digital pre‐processing and ultra‐broadband electrical bandwidth doubler for high‐speed optical transmitter

Proposed is an electrical spectrum synthesis technique that converts low-speed signals to a high-speed signal using transmitter-side digital signal processing (DSP) and an ultra-broadband electrical bandwidth doubler. The transmitter-side DSP converts a high-speed signal to low-speed upper and lower sideband signals, down- and up-converts the low-speed signals into baseband signals, and adds and subtracts the in-phase and the quadrature components of the baseband signals. The digital pre-processed low-speed signals output from digital-to-analogue converters are multiplexed to the high-speed signal by the bandwidth doubler, which consists of analogue multiplexers designed and fabricated using in-house indium phosphide heterojunction bipolar transistor technologies. A 120 GBaud quadrature phase shift keying signal has been successfully generated by using the proposed technique as a demonstration of a high-speed optical transmitter.

A Broadband THz On-Chip Transition Using a Dipole Antenna with Integrated Balun

A waveguide-to-microstrip transition is an essential component for packaging integrated circuits (ICs) in rectangular waveguides, especially at millimeter-wave and terahertz (THz) frequencies. At THz frequencies, the on-chip transitions, which are monolithically integrated in ICs are preferred to off-chip transitions, as the former can eliminate the wire-bonding process, which can cause severe impedance mismatch and additional insertion loss of the transitions. Therefore, on-chip transitions can allow the production of low cost and repeatable THz modules. However, on-chip transitions show limited performance in insertion loss and bandwidth, more seriously, this is an in-band resonance issue. These problems are mainly caused by the substrate used in the THz ICs, such as an indium phosphide (InP), which exhibits a high dielectric constant, high dielectric loss, and high thickness, compared with the size of THz waveguides. In this work, we propose a broadband THz on-chip transition using a dipole antenna with an integrated balun in the InP substrate. The transition is designed using three-dimensional electromagnetic (EM) simulations based on the equivalent circuit model. We show that in-band resonances can be induced within the InP substrate and also prove that backside vias can effectively eliminate these resonances. Measurement of the fabricated on-chip transition in 250 nm InP heterojunction bipolar transistor (HBT) technology, shows wideband impedance match and low insertion loss at H-band frequencies (220–320 GHz), without in-band resonances, due to the properly placed backside vias.

InP HBT Technologies for THz Integrated Circuits

Highly scaled indium phosphide (InP) heterojunction bipolar transistor (HBT) technologies have been demonstrated with maximum frequencies of oscillation ( $f_{\max}$ ) of >1 THz and circuit operation has been extended into the lower end of the terahertz (THz) frequency band. InP HBTs offer high radio-frequency (RF) output power density, millivolt (mV) threshold uniformity, and high levels of integration. Integration with multilevel thin-film wiring permits the realization of compact and complex THz monolithic integrated circuits (TMICs). Circuit results reported from InP HBT technologies include: 200-mW power amplifiers at 210 GHz, 670-GHz amplifiers and fundamental oscillators, and fully integrated 600-GHz transmitter circuits. We review the state of the art in THz-capable InP HBT devices and integrated circuit (IC) technologies. Challenges in extending transistor bandwidth and in circuit design at THz frequencies will also be addressed.

A Nonuniform Sampler for Wideband Spectrally-Sparse Environments

We present a wide bandwidth, compressed sensing based nonuniform sampling (NUS) system with a custom sample-and-hold chip designed to take advantage of a low average sampling rate. By sampling signals nonuniformly, the average sample rate can be more than a magnitude lower than the Nyquist rate, provided that these signals have a relatively low information content as measured by the sparsity of their spectrum. The hardware design combines a wideband Indium-Phosphide heterojunction bipolar transistor sample-and-hold with a commercial off-the-shelf analog-to-digital converter to digitize an 800 MHz to 2 GHz band (having 100 MHz of noncontiguous spectral content) at an average sample rate of 236 Ms/s. Signal reconstruction is performed via a nonlinear compressed sensing algorithm, and the challenges of developing an efficient implementation are discussed. The NUS system is a general purpose digital receiver. As an example of its real signal capabilities, measured bit-error-rate data for a GSM channel is presented, and comparisons to a conventional wideband 4.4 Gs/s ADC are made.

Indium Phosphide Heterojunction Bipolar Transistors as Magnetic Field Sensors

This paper describes the design, fabrication, and characterization of a sensor for moderately strong magnetic fields (~0.1 T and above) based on a heterojunction bipolar transistor (HBT). Our ferromagnetic-semiconductor hybrid device consisted of a mesa-isolated multistep single heterojunction InGaAs/InP HBT with an integrated 3-D thin-film magnetic structure formed on the base-collector mesa. The latter structure was optimized by simulation to focus the magnetic field into the base region of the HBT, where the interaction of the charge carriers and the magnetic field takes place. We report a minimum signal-to-noise ratio for the sensors of 36.4 dB, magnetic field sensitivity of at least 33.9% T-1, an angle sensitivity of 10% rad-1, and an equivalent noise of at most 2 mT. The sensors are novel in that they are fabricated using a highly scaled layer design of the type used in radio-frequency monolithic microwave integrated circuits and are suitable for incorporation in such circuits to increase functionality for low overhead in, for example, distributed sensor networks.

An InP HBT-Based Oscillator Monolithically Integrated With a Photodiode

An indium phosphide heterojunction bipolar transistor (InP HBT) oscillator chip was monolithically integrated with an on chip p-i-n photodiode. A controllable locking range was obtained in unidirectional injection locking. High-purity optoelectronic oscillator with parasitic modes lower than -4 dBc resulted from bidirectional injection locking. The optoelectronic oscillator power consumption was 50 mW while providing output power of - 2 dBm . The overall chip size is 1.3 times 0.8 mm.

InP Bipolar ICs: Scaling Roadmaps, Frequency Limits, Manufacturable Technologies

Indium phosphide heterojunction bipolar transistors (HBTs) find applications in very wide-band digital and mixed-signal integrated circuits (ICs). Devices fabricated in high-yield process flows at 500 nm feature size obtain 450 GHz cutoff frequencies and 5 V breakdown and enable high yield fabrication of integrated circuits having more than 3000 transistors. Laboratory devices at 250 nm feature size obtain 755 GHz . We describe device and circuit bandwidth limits associated with HBTs, develop scaling roadmaps for HBTs having lithographic minimum feature sizes between 512 and 64 nm, and identify key technological challenges in realizing 480-GHz digital ICs and 1000-GHz amplifiers. Key features of manufacturable self-aligned dielectric sidewall processes are described in detail.

Silicon transistor hits 500GHz performance

Low-cost silicon germanium technology is chasing indium phosphide heterojunction bipolar transistor performance. US researchers have pushed the cut-off frequency for SiGe HBTs to 500 GHz, but this is still about 200 GHz behind the best InP result so far.

Collector-pedestal InGaAs/InP DHBTs fabricated in a single-growth, triple-implant process

This letter reports InP/In/sub 0.53/Ga/sub 0.47/As/InP double heterojunction bipolar transistors (DHBTs) employing an N/sup +/ subcollector and N/sup +/ collector pedestal-formed by blanket Fe and patterned Si ion implants, intended to reduce the extrinsic collector-base capacitance C/sub cb/ associated with the device footprint. The Fe implant is used to compensate Si within the upper 130 nm of the N/sup +/ subcollector that lies underneath the base ohmic contact, as well as compensate the /spl sim/1-7/spl times/10/sup -7/ C/cm/sup 2/ surface charge at the interface between the indium phosphide (InP) substrate and the N/sup $/collector drift layer. By implanting the subcollector, C/sub cb/ associated with the base interconnect pad is eliminated, and when combined with the Fe implant and selective Si pedestal implant, further reduces C/sub cb/ by creating a thick extrinsic collector region underneath the base contact. Unlike previous InP heterojunction bipolar transistor collector pedestal processes, multiple epitaxial growths are not required. The InP DHBTs here have simultaneous 352-GHz f/sub /spl tau// and 403-GHz f/sub max/. The dc current gain /spl beta//spl ap/38, BV/sub ceo/=6.0 V, BV/sub cbo/=5.4 V, and I/sub cbo/<50 pA at V/sub cb/=0.3 V.

Clock and data recovery IC for 40-Gb/s fiber-optic receiver

The integrated clock and data recovery (CDR) circuit is a key element for broad-band optical communication systems at 40 Gb/s. We report a 40-Gb/s CDR fabricated in indium-phosphide heterojunction bipolar transistor (InP HBT) technology using a robust architecture of a phase-locked loop (PLL) with a digital early-late phase detector. The faster InP HBT technology allows the digital phase detector to operate at the full data rate of 40 Gb/s. This, in turn, reduces the circuit complexity (transistor count) and the voltage-controlled oscillator (VCO) requirements. The IC includes an on-chip LC VCO, on-chip clock dividers to drive an external demultiplexer, and low-frequency PLL control loop and on-chip limiting amplifier buffers for the data and clock I/O. To our knowledge, this is the first demonstration of a mixed-signal IC operating at the clock rate of 40 GHz. We also describe the chip architecture and measurement results.