Indium Gallium Zinc Oxide Thin-film Transistors Research Articles

Addressing Mobility Overestimation in Short-Channel IGZO TFTs Using the Gated Van der Pauw Method.

The determination of field-effect mobility in indium gallium zinc oxide (IGZO) thin-film transistors (TFTs) is pivotal for advancing high-performance electronic devices. However, accurately evaluating the field-effect mobility in IGZO-TFTs with short channel lengths of less than a few micrometers poses a formidable challenge. This difficulty arises due to the increasing significance of contact resistance in the total resistance as the channel length decreases. Consequently, increasing contact resistance can lead to inaccurate sheet resistance values, resulting in overestimating critical parameters, such as mobility and contact resistance, during device evaluations. Therefore, a precise method for extracting sheet resistance, an intrinsic channel characteristic, is imperative for short-channel IGZO TFTs. Herein, a gated van der Pauw (gVDP) method was employed to extract sheet resistance precisely and independently of contact resistance. This contact-resistance-independent approach mitigates the risk of overestimating charge behaviors in IGZO TFTs. Furthermore, it facilitates precise evaluations of intrinsic channel mobility, enabling accurate predictions of the maximum performance of devices with short channels.

Effect of ozone gas exposure on drain current of solution-processed IGZO-TFT

The drain current (ID) of indium gallium zinc oxide thin-film transistors (IGZO-TFTs), fabricated by spin coating, decreases even when they are exposed to ozone gas at a concentration equal to or lower than 5 ppm. The ID reduction rate increases when the film thickness and the firing temperature in the spin-coating process of IGZO layer decreases. In these samples, the peak intensity ratio of the O 1s X-ray photoelectron spectroscopy (XPS) peak due to the OH group and the intensity of the infrared (IR) absorption band at 3000 cm−1–3500 cm−1 due to the OH stretching vibration increase. This indicates that OH groups within the IGZO film contribute to the ozone reaction mechanism. These findings are significant for developing high-sensitivity ozone sensors using a simpler process.

Analog reservoir computing via ferroelectric mixed phase boundary transistors

Analog reservoir computing (ARC) systems have attracted attention owing to their efficiency in processing temporal information. However, the distinct functionalities of the system components pose challenges for hardware implementation. Herein, we report a fully integrated ARC system that leverages material versatility of the ferroelectric-to-mixed phase boundary (MPB) hafnium zirconium oxides integrated onto indium–gallium–zinc oxide thin-film transistors (TFTs). MPB-based TFTs (MPBTFTs) with nonlinear short-term memory characteristics are utilized for physical reservoirs and artificial neuron, while nonvolatile ferroelectric TFTs mimic synaptic behavior for readout networks. Furthermore, double-gate configuration of MPBTFTs enhances reservoir state differentiation and state expansion for physical reservoir and processes both excitatory and inhibitory pulses for neuronal functionality with minimal hardware burden. The seamless integration of ARC components on a single wafer executes complex real-world time-series predictions with a low normalized root mean squared error of 0.28. The material-device co-optimization proposed in this study paves the way for the development of area- and energy-efficient ARC systems.

Modeling and characterization of low frequency noise in self-aligned top-gate coplanar IGZO thin-film transistors

Abstract A modified low-frequency noise (LFN) model was proposed to accurately estimate the quality of the gate dielectric in self-aligned top-gate (SA TG) coplanar structure indium–gallium–zinc oxide (IGZO) thin-film transistors (TFTs). The proposed LFN model was derived by modifying the conventional carrier number with correlated mobility fluctuation model considering the peculiar characteristics of SA TG coplanar IGZO TFTs such as the channel length reduction due to the diffusion of hydrogen atoms or oxygen vacancies from the source/drain to the channel, as well as the relatively large source/drain parasitic resistance. The proposed model was validated by demonstrating that the measured LFN values were in good agreement with the predicted values from the proposed model for all SA TG coplanar IGZO TFTs with SiO2 gate dielectrics deposited under different plasma-enhanced chemical vapor deposition (PECVD) power densities. The near-interface gate dielectric trap densities extracted from each TFT using the proposed LFN model revealed a clear increase as the PECVD power increased, which is considered a major cause of poor positive-bias-temperature-stress stability of the SA TG coplanar IGZO TFT with SiO2 gate dielectric deposited under high PECVD power conditions.

Enhanced Electrical Properties and Stability in IGZO TFTs via Low-Temperature Activation with MgOx Layer.

We propose the introduction of a magnesium oxide (MgOx) layer to reduce the temperature required for the activation of indium gallium zinc oxide (IGZO) thin films. By incorporating the MgOx layer between the IGZO channel layer and the gate insulator layer, the required activation temperature is lowered from 300 to 200 °C while enhancing the electrical performance of the IGZO thin-film transistor (TFT). Specifically, the field effect mobility is improved from 6.40 to 16.12 cm2/(V s), the on/off current ratio is enhanced from 1.62 × 109 to 7.16 × 109, and subthreshold swing is enhanced from 0.48 to 0.46 V/decade. Furthermore, IGZO TFTs with the MgOx layer exhibit enhancements in threshold voltage (VTH) shift compared to TFTs without the MgOx layer under positive bias stress (VGS = 20 V and VDS = 0.1 V for 10,000 s) and negative bias stress (VGS = -20 V and VDS = 0.1 V for 10,000 s): the VTH shifts are decreased from 2.40 to 1.72 V and from 0.56 to 0.53 V, respectively. These enhancements are verified through various analyses and are attributed to the diffusion of Mg atoms into the IGZO front channel during the low-temperature activation process, which results in the formation of Mg-doped IGZO between the MgOx and IGZO channel layers.

One-volt oxide based complementary circuit

In low-power electronics, there is a substantial demand for high-performance p-type oxide thin-film transistors (TFTs) that are capable of efficient operation at low voltages. In this study, we employ anodization to form an aluminum oxide gate dielectric layer, enabling the fabrication of p-type tin oxide (SnO) TFTs that effectively operate at a low voltage of 1 V. Under optimal device fabrication conditions, the SnO TFT demonstrates an on/off current ratio exceeding 103 and a saturation mobility of 1.94 cm2 V−1 s−1 at 1 V operation. The optimal SnO TFT fabrication conditions are subsequently used to fabricate a complementary inverter, comprising a SnO TFT and an n-type indium gallium zinc oxide TFT, achieving a gain of up to 38 at a 1 V supply voltage. Notably, the inverter’s switching point voltage is finely tuned to the ideal value, precisely half of the supply voltage. This oxide-based complementary inverter showcases promising potential in low-power electronics.

Optimizing Length Scalability of InGaZnO Thin‐Film Transistors through Lateral Carrier Profile Engineering and Negative ΔL Extension Structure

AbstractThe lateral carrier profile of amorphous indium gallium zinc oxide (IGZO) thin‐film transistors (TFTs) plays a significant role in determining the effective channel length (Leff) and length scalability even when the physical gate length (Lg) is the same. Especially, devices with high carrier concentration that have a high mobility of 14.54 cm2 V·s−1 suffer from severe short channel effects at Lg = 1 µm due to the reduced Leff. The current work proposes a systematic methodology for optimizing length scalability for a given Lg that involves engineering of the lateral carrier profile. Unique lateral carrier profiles are extracted using contour maps of ΔL and RSD as a function of carrier profile parameters, and they are validated by comparing the measured Leff, drain‐to‐source resistance, and current‐voltage characteristics with the results of simulations using the extracted carrier profiles. Further, to overcome the trade‐off between enhanced mobility and degraded VT roll‐off that occurs with increasing carrier concentration, an IGZO TFT with gate‐insulator shoulders is fabricated to structurally form negative ΔL and physically increase Leff, while also obtaining a high carrier concentration, ultimately achieving both optimal electrical performance, with mobility of 17.50 cm2 V·s−1, and complete control of the electrostatic integrity of the gate.

Effects of Laser Treatment of Terbium-Doped Indium Oxide Thin Films and Transistors.

In this study, a KrF excimer laser with a high-absorption coefficient in metal oxide films and a wavelength of 248 nm was selected for the post-processing of a film and metal oxide thin film transistor (MOTFT). Due to the poor negative bias illumination stress (NBIS) stability of indium gallium zinc oxide thin film transistor (IGZO-TFT) devices, terbium-doped Tb:In2O3 material was selected as the target of this study. The XPS test revealed the presence of both Tb3+ and Tb4+ ions in the Tb:In2O3 film. It was hypothesized that the peak of the laser thermal effect was reduced and the action time was prolonged by the f-f jump of Tb3+ ions and the C-T jump of Tb4+ ions during the laser treatment. Studies related to the treatment of Tb:In2O3 films with different laser energy densities have been carried out. It is shown that as the laser energy density increases, the film density increases, the thickness decreases, the carrier concentration increases, and the optical band gap widens. Terbium has a low electronegativity (1.1 eV) and a high Tb-O dissociation energy (707 kJ/mol), which brings about a large lattice distortion. The Tb:In2O3 films did not show significant crystallization even under laser energy density treatment of up to 250 mJ/cm2. Compared with pure In2O3-TFT, the doping of Tb ions effectively reduces the off-state current (1.16 × 10-11 A vs. 1.66 × 10-12 A), improves the switching current ratio (1.63 × 106 vs. 1.34 × 107) and improves the NBIS stability (ΔVON = -10.4 V vs. 6.4 V) and positive bias illumination stress (PBIS) stability (ΔVON = 8 V vs. 1.6 V).

Specific contact resistivity reduction in amorphous IGZO thin-film transistors through a TiN/IGTO heterogeneous interlayer

Oxide semiconductors have gained significant attention in electronic device industry due to their high potential for emerging thin-film transistor (TFT) applications. However, electrical contact properties such as specific contact resistivity (ρC) and width-normalized contact resistance (RCW) are significantly inferior in oxide TFTs compared to conventional silicon metal oxide semiconductor field-effect transistors. In this study, a multi-stack interlayer (IL) consisting of titanium nitride (TiN) and indium-gallium-tin-oxide (IGTO) is inserted between source/drain electrodes and amorphous indium-gallium-zinc-oxide (IGZO). The TiN is introduced to increase conductivity of the underlying layer, while IGTO acts as an n+-layer. Our findings reveal IGTO thickness (tIGTO)-dependent electrical contact properties of IGZO TFT, where ρC and RCW decrease as tIGTO increases to 8 nm. However, at tIGTO > 8 nm, they increase mainly due to IGTO crystallization-induced contact interface aggravation. Consequently, the IGZO TFTs with a TiN/IGTO (3/8 nm) IL reveal the lowest ρC and RCW of 9.0 × 10−6 Ω·cm2 and 0.7 Ω·cm, significantly lower than 8.0 × 10−4 Ω·cm2 and 6.9 Ω·cm in the TFTs without the IL, respectively. This improved electrical contact properties increases field-effect mobility from 39.9 to 45.0 cm2/Vs. This study demonstrates the effectiveness of this multi-stack IL approach in oxide TFTs.

Floating body effect in indium–gallium–zinc–oxide (IGZO) thin-film transistor (TFT)

In this paper, the floating body effect (FBE) in indium-gallium-zinc-oxide (IGZO) thin-film transistor (TFT) and the mechanism of device failure caused by that are reported for the first time. If the toggle AC pulses are applied to the gate and drain simultaneously for the switching operation, the drain current of IGZO TFT increases dramatically and cannot show the on/off switching characteristics. This phenomenon was not reported before, and our study reveals that the main cause is the formation of a conductive path between the source and drain: short failure. It is attributed in part to the donor creation at the drain region during the high voltage (Vhigh) condition and in part to the donor creation at the source region during the falling edge and low voltage (Vlow) conditions. Donor creation is attributed to the peroxide formation in the IGZO layer induced by the electrons under the high lateral field. Because the donor creation features positive charges, it lowers the threshold voltage of IGZO TFT. In detail, during the Vhigh condition, the donor creation is generated by accumulated electrons with a high lateral field at the drain region. On the other hand, the floating electrons remaining at the short falling edge (i.e., FBE of the IGZO TFT) are affected by the high lateral field at the source region during the Vlow condition. As a result, the donor creation is generated at the source region. Therefore, the short failure occurs because the donor creations are generated and expanded to channel from the drain and source region as the AC stress accumulates. In summary, the FBE in IGZO TFT is reported, and its effect on the electrical characteristics of IGZO TFT (i.e., the short failure) is rigorously analyzed for the first time.

Flexible multi-electrode neural probe using active-matrix design of transistor array

To realize a brain-machine interface, a neural probe is one of key hardware. For the neural probe, a high spatial resolution of an electrode array, high electrical sensitivity, and mechanical flexibility remain challenging and essential issues. In regard to these, implantable multi-electrode neural probe employing active-matrix design with field effect transistors (FETs) can attract attention due to their advantages of a suitable integration density and good signal-amplifying abilities. Therefore, we developed a flexible multi-electrode neural probe employing an active-matrix design based on a two-transistor (2T) scheme for application to a flexible neural signal recording probe. As a proof of concept, 4 × 8 electrode array (32 channels) with TFTs was demonstrated. For the flexible active-matrix design, back-gate indium-gallium-zinc-oxide (IGZO) thin film transistors (TFTs) were fabricated on a polyimide (PI). The TFTs used here can amplify signals and achieve a switching function to drive the active matrix. The probe structure was encapsulated by the same PI material again to achieve flexibility with good reliability, as the sandwich-like structure can induce a neutral plane on the TFT and electrodes. To ensure a high signal-to-noise ratio, the structural and process parameters of the TFT were studied. Among different annealing times and temperatures of the IGZO TFT, the optimized annealing condition of the TFT was found to be 250 °C a 1 hour on a flexible substrate. The width over length of the transistors was optimized to 50 μm/10 μm, and the field-effect mobility was 8.33 cm2/V·s. The on current was 2.28 × 10−6 A at a low driving voltage of 5 V. The transconductance was 2.16 μS and the threshold voltage (Vth) was 1.6 V. By applying 5 V, the switching TFT was turned on, and a doubly amplified signal (> 2.4 times) could be measured on the drain line. The electrode array probe with the active-matrix design can use for accurate neural recording and herald a new generation of flexible neural probes with high spatial resolutions.

A ternary gate-connected threshold switching thin-film transistor

Multi-valued logic has been a significant focus of research in various fields with the advancement of information technology. One approach to realizing ternary logic is integrating of a threshold switching (TS) device with a transistor, but this method often entails a complex fabrication process. This work suggests a ternary gate-connected threshold switching thin-film transistor (TS-TFT) by serially connecting the TS device with a bottom-gate thin-film transistor (TFT). The fabrication process is simplified with a structure that shares electrodes and insulators. Different threshold voltages from TS and TFT devices produce stable multiple states. The Pt/HfO2/TiN TS device has an electronic trapping/detrapping switching mechanism that exhibits low power consumption and high reliability. With the superior electrical performance of an amorphous indium gallium zinc oxide TFT, the TS-TFT has stable endurance. Furthermore, pulse switching and ternary inverter are demonstrated from the practical point of view.

Innovations in thin‐film electronics for the new generation of displays

AbstractToday's display industry faces transistor‐level challenges similar to those of complementary metal‐oxide semiconductor (CMOS) metal‐oxide semiconductor field‐effect transistors (MOSFETs) in the mid‐1990s. Learnings from MOSFETs inform the display industry's response to the limitations of silicon‐based thin‐film transistors (TFTs). Improvements sustaining Moore's Law drove the need to rethink MOSFET materials and structures. The display industry needs fundamental innovation at the device level. New thin‐film devices enable an inflection point in the use of displays, just as fin field‐effect transistor (FinFET) defined the inflection point in CMOS in the 2000s. This paper outlines two innovations in thin‐film device technology that offers improvement in image quality and power consumption of flat panel displays: amorphous metal gate TFTs (AMeTFTs) and amorphous metal nonlinear resistors (AMNRs). Linked through a single core material set based on mass‐producible, thin‐film amorphous metals, these two innovations create near‐ and long‐term roadmaps simplifying the production of high‐image quality, low‐power consumption displays on glass (now) and plastic (future). In particular, the field‐effect mobility of indium gallium zinc oxide (IGZO) AMeTFTs (55–72 cm2/Vs) exceeds that of IGZO TFTs developed by existing display manufacturers without the need for atomic layer deposition or vertical stacking of heterostructure semiconductor films, making AMeTFTs a natural choice for the new G8.5–G8.7 fabs targeting IGZO backplanes.

Effect of sputtering working pressure on the reliability and performance of amorphous indium gallium zinc oxide thin film transistors

In this study, the reliability and electrical properties of indium gallium zinc oxide (IGZO) thin film transistors (TFTs) are investigated when the working pressure of the sputtering system is varied. As IGZO is deposited at a low working pressure, the sputtering yield increases and the film density increases from 5.84 to 6.00 g/cm3 based on x-ray reflectivity measurements. IGZO TFT sputtered at low working pressure has a mobility of 8.05 cm2/V s, a threshold voltage of 1.25 V, and a subthreshold swing of 0.25 V/dec. In addition, x-ray photoelectron spectroscopy analysis shows that the oxygen content in the film decreases when IGZO is deposited at a low working pressure, resulting in improved positive bias stress reliability due to the oxygen-poor film. Furthermore, the IGZO film deposited at a low working pressure effectively prevents the formation of defects caused by the environment such as H2O molecules.

A low-temperature photoresist-based film-profile engineering scheme for fabricating bottom- and double-gated indium–gallium–zinc oxide TFTs

We proposed a novel low-temperature (<110 °C) process scheme based on the film-profile engineering technique for fabricating indium–gallium–zinc oxide thin-film transistors (TFTs) with both bottom-gated (BG) and double-gated (DG) configurations. An organic photoresist (PR) suspended bridge is constructed to shadow the depositing species during the deposition processes of the bottom gate-oxide, channel, and source/drain metal films. An Al2O3 layer deposited at 110 °C using atomic-layer deposition is employed as the bottom gate-oxide layer. Such a low-temperature process allows us to deposit the Al2O3 layer following the formation of the PR suspended bridge, preventing the formation of organic residues between the gate-oxide and channel layers. As a result, excellent device performance in terms of field-effect mobility of 12.1 cm2 V−1 s−1 and subthreshold swing of 141 mV/dec is achieved. Our proposed low-temperature process scheme is readily applicable for fabricating DG TFTs which show substantial enhancements in driving currents.

Charge transport properties of high-mobility indium–gallium–zinc oxide thin-film transistors fabricated through atomic-layer deposition

Charge transport properties of indium–gallium–zinc oxide thin-film transistors fabricated by atomic-layer deposition are investigated through comparative analyses based on steady-state DC and time-domain transient measurements.

Effect of Channel Shape on Performance of Printed Indium Gallium Zinc Oxide Thin-Film Transistors.

Printing technology will improve the complexity and material waste of traditional deposition and lithography processes in device fabrication. In particular, the printing process can effectively control the functional layer stacking and channel shape in thin-film transistor (TFT) devices. We prepared the patterning indium gallium zinc oxide (IGZO) semiconductor layer with Ga, In, and Zn molar ratios of 1:2:7 on Si/SiO2 substrates. And the patterning source and drain electrodes were printed on the surface of semiconductor layers to construct a TFT device with the top contact and bottom gate structures. To overcome the problem of uniform distribution of applied voltages between electrode centers and edges, we investigated whether the circular arc channel could improve the carrier regulation ability under the field effect in printed TFTs compared with a traditional structure of rectangular symmetry and a rectangular groove channel. The drain current value of the IGZO TFT with a circular arc channel pattern was significantly enhanced compared to that of a TFT with rectangular symmetric source/drain electrodes under the corresponding drain-source voltage and gate voltage. The field effect properties of the device were obviously improved by introducing the arc-shaped channel structure.

Rapid thermal annealing effect on performance variations of solution processed indium–gallium–zinc-oxide thin-film transistors

In this paper, the 1 min annealing effect on the electrical characteristics of solution-processed amorphous indium–gallium–zinc-oxide thin-film transistors (a-IGZO TFTs) was analyzed in an ambient gas environment comprising He, Ar, N2, and O2 and an annealing temperature range from 400 to 600 °C for different active layer thicknesses. Even for the short annealing time of 1 min, the He-annealed TFTs show good performance with a threshold voltage of −1.27 V, a subthreshold slope of 605 mV/dec, and a field-effect mobility of 7.19 cm2/Vs under the thick active layer condition. The resulting good performance of the He-annealed TFT originates from the high thermal velocity of the He atom, which can be confirmed from the x-ray photoelectron spectroscopic measurement by the sharp definition of the active layer near the a-IGZO/gate insulator interface.

Insight into the evolution of electrical properties for Schottky-barrier IGZO thin-film transistors with Cu-based Schottky contacts

In this work, we performed systematic electrical characterization and analysis of indium–gallium–zinc oxide (IGZO) Schottky-barrier thin-film transistors (SBTFTs) with different Cu-based Schottky contact structures. It was found that the Schottky barrier height (ΦB) between the IGZO layer and the Cu electrode could be modulated notably by changing the thickness of the AlOx tunnel layer, and the variation in ΦB significantly changed the saturation drain current (Idsat) of the IGZO SBTFTs based on the Schottky contacts but only had a minor influence on the saturation voltage (Vdsat) of the devices. Furthermore, Cu/Al stacked source/drain electrodes and silicon nitride (SiNx) passivation were employed to tailor the contact resistance and channel resistance of the IGZO SBTFTs, which led to an increase in Idsat and a variation in Vdsat. A universal resistance–capacitance network model was proposed to explain the observed evolution of Vdsat of the SBTFTs with different device structures. This work provides meaningful insight into developing low-cost metal oxide SBTFTs with tailored device performances.

Enhancing photodetection performance of UV photodetectors with stacked Pt/NiO dual capping layers on IGZO thin-film transistors

This paper proposes a solution to mitigate the trade-off between dark and photocurrents in the indium gallium zinc oxide (IGZO) thin-film transistor (TFT) applications, such as ultraviolet photodetectors, by using a stacked Pt/NiO dual capping layer (CL). The Pt CL forms a Schottky contact with the IGZO channel, which maximizes the depletion width on the channel layer and allows the use of a thicker channel to suppress both dark current and channel resistance. On the other hand, the NiO CL forms a pn heterojunction with the IGZO channel, which provides additional space for generating electron–hole pairs and is forward biased by the photovoltaic voltage under UV irradiation, resulting in a further negative shift in the threshold voltage and a significant increase in photocurrent. Experimental results show that the proposed CL scheme exhibits excellent photoresponsivity, photosensitivity, and specific detectivity in a 40 nm-thick IGZO TFT, with the values of 1888 A/W, 3.37 × 108 A/A, and 3.99 × 1016 Jones, respectively, which are about 55%, 83%, and 68% higher than a traditional 30 nm-thick IGZO TFT using only NiO CL under 275 nm UV irradiation.